CN101986621A - Data mapping method and device - Google Patents

Data mapping method and device Download PDF

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Publication number
CN101986621A
CN101986621A CN2010105366001A CN201010536600A CN101986621A CN 101986621 A CN101986621 A CN 101986621A CN 2010105366001 A CN2010105366001 A CN 2010105366001A CN 201010536600 A CN201010536600 A CN 201010536600A CN 101986621 A CN101986621 A CN 101986621A
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data
buffer
justification
reading
read
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刘学斌
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ZTE Corp
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ZTE Corp
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Priority to CN2010105366001A priority Critical patent/CN101986621A/en
Publication of CN101986621A publication Critical patent/CN101986621A/en
Priority to PCT/CN2011/073839 priority patent/WO2012062093A1/en
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00Traffic control in data switching networks
    • H04L47/50Queue scheduling
    • H04L47/62Queue scheduling characterised by scheduling criteria
    • H04L47/621Individual queue per connection or flow, e.g. per VC

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  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

The invention discloses a data mapping method and a data mapping device. The method comprises the following steps of: writing the constant bit rate (CBR) into a plurality of buffers, wherein the number of the buffers is same as that of parallelly processed bytes, and data quantity written in each buffer is same; when data is read from the buffers according to indication information, continuously performing positive justification or negative justification on the data read from each buffer one by one, wherein the indication information is used for indicating the quantity of data stored in each buffer; and performing registration on the read data subjected to positive justification or negative justification so as to map the data into data of an optical channel payload unit (OPUk). Through the method and the device, the single byte justification of a multi-byte parallel processing circuit is realized.

Description

Data mapping method and device
Technical field
The present invention relates to the communications field, in particular to a kind of data mapping method and device.
Background technology
Optical transfer network (Optical Transport Network abbreviates OTN as) is the network that transmits of future generation.G.709 two kinds of patterns that use OTN transmission frame transmits SDH (Synchronous Digital Hierarchy) (Synchronous Digital Hierarchy abbreviates SDH as) data have been defined: synchronous mode, asynchronous mode.Wherein, in asynchronous mode, the OTN frame provides three to adjust control (JC) bytes, negative justification opportunity (NJO) byte and a positive justification opportunity (PJO) byte.Adjust control signal (JC) and be positioned at the 1st to 3 row the 16th row, its 7th and the 8th is used for controlling two adjustment chance byte N JO and PJO.Do negative justification when client signal speed is higher than light path Payload Unit (Optical Channel Payload Unit abbreviates OPU as) k nominal value, NJO and PJO are data byte, and control signal JC is 01; Do positive justification when client signal speed is lower than the OPUk nominal value, NJO and PJO should be the adjustment byte, and control signal JC is 11.
In correlation technique, use special chip or FPGA to realize the mapping of fixed rate data (Constant Bit Rate abbreviates CBR as) usually to OPUk.Way commonly used is to use first in first out (First Input First Output, abbreviate FIFO as) finish, expire state soon according to the fast sky of FIFO and produce positive negative justification indication, FIFO produces the positive justification index signal when empty soon, and FIFO produces the negative justification index signal when expiring soon.But because the signal rate of special chip and FPGA inside restriction, causing the CBR signal must be parallel work-flow at chip internal, bit wide is normally greater than a byte (8bit), adjusting byte all is byte, in correlation technique, in the circuit of multibyte parallel processing, do not realize the adjustment of byte.
Summary of the invention
Main purpose of the present invention is to provide a kind of data map scheme, to address the above problem at least.
According to an aspect of the present invention, a kind of data mapping method is provided, has comprised: the fixed rate data cbr has been written in a plurality of buffers, wherein, the quantity of described buffer is identical with the byte quantity of parallel processing, and the data volume that writes each buffer is identical; When the reading of data from described buffer, the data that read are carried out positive justification or negative justification continuously one by one according to indication information from described each buffer, wherein, what of described buffer storage data described indication information be used for indicating; The data of carrying out reading after positive justification or the negative justification are spliced, to be mapped to light path Payload Unit OPUk data.
Further, according to described indication information when the reading of data from described buffer, the data that read from described each buffer are carried out positive justification or negative justification continuously one by one to be comprised: when described indication information indicates the data of storing in the described buffer to exceed first threshold, when reading of data from described buffer, the data that read are carried out negative justification continuously one by one from described each buffer; When described indication information indicates the data of storing in the described buffer to be lower than second threshold value, when reading of data from described buffer, the data that read are carried out positive justification continuously one by one from described each buffer.
Further, the data of carrying out reading after positive justification or the negative justification are spliced comprise: the data of carrying out reading after described positive justification or the negative justification are spliced according to the splicing indication information, wherein, described splicing indication information is used in reference to the buffer that positive justification or negative justification take place when being shown in reading of data.
Further, after the data of carrying out reading after positive justification or the negative justification were spliced, also comprise: the data after will splicing were put into the payload section of OPUk frame, and insert expense.
Further, determine the byte quantity of described parallel processing and the quantity of described buffer according to the data rate of fixed rate data and the frequency of processing clock.
According to a further aspect in the invention, also provide a kind of data mapping unit, having comprised: a plurality of buffers, be used for the fixed rate data cbr that buffer memory writes, the quantity of described buffer is identical with the byte quantity of parallel processing, and the data volume that writes each buffer is identical; Read-write controller, be used for according to the indication information of described buffer generating the time from described buffer reading of data, the data that read from described each buffer are carried out positive justification or negative justification continuously one by one, wherein, what of described buffer storage data described indication information be used for indicating; The data splicing device is used for the data of carrying out reading after positive justification or the negative justification are spliced, to be mapped to light path Payload Unit OPUk data.
Further, described read-write controller is used for when the data that described indication information indicates described buffer to store exceed first threshold, when reading of data from described buffer, the data that read from described each buffer is carried out negative justification continuously one by one; And when described indication information indicates the data of storing in the described buffer to be lower than second threshold value, when reading of data from described buffer, the data that read are carried out positive justification continuously one by one from described each buffer.
Further, described data splicing device is used for according to the splicing indication information data of carrying out reading after described positive justification or the negative justification being spliced, and wherein, described splicing indication information is used in reference to the buffer that positive justification or negative justification take place when being shown in reading of data.
Further, said apparatus also comprises: the OPUk framer is used for the data after splicing are put into the payload section of OPUk frame, and inserts expense.
Further, the quantity of the byte quantity of described parallel processing and described buffer is to determine according to the data rate of fixed rate data and the frequency of processing clock.
By the present invention, adopt the fixed rate data cbr is written in a plurality of buffers, wherein, the quantity of buffer is identical with the byte quantity of parallel processing, and the data volume that writes each buffer is identical; When the reading of data from buffer, the data that read are carried out positive justification or negative justification continuously one by one according to indication information from each buffer, wherein, what of buffer storage data indication information be used for indicating; The data of carrying out reading after positive justification or the negative justification are spliced, to be mapped to light path Payload Unit OPUk data, solve the problem that in correlation technique, in the circuit of multibyte parallel processing, does not realize the adjustment of byte, realized the byte adjustment of multibyte parallel processing circuit.
Description of drawings
Accompanying drawing described herein is used to provide further understanding of the present invention, constitutes the application's a part, and illustrative examples of the present invention and explanation thereof are used to explain the present invention, do not constitute improper qualification of the present invention.In the accompanying drawings:
Fig. 1 is the flow chart according to the data mapping method of the embodiment of the invention;
Fig. 2 is the schematic diagram according to the data mapping unit of the embodiment of the invention;
Fig. 3 is the flow chart according to the preferred data mapping method of the embodiment of the invention.
Embodiment
Hereinafter will describe the present invention with reference to the accompanying drawings and in conjunction with the embodiments in detail.Need to prove that under the situation of not conflicting, embodiment and the feature among the embodiment among the application can make up mutually.
Fig. 1 is the flow chart according to the data mapping method of the embodiment of the invention, and as shown in Figure 1, this flow process comprises the steps:
Step S102 is written to the fixed rate data cbr in a plurality of buffers, and wherein, the quantity of buffer is identical with the byte quantity of parallel processing, and the data volume that writes each buffer is identical;
Step S104 when the reading of data from buffer, continuously one by one carries out positive justification or negative justification to the data that read according to indication information from each buffer, wherein, what of buffer storage data indication information be used for indicating;
Step S106 splices the data of carrying out reading after positive justification or the negative justification, to be mapped to light path Payload Unit OPUk data.
Pass through above-mentioned steps, adopted the buffer identical to carry out buffer memory with parallel processing byte quantity, then in positive justification or the negative justification buffer carried out one by one, thereby solve the problem that in correlation technique, in the circuit of multibyte parallel processing, does not realize the adjustment of byte.
Preferably, when implementing, can send fast full or fast empty indication (these indications can be referred to as indication information), control and carry out positive justification or negative justification.Fast full or fast empty judgement can be carried out according to threshold ratio mode, can certainly adopt other mode.Below threshold ratio mode is illustrated.
When the data of storing exceed first threshold (for example, 80%), when reading of data from buffer, the data that read are carried out negative justification continuously one by one from each buffer in indication information indication buffer; When the data of storing are lower than second threshold value (for example, 10%), when reading of data from buffer, the data that read are carried out positive justification continuously one by one from each buffer in indication information indication buffer.
Preferably, when splicing, can splice the data of carrying out reading after positive justification or the negative justification according to the splicing indication information, wherein, the splicing indication information is used in reference to the buffer that positive justification or negative justification take place when being shown in reading of data.
Preferably, can determine the gentle quantity of byte quantity of parallel processing according to the frequency of the data rate of fixed rate data and processing clock towards device, for example, the data rate of 10G, the 311M processing clock, the gentle data towards device of the byte quantity of parallel processing this moment are 4; Again for example, if the speed of 10G, the 155M clock is handled, and the gentle data towards device of the byte quantity of parallel processing this moment are 8.
Fig. 2 is the schematic diagram according to the data mapping unit of the embodiment of the invention, and as shown in Figure 2, this device comprises: a plurality of buffers, read-write controller, data splicing device illustrate respectively this below.
A plurality of buffers are used for the fixed rate data cbr that buffer memory writes, and the quantity of buffer is identical with the byte quantity of parallel processing, and the data volume that writes each buffer is identical; Read-write controller, be used for indication information according to buffer generating the time from the buffer reading of data, the data that read from each buffer are carried out positive justification or negative justification continuously one by one, and wherein, what of buffer storage data indication information be used for indicating; The data splicing device is used for the data of carrying out reading after positive justification or the negative justification are spliced, to be mapped to light path Payload Unit OPUk data.
Preferably, read-write controller is used for when reading of data from buffer, the data that read being carried out negative justification continuously one by one from each buffer when the data that indication information indication buffer is stored exceed first threshold; And when indication information indicates the data of storing in the buffer to be lower than second threshold value, when reading of data from buffer, the data that read are carried out positive justification continuously one by one from each buffer.
Preferably, the data splicing device is used for according to the splicing indication information data of carrying out reading after positive justification or the negative justification being spliced, and wherein, the splicing indication information is used in reference to the buffer that positive justification or negative justification take place when being shown in reading of data.
Preferably, as shown in Figure 2, this device can also comprise: the OPUk framer is used for the data after splicing are put into the payload section of OPUk frame, and inserts expense.
Below in conjunction with the device among Fig. 2 the gentle quantity towards device of the byte quantity of parallel processing being 4 preferred embodiment describes.
Data buffer
Data buffer is finished the conversion of data from the OPUk clock zone of CBR clock zone.As a preferred embodiment,, N buffer is set so if chip internal is handled according to N byte parallel.Utilize CBR to receive recovered clock and in buffer, write the CBR data, utilize the OPUk clock to read again.In said process, because reception recovered clock and OPUk clock are asynchronous clocks, read-write speed is different, and fast empty or fast full indication can appear in the state of buffer.Fast empty or expire positive justification or the negative justification that state all will trigger OPUk soon, the OPUk side can be read less accordingly or mutiread goes out a secondary data.The writing speed of each buffer is identical, and reading speed then needs according to buffer status change, all is N byte of read-write when normally reading and writing at every turn.Because the each adjustment of OPUk can only be handled a byte, and that CBR writes is unadjustable, CBR writes N byte by fixed rate, and institute thinks and prevent that a plurality of buffers from independently adjusting reading speed and causing the state confusion that present embodiment utilizes the continuous adjustment of N OPUK frame to solve this problem.
In the present embodiment, use the speed difference that 4 buffers (for example, these four buffers is numbered 1,2,3,4) are adjusted CBR and OPUK.Buffer does not have when overflowing, and buffer data is read the number order (can certainly read in proper order according to other) according to 1,2,3,4.Because 4 buffer read or write speeds are identical, when negative justification took place, 4 buffers all can produce and overflow alarm.This moment on the position of first OPUK frame NJO byte one time No. 1 buffer of mutiread; On the NJO position of second OPUK frame, read buffer one time No. 2, and the like, N buffer of an order on N NJO position, read.All the other still read and write all buffers constantly.Equally, in the time of positive justification, have only the PJO position can not loading data, corresponding data buffer be read a byte less.Present embodiment is just finished the adjustment of CBR and OPUK speed difference like this.
Read-write controller
In the present embodiment, this system controls the read/write address of each buffer with read-write controller.
Because difference can appear in each buffer address when take place adjusting, so, need it to go control to read the address according to the state of buffer.Controller also will produce the enable signal of reading of buffer, and produces positive justification indication or negative justification indication control data, thereby selects splicer correctly to work.
The data splicing device
Before not adjusting, the data of data splicing device output are according to the order of 1 to N buffer, need not concatenation.Yet, after adjusting, needing the intervention of concatenation.
In the present embodiment, be example with the negative justification, after occurring adjusting for the first time, the position that will be placed on NJO from the byte that No. 1 buffer mutiread goes out sends, then according to 2,3......N, 1 order assembly unit buffer data put into OPUK frame payload section.After occurring adjusting for the second time, the position that will be placed on NJO from the byte that No. 2 buffer mutireads go out sends, then according to 3,4......N, 1,2 order assembly unit buffer data put into OPUK frame payload section.And the like, through N adjustment, the data splicing device restPoses.Equally, in the time of positive justification, skip a data buffer, change the splicing order of other buffer in the PJO position.
The OPUk framer
In the present embodiment, system uses framer successively the payload section of putting into the OPUk frame through the data flow behind the data splicing device, inserts some expenses of OPUk again and forms rational OPUk frame.
Fig. 3 is according to the flow chart of the preferred data mapping method of the embodiment of the invention, describes below in conjunction with Fig. 3.
At first, reading buffering reads sky and reads full indication, if buffer has described control or fast full indication, then carry out PJO and NJO byte are regulated according to indication, this step cycle number of times is identical with described buffer memory byte number, when reading NJO or PJO byte, then adjust read-write, carry out the splicing of OPUk Frame then, judge whether to handle all buffers at last last buffer, if do not handle, then return and read buffering and read sky and read to indicate slowly.
As a preferred embodiment, here, by the verilog language compilation one 32 parallel-by-bit CBR mapping logic to OPUk.
The data buffering module
The dual-port ram of four 8bit width of definition.Wherein, different clocks is used in the read-write of dual-port ram, writes direction unconditionally to ram the inside write data, reads direction according to the payload position of the frame structure of OPUk read data outward.Read/write address difference according to ram produces fast empty (almost_empty) signal of ram, fast full (almost_full) signal, overflow (overflow) signal and underflow (underflow) in addition, and above-mentioned signal is used to indicate the state of ram.Under normal circumstances, ram overflow or underflow can not occur, only just can occur when the CBR signal rate departs from the bit tolerance of OPUk, and at this moment circuit can be done a reset operation to ram.
The read-write control module
The state indication of read-write control module data buffer produces various control signals.When a fast spacing wave of described buffer (almost_empty) is effective, then produce positive justification index signal (pjo_ind), when buffer produces then negative justification index signal (njo_ind) when completely signal (almost_full) is effective soon.Come of the operation of control data concatenation module with said method to NJO and PJO.
Here, control module according to the payload position index signal of OPUk frame structure and buffer state produce data buffer read enable.Under the normal condition, read to enable in the payload position generation of OPUk.When positive justification took place, the PJO byte was not loaded business datum, forbids from the data buffer reading of data; Handle because circuit is 4 byte parallels, remaining three bytes in PJO position still need reading of data to load, and therefore only produce the enable signal that reads of 3 buffers, change the address of reading of 3 buffers simultaneously.Similarly, when negative justification took place, the NJO byte needed the data of read buffers, produced the enable signal that reads of 1 buffer in the position of NJO, changed it simultaneously and read the address.Such operation is done 4 times seriatim to different buffers, and each sky falls or mutiread is got a buffer, finishes one and takes turns the adjustment operation.
The data splicing module
In the present embodiment, the realization of data splicing module divides three kinds of situations: 1. the data splicing of the data of payload section (data that do not contain the PJO position) splicing, 2.PJO position.3.NJO the data splicing of position.Here, three kinds of situations all are to determine the mode of splicing by the adjustment count status (adj_cnt promptly splices a kind of preferred implementation of indication information) of judging buffer more than.There is not when adjustment adj_cnt=0; Adj_cnt changes when taking place to adjust, and reverts to adj_cnt=0 after adjustment finishes.
Wherein, the data splicing of payload section is followed following regulation rule: select the data rd_data[31:0 that reads from buffer when the payload section data of adj_cnt=0 output] (expression is from 0 bit of the 31st bit to the); When the data of adj_cnt=1 output are chosen as 4 bytes that { rd_data[7:0], rd_data[31:8] } is spliced; When the data of adj_cnt=2 output are chosen as 4 bytes that { rd_data[15:0], rd_data[31:16] } is spliced; When the data of adj_cnt=3 output are chosen as 4 bytes that { rd_data[23:0], rd_data[31:24] } is spliced;
In the present embodiment, the data splicing of PJO position is followed following regulation rule: when no positive justification was indicated, PJO position data joining method was identical with the data splicing method of payload section.During positive justification for the first time, set adj_cnt=1, the data of low three bytes output of PJO position are selected a Senior Three byte buffer _ rd_data[31:8 of the data that read from buffer], a remaining byte can not read from buffer owing to there not being No. 4 buffers to read enable signal; Since when the indication of positive justification for the first time occurring still from the buffer reading of data, the partial buffer device still is in fast dummy status (almost_empty), so can continue to produce the indication of positive justification for the second time, set adj_cnt=2 this moment, being combined as of splicing { rd_data[7:0], rd_data[31:16] }, similar with adjusting for the first time, No. 3 buffer does not read enable signal, can not read from buffer; Positive justification for the third time in like manner, set adj_cnt=3 this moment, being combined as of splicing rd_data[15:0], rd_data[31:24]; Adj_cnt=0 is set in the 4th positive justification in like manner indication this moment, splicing be combined as rd_data[23:0]; So far positive justification loop ends has realized the first time rate adjustment.
The data splicing of NJO position is followed following regulation rule: when no negative justification was indicated, business datum was not loaded in the NJO position.Produce the indication of negative justification for the first time when buffer occurs expiring state (almost_full) soon, set adj_cnt=3 at this moment, the data of NJO position output are selected from rd_data[31:24], three remaining buffers are reading of data not; First buffer disappears through the fast full state (almost_full) of current read operation, but other also continuing to produce the negative justification index signal.During the indication of negative justification for the second time, set adj_cnt=2, the data of NJO byte output are selected rd_data[23:16].During the indication of negative justification for the third time, set adj_cnt=1, the data of NJO byte output are selected rd_data[15:8].In like manner, also be same operation during the 4th negative justification indication, set adj_cnt=0, the data of NJO byte output are selected rd_data[7:0].Through having finished negative justification circulation after four negative justification.
OPUk becomes frame module
Design a line count device, the value by the line count device makes up the frame structure of an OPUk, provide simultaneously JC and PSI expense position indication, adjust position indication and payload position indication.Become the data that frame module splice by these indications to insert payload section or adjust the position, and insert correct JC expense and insertion PSI expense according to adjusting indication.
In sum, can handle effectively in optical transfer network by the foregoing description, CBR fixed rate data are to the mapping of OPUk.
Obviously, those skilled in the art should be understood that, above-mentioned each module of the present invention or each step can realize with the general calculation device, they can concentrate on the single calculation element, perhaps be distributed on the network that a plurality of calculation element forms, alternatively, they can be realized with the executable program code of calculation element, thereby, they can be stored in the storage device and carry out by calculation element, and in some cases, can carry out step shown or that describe with the order that is different from herein, perhaps they are made into each integrated circuit modules respectively, perhaps a plurality of modules in them or step are made into the single integrated circuit module and realize.Like this, the present invention is not restricted to any specific hardware and software combination.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (10)

1. a data mapping method is characterized in that, comprising:
The fixed rate data cbr is written in a plurality of buffers, and wherein, the quantity of described buffer is identical with the byte quantity of parallel processing, and the data volume that writes each buffer is identical;
When the reading of data from described buffer, the data that read are carried out positive justification or negative justification continuously one by one according to indication information from described each buffer, wherein, what of described buffer storage data described indication information be used for indicating;
The data of carrying out reading after positive justification or the negative justification are spliced, to be mapped to light path Payload Unit OPUk data.
2. method according to claim 1 is characterized in that,, the data that read from described each buffer is carried out positive justification or negative justification continuously one by one comprise when the reading of data from described buffer according to described indication information:
When described indication information indicates the data of storing in the described buffer to exceed first threshold, when reading of data from described buffer, the data that read are carried out negative justification continuously one by one from described each buffer;
When described indication information indicates the data of storing in the described buffer to be lower than second threshold value, when reading of data from described buffer, the data that read are carried out positive justification continuously one by one from described each buffer.
3. method according to claim 1 is characterized in that, the data of carrying out reading after positive justification or the negative justification is spliced comprise:
According to the splicing indication information data of carrying out reading after described positive justification or the negative justification are spliced, wherein, described splicing indication information is used in reference to the buffer that positive justification or negative justification take place when being shown in reading of data.
4. according to each described method in the claim 1 to 3, it is characterized in that, after the data of carrying out reading after positive justification or the negative justification are spliced, also comprise:
Data after will splicing are put into the payload section of OPUk frame, and insert expense.
5. according to each described method in the claim 1 to 3, it is characterized in that, determine the byte quantity of described parallel processing and the quantity of described buffer according to the data rate of fixed rate data and the frequency of processing clock.
6. a data mapping unit is characterized in that, comprising:
A plurality of buffers are used for the fixed rate data cbr that buffer memory writes, and the quantity of described buffer is identical with the byte quantity of parallel processing, and the data volume that writes each buffer is identical;
Read-write controller, be used for according to the indication information of described buffer generating the time from described buffer reading of data, the data that read from described each buffer are carried out positive justification or negative justification continuously one by one, wherein, what of described buffer storage data described indication information be used for indicating;
The data splicing device is used for the data of carrying out reading after positive justification or the negative justification are spliced, to be mapped to light path Payload Unit OPUk data.
7. device according to claim 6, it is characterized in that, described read-write controller is used for when the data that described indication information indicates described buffer to store exceed first threshold, when reading of data from described buffer, the data that read are carried out negative justification continuously one by one from described each buffer; And when described indication information indicates the data of storing in the described buffer to be lower than second threshold value, when reading of data from described buffer, the data that read are carried out positive justification continuously one by one from described each buffer.
8. device according to claim 6, it is characterized in that, described data splicing device is used for according to the splicing indication information data of carrying out reading after described positive justification or the negative justification being spliced, wherein, described splicing indication information is used in reference to the buffer that positive justification or negative justification take place when being shown in reading of data.
9. according to each described device in the claim 6 to 8, it is characterized in that, also comprise:
The OPUk framer is used for the data after splicing are put into the payload section of OPUk frame, and inserts expense.
10. according to each described device in the claim 6 to 8, it is characterized in that the byte quantity of described parallel processing and the quantity of described buffer are to determine according to the frequency of the data rate of fixed rate data and processing clock.
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