CN101982876B - Semiconductor packaging part and manufacturing method thereof - Google Patents
Semiconductor packaging part and manufacturing method thereof Download PDFInfo
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- CN101982876B CN101982876B CN2010102863407A CN201010286340A CN101982876B CN 101982876 B CN101982876 B CN 101982876B CN 2010102863407 A CN2010102863407 A CN 2010102863407A CN 201010286340 A CN201010286340 A CN 201010286340A CN 101982876 B CN101982876 B CN 101982876B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Abstract
The invention provides a semiconductor packaging part and a manufacturing method thereof. The semiconductor packaging part comprises a first circuit structure, first semiconductor assemblies, a first dielectric layer, a through hole conductive structure, a second circuit structure, second semiconductor assemblies, a second dielectric layer and a strengthening structure, wherein the first dielectric layer covers the first semiconductor assemblies, defines a through part and is provided with a through part wall corresponding to the through part; the through hole conductive structure is formed on the through part wall and is electrically connected with the first circuit structure; the second circuit structure is electrically connected with the through hole conductive structure; the second semiconductor assemblies are arranged on the second circuit structure and are electrically connected with the through hole conductive structure; the second dielectric layer covers the second semiconductor assemblies; the strengthening structure is used for strengthening the semiconductor packaging part; and the second dielectric layer is arranged between the first circuit structure and the strengthening structure.
Description
Technical field
The invention relates to a kind of semiconductor package part and manufacture method thereof, and particularly relevant for a kind of semiconductor package part and manufacture method thereof with multi-chip.
Background technology
Traditional stack type semiconductor structure comprises two semiconductor package parts and several soldered balls.The rear docking that completes respectively of two semiconductor package parts, soldered ball also is located between two semiconductor package parts, to be electrically connected two chips in two semiconductor package parts.
Yet its amount of warpage of stack type semiconductor structure made from said method is larger.In addition, because the volume of soldered ball is larger, cause the thicker and defeated in/out contact of the thickness number of stack type semiconductor structure less.
Summary of the invention
The present invention is relevant for a kind of semiconductor package part and manufacture method thereof, the thinner thickness of semiconductor package part, and its defeated in/out contact number is more.
According to a first aspect of the invention, a kind of semiconductor package part is proposed.Semiconductor package part comprises that a First Line line structure, one first semiconductor subassembly, run through section, one first dielectric layer, a perforation conductive structure, one second line construction, one second semiconductor subassembly, one second dielectric layer and a reinforced structure.The first semiconductor subassembly is located on the First Line line structure.The first dielectric layer defines one first to be run through section and coats the first semiconductor subassembly, and the first dielectric layer has corresponding first to be run through one first of section and run through section's wall, and the First Line line structure exposes in first section of running through.The perforation conductive structure is formed at first at least to be run through on section's wall and is electrically connected at the First Line line structure.The second line construction covers the first dielectric layer and is electrically connected at the perforation conductive structure.The second semiconductor subassembly is located on the second line construction.The second semiconductor subassembly sees through the second line construction and is electrically connected at the perforation conductive structure.The second dielectric layer coats the second semiconductor subassembly.Reinforced structure is in order to strengthen the intensity of semiconductor package part, and wherein the second dielectric layer is between First Line line structure and reinforced structure.
A kind of manufacture method of semiconductor package part is proposed according to a second aspect of the invention.Manufacture method may further comprise the steps.One support plate is provided; Form a First Line line structure on support plate; One first semiconductor subassembly is set on the First Line line structure; Form one first dielectric layer and coat the first semiconductor subassembly; Form the section of running through and run through the first dielectric layer, wherein, the First Line line structure exposes in the section of running through, and the first dielectric layer has correspondence and runs through one first of section and run through section's wall; Form a perforation conductive structure, form a perforation conductive structure, wherein the perforation conductive structure is formed at least first and runs through on section's wall; Form one second line construction and cover the first dielectric layer, wherein, the second line construction is electrically connected at the perforation conductive structure; One second semiconductor subassembly is set on the second line construction, wherein, the second semiconductor subassembly is electrically connected at the second line construction; Form one second dielectric layer and coat the second semiconductor subassembly; Contiguous the second dielectric layer arranges a reinforced structure; Separate support plate and First Line line structure; And, cutting reinforced structure, the second dielectric layer, the second line construction, the first dielectric layer and First Line line structure.
For foregoing of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperation accompanying drawing are described in detail below:
Description of drawings
Fig. 1 illustrates the cutaway view of the semiconductor package part of first embodiment of the invention.
Fig. 2 A to 2B illustrates the manufacturing flow chart according to the semiconductor package part of first embodiment of the invention.
Fig. 3 A to 3J illustrates the manufacturing schematic diagram of the semiconductor package part of Fig. 1.
Fig. 4 illustrates the cutaway view according to the semiconductor package part of second embodiment of the invention.
Fig. 5 (not illustrating the 3rd dielectric layer and reinforced structure) illustrates among Fig. 4 the top view of the perforation conductive structure of watching along direction V5.
Fig. 6 illustrates the cutaway view of the semiconductor package part of another embodiment of the present invention.
Fig. 7 illustrates the top view of the perforation conductive structure that past direction V7 watches among Fig. 6.
Fig. 8 A to 8B illustrates the manufacturing flow chart according to the semiconductor package part of second embodiment of the invention.
Fig. 9 A to 9G illustrates the manufacturing schematic diagram of the semiconductor package part of Fig. 4.
The primary clustering symbol description:
100,200,300: semiconductor package part
102: the First Line line structure
102 ': semiconductor structure
102a, 102a ': the first dielectric structure
102a1,106a, 110c, 114a, 214a: upper surface
102a2: the first perforate
102b, 102b ': the first conductive structure
102s, 106s, 110s, 114s, 116s: lateral surface
104: the first semiconductor subassemblies
106,206: the first dielectric layers
106w, 206w: first runs through section's wall
108,208,308: the perforation conductive structure
110,210: the second line constructions
110a: the second dielectric structure
110b, 210b: the second conductive structure
112: the second semiconductor subassemblies
114,214: the second dielectric layers
116,216: reinforced structure
118,218: patterned line layer
118 ': metal level
118w, 218w: the 4th perforation section wall
120: electrical contact
122: the second assembly contacts
124: the first assembly contacts
126: support plate
126a: intermediate layer
126b: the first metal layer
126b1: the first support plate surface
126c: the second metal level
126c1: the second support plate surface
128, run through section at 228: the first
132, ran through section in 232: the four
208a, 308a: perforation line construction
208b: surface lines layer
210w: the second perforation section wall
214w: the 3rd perforation section wall
230,330: the three dielectric layers
236: the dielectric interstitital texture
Run through section at 238: the second
Ran through section in 240: the three
242: run through section
308b: routing layer
308b1: cabling
308b2: connection pad
332: the three semiconductor subassemblies
H: heat
P: pressure
R: packaging part district
V5, V7: direction
Embodiment
The first embodiment
Please refer to Fig. 1, it illustrates the cutaway view of the semiconductor package part of first embodiment of the invention.Semiconductor package part 100 comprises First Line line structure 102, the first semiconductor subassembly 104, the first dielectric layer 106, patterned line layer 118, perforation conductive structure 108, the second line construction 110, the second semiconductor subassembly 112, the second dielectric layer 114, reinforced structure 116 and several electrical contacts 120.Electrical contact 120 for example is soldered ball (solder ball) or projection (bump), in order to be electrically connected at an external circuit, for example is circuit board.
The second line construction 110 comprises the second dielectric structure 110a and the second conductive structure 110b, and wherein the second conductive structure 110b for example is conductive pole (conductive pillar) or cabling (trace).
The first semiconductor subassembly 104 and the second semiconductor subassembly 112 overlap up and down and form a stack architecture across the second line construction 110.Wherein, the second semiconductor subassembly 112 is located on the second line construction 110 and is had a plurality of the second assembly contacts 122.The second conductive structure 110b that the second assembly contact 122 of the second semiconductor subassembly 112 sees through the second line construction 110 is electrically connected at perforation conductive structure 108.
Compared to the stack type semiconductor structure of tradition with the soldered ball connection, the present embodiment the first semiconductor subassembly 104 and the second semiconductor subassembly 112 are electrically connected with the more tiny circuit of size (trace) structure, can dwindle the thickness of overall semiconductor packaging part 100.Moreover the thinner thickness of First Line line structure 102, the first dielectric layer 106, the second line construction 110 and the second dielectric layer 114 helps to dwindle the thickness of overall semiconductor packaging part 100.In addition, via the more tiny circuit of size (trace) structure, can form the more defeated in/out contact of number.
In addition, the first semiconductor subassembly 104 has a plurality of the first assembly contacts 124.The first semiconductor subassembly 104 for example is to cover crystalline substance (flip chip), and it is located on the First Line line structure 102 and sees through the first conductive structure 102b that the first assembly contact 124 is electrically connected at First Line line structure 102.Better but non-exclusively, the first semiconductor subassembly 104 thin chips (thin chip), its thickness between approximately 50 microns (μ m) between the 150 μ m.
Reinforced structure 116 plates (plate) are in order to strengthen the structural strength of semiconductor package part 100, to reduce the amount of warpage of semiconductor package part 100.The material of reinforced structure 116 for example is metal, and its material forms and comprises at least copper.The thickness of reinforced structure 116 is greater than 300 μ m, and so this is non-in order to limit the present invention.Better but non-exclusively, the thickness 500 μ m of reinforced structure 116.
First Line line structure 102 multilayer semiconductor structures, every layer of semiconductor structure comprises the first dielectric structure 102a and the first conductive structure 102b, wherein the first conductive structure 102b for example is conductive pole or cabling.In another enforcement aspect, First Line line structure 102 also can be the individual layer semiconductor structure.
The first dielectric layer 106 definition one first runs through section 128 and has corresponding first and runs through first of section 128 and run through the wall 106w of section.Perforation conductive structure 108 is formed at first of the first dielectric layer 106 to be run through on the wall 106w of section.First runs through the first conductive structure 102b that First Line line structure 102 exposes in section 128, makes perforation conductive structure 108 can touch the first conductive structure 102b.In addition, it is upper and be electrically connected perforation conductive structure 108 and the second conductive structure 110b that patterned line layer 118 is formed at the upper surface 106a of the first dielectric layer 106.By this, the second semiconductor subassembly 112 is electrically connected at First Line line structure 102.
Below with the manufacture method of the semiconductor package part of Fig. 2 A to 2B and Fig. 3 A to the 3J key diagram 1 of arranging in pairs or groups.Fig. 2 A to 2B illustrates the manufacturing flow chart according to the semiconductor package part of first embodiment of the invention, and Fig. 3 A to 3J illustrates the manufacturing schematic diagram of the semiconductor package part of Fig. 1.
In the step S102 of Fig. 2 A, as shown in Figure 3A, provide support plate 126.Support plate 126 for example is BT substrate (BT core), and it comprises intermediate layer 126a, the first metal layer 126b and the second metal level 126c.The first metal layer 126b and the second metal level 126c are located on relative two of intermediate layer 126a.The first metal layer 126b and the second metal level 126c for example are copper (Cu) layers.
Definition several packaging part districts R on the support plate 126.In the subsequent step, form accordingly structure in packaging part district R, and in follow-up cutting step, after carrying out cutting action along the scope of packaging part district R, can obtain several semiconductor package parts 100.
In the ensuing processing step, can be simultaneously in support plate 126, form respectively two groups of similar structures on relative the first support plate surface 126b1 and the surperficial 126c1 of the second support plate, production capacity is doubled.Below explain as example take the structure that is formed on the 126b1 of the first support plate surface.
Then, in step S104, shown in Fig. 3 B (only illustrating single package district R).Form First Line line structure 102 on the 126b1 of the first support plate surface.First Line line structure 102 multilayer semiconductor structures, its generation type is similar in appearance to the generation type of the rerouting structure (RedistributionLayer, RDL) of wafer-level packaging (Wafer-Level Packaging, WLP).The manufacture method of the semiconductor structure 102 ' that contacts with the first support plate surface 126b1 below is described.
Use coating technique and be coated with a dielectric material (not illustrating) on support plate 126; Then, use patterning techniques and form a plurality of the first perforate 102a2 on this dielectric material, to form the first dielectric structure 102a ' shown in Fig. 3 B; Then, application examples is long-pending, the electroless plating method (electroless plating) in chemical gaseous phase Shen, metallide (electrolytic plating), printing, spin coating, spraying, long-pending method (vacuumdeposition) technology of sputter (sputtering) or vacuum Shen in this way, forms an electric conducting material in the first perforate 102a2 and on the whole upper surface 102a1 of the first dielectric structure 102a; Then, use this electric conducting material of patterning techniques patterning, to form the first conductive structure 102b ' shown in Fig. 3 B.Wherein, above-mentioned coating technique for example is printing (printing), spin coating (spinning) or spraying (spraying), and above-mentioned patterning techniques for example is lithography process (photolithography), chemical etching (chemical etching), laser drill (laser drilling) or machine drilling (mechanical drilling).In addition, above-mentioned dielectric material for example is photoresist, epoxy glass-fiber-fabric prepreg (Prepreg, PP) or ABF resin (Ajinomoto Build-up Film).
Then, in step S106, shown in Fig. 3 C, several first semiconductor subassemblies 104 (Fig. 3 C only illustrates single the first semiconductor subassembly 104) are set on First Line line structure 102.The first assembly contact 124 of the first semiconductor subassembly 104 is electrically connected at the first conductive structure 102b of First Line line structure 102.
Then, in step S108, shown in Fig. 3 D, form the first dielectric layer 106 and coat the first semiconductor subassembly 104.Wherein, the part of the first dielectric layer 106 is formed between the first semiconductor subassembly 104 and the First Line line structure 102, to coat the first assembly contact 124 of the first semiconductor subassembly 104.In addition, the first dielectric layer 106 and cover the upper surface 102a1 of First Line line structure 102.
In step S108, the first dielectric layer 106 can not formed by a solid dielectric film (film type) (illustrating).Say further, step S108 may further comprise the steps: this solid dielectric film is provided, and it is formed by made from thermosetting material, for example is that PP or ABF form; Then, this solid dielectric film is located on the first semiconductor subassembly 104; Then, the metal level 118 ' of setting shown in Fig. 3 D is on this solid dielectric film, and wherein, metal level 118 ' for example is Copper Foil (foil) or copper coin (plate); Then, exert pressure P and heat H makes metal level 118 ' push this solid dielectric film on metal level 118 '.Then this solid dielectric film coats the first semiconductor subassembly 104 equably in pressurized and the rear fusing of being heated, and in solidifying first dielectric layer 106 of rear formation shown in Fig. 3 D.
Sealing (molding compound) compared to the conventional package semiconductor subassembly, the material of the first dielectric layer 106 can be to omit PP or the ABF that fills grain (fller), can reduce the tack of material cost and the formed copper layer of lifting subsequent step.
In addition, the metal level 118 ' of step S108 optionally uses, and, removes to coat the first semiconductor subassembly 104 as long as can form the first dielectric layer 106 that is, and the use of metal level 118 ' is not to limit the present invention.For instance, when the first dielectric layer 106 adhesive material, the use that can omit metal level 118 '.
In addition, aspect another enforcement in, after step S106, can form first primer (underfill) between the first semiconductor subassembly 104 and First Line line structure 102, to coat the first assembly contact 124 of the first semiconductor subassembly 104; Then, execution in step S108 again.
Then, in step S110, shown in Fig. 3 E, application examples is the laser drill technology in this way, forms first and runs through section 128 and run through the first dielectric layer 106 and form the 4th and run through section 132 and run through metal level 118 '.Wherein, first runs through section 128 and the 4th and runs through the first conductive structure 102b that First Line line structure 102 exposes in section 132.First runs through section 128 and the 4th runs through after section 132 forms, and the first dielectric layer 106 forms corresponding first to be run through first of section 128 and run through the wall 106w of section, and the metal level 118 ' that is run through forms the corresponding the 4th to be run through the 4th of section 132 and run through the wall 118w of section.
Then, in step S112, use patterning techniques patterned metal layer 118 ', to form the patterned line layer 118 shown in Fig. 3 E.
Then, in step S114, shown in Fig. 3 F, use electroless plating method, formation perforation conductive structure 108 runs through the wall 106w of section and the 4th in first and runs through on the wall 118w of section (the 4th runs through the wall 118w of section is illustrated in Fig. 3 E).Wherein, perforation conductive structure 108 is connected in patterned line layer 118, and the material of perforation conductive structure 108 for example is copper.
Although the manufacture method of the semiconductor package part of the present embodiment comprises the step that forms patterned line layer 118, so this is non-in order to limit the present invention.In an enforcement aspect, after the first dielectric layer 106 forms in step S108, remove metal level 118 '; Then, in step S114, perforation conductive structure 108 more is formed on the upper surface 106a (upper surface 106a is illustrated in Fig. 3 E) of the first dielectric layer 106, replaces by this patterned line layer 118 of Fig. 3 E.In another enforcement aspect, also can form the first dielectric layer 106 under the metal level 118 ' must not using, in the case, can be in forming again patterned line layer 118 shown in Fig. 3 E behind the step S108 on the first dielectric layer 106.
Then, in the step S116 of Fig. 2 B, shown in Fig. 3 G, form the second line construction 110 and cover the first dielectric layer 106, perforation conductive structure 108 and patterned line layer 118.Wherein, the formation method of the second line construction 110 does not repeat them here similar in appearance to First Line line structure 102.
The second line construction 110 comprises the second dielectric structure 110a and the second conductive structure 110b.The second conductive structure 110b electrical contact of the second line construction 110 is in patterned line layer 118.The formation method of the second dielectric structure 110a is similar in appearance to the formation method of the first dielectric layer 106 of Fig. 3 D, and the second line construction 110 can be used semi-additive process (Semi Additive Process, SAP), plating or method for sputtering formation.
Then, in step S118, shown in Fig. 3 H, application chip joining technique (die bonding), several second semiconductor subassemblies 112 (Fig. 3 H only illustrates single the second semiconductor subassembly 112) are set on the second line construction 110, to form the stack type semiconductor structure.Wherein, the second assembly contact 122 of the second semiconductor subassembly 112 is electrically connected at the second conductive structure 110b of the second line construction 110.
In addition, aspect an enforcement in, after step S118, can form a primer (underfill) (not illustrating) between the second semiconductor subassembly 112 and the second line construction 110, to coat the second assembly contact 122 of the second semiconductor subassembly 112.
Then, in step S120, shown in Fig. 3 I, form the second dielectric layer 114 and coat the second semiconductor subassembly 112.Wherein, the part of the second dielectric layer 114 is formed between the second semiconductor subassembly 112 and the second line construction 110, to coat the second assembly contact 122 of the second semiconductor subassembly 112.In addition, the second dielectric layer 114 covers the upper surface 110c of the second line construction 110.
The formation method of the second dielectric layer 114 is not repeated similar in appearance to the formation method of the first dielectric layer 106 of Fig. 3 D.
Then, in step S122, shown in Fig. 3 J, application examples is pasted mode in this way, reinforced structure 116 is set on the upper surface 114a of the second dielectric layer 114.
Then, in step S124, separate support plate 126 and First Line line structure 102, to expose First Line line structure 102.When support plate 126 with after First Line line structure 102 separates, formed structure still firmly is incorporated into together among the step S104 to S122.
Then, in step S126, along the position (along the scope of packaging part district R) between those first semiconductor subassemblies 104, cutting reinforced structure 116, the second dielectric layer 114, the second line construction 110, the first dielectric layer 106 and First Line line structure 102.
Reinforced structure 116, second dielectric layer 114, second line construction 110, first dielectric layer 106 and the First Line line structure 102 of cutting path through overlapping, lateral surface 116s, lateral surface 114s, the lateral surface 110s of the second line construction 110, the lateral surface 106s of the first dielectric layer 106 and the lateral surface 102s of First Line line structure 102 of the second dielectric layer 114 of the reinforced structure 116 after the cutting are trimmed in fact, i.e. lateral surface 116s, 114s, 110s, 106s and 102s copline haply.
In addition, after step S124 or S126, formation electrical contact 120 as shown in Figure 1 is on the first conductive structure 102b ' of the First Line line structure 102 that exposes, to form semiconductor package part 100 as shown in Figure 1.
The second embodiment
Please refer to Fig. 4, it illustrates the cutaway view according to the semiconductor package part of second embodiment of the invention.The part that is basically the same as those in the first embodiment among the second embodiment adopts same numeral, does not repeat them here.Semiconductor package part 100 differences of the semiconductor package part 200 of the present embodiment and the first embodiment are, the second line construction 210 of semiconductor package part 200 and the second dielectric layer 214 all define the section of running through.
Semiconductor package part 200 comprises First Line line structure 102, the first semiconductor subassembly 104, the first dielectric layer 206, patterned line layer 218, perforation conductive structure 208, the second line construction 210, the second semiconductor subassembly 112, the second dielectric layer 114, the 3rd dielectric layer 230, reinforced structure 216, dielectric interstitital texture 236 and several electrical contacts 120.
The first dielectric layer 206 definition first runs through section 228 and has corresponding first and runs through first of section 228 and run through the wall 206w of section, the second line construction 210 definition second runs through section 238 and has corresponding second and runs through second of section 238 and run through the wall 210w of section, the second dielectric layer 214 definition the 3rd runs through section 240 and has the corresponding the 3rd and runs through the 3rd of section 240 and run through the wall 214w of section, runs through the 4th of section 232 and runs through the wall 218w of section and patterned line layer 218 definition the 4th run through section 232 and have the corresponding the 4th.
First runs through section 228, second runs through section 238, the 3rd and runs through section 240 and the 4th and run through section 232 1 and run through section 242 (being illustrated in Fig. 9 E) it once runs through the first dielectric layer 206, the second line construction 210, the second dielectric layer 214 and patterned line layer 218 rear formation.In other embodiment, first runs through section 228, second runs through section 238, the 3rd and runs through section 240 and the 4th and run through section 232 and also can form respectively.
The 3rd dielectric layer 230 covers the second dielectric layer 214.Reinforced structure 216 contiguous the second dielectric layers 214 are located on the 3rd dielectric layer 230, and reinforced structure 216 no longer repeats to give unnecessary details at this similar in appearance to the reinforced structure 116 of the first embodiment.
The material dielectric medium of dielectric interstitital texture 236 for example is ABF or PP, and it fills up first and runs through section 228, second and run through section 238, the 3rd and run through section 240 and the 4th and run through section 232.
Perforation conductive structure 208 comprises perforation line construction 208a and surface lines layer 208b.Perforation line construction 208a is formed at first to be run through the wall 206w of section, second and runs through the wall 210w of section, the 3rd and run through the wall 214w of section and the 4th and run through on the wall 218w of section.Surface lines layer 208b is formed on the upper surface 214a of the second dielectric layer 214.Please refer to Fig. 5 (not illustrating the 3rd dielectric layer and reinforced structure), it illustrates among Fig. 4 the top view of the perforation conductive structure of watching along direction V5.Surface lines layer 208b is around perforation line construction 208a.
Please refer to Fig. 6 (not illustrating the 3rd dielectric layer and reinforced structure) and Fig. 7, Fig. 6 illustrates the cutaway view of the semiconductor package part of another embodiment of the present invention, and Fig. 7 illustrates the top view of the perforation conductive structure that past direction V7 watches among Fig. 6.As shown in Figure 6, the perforation conductive structure 308 of semiconductor package part 300 comprises perforation line construction 308a and routing layer 308b, and routing layer 308b is electrically connected at perforation line construction 308a.Wherein, routing layer 308b is formed on the upper surface 214a of the second dielectric layer 214.As shown in Figure 7, routing layer 308b comprises several cablings 308b1 and several connection pads 308b2, and every cabling 308b1 connects corresponding connection pad 308b2.In addition, the position of connection pad 308b2 is corresponding to the zone of being located in of the second semiconductor subassembly 112, that is, the zone of being located in of the position of connection pad 308b2 and the second semiconductor subassembly 112 overlaps, and uses forming fan-in type (fan-in) structure.
In addition, the 3rd semiconductor subassembly 332 can be set and go up and be electrically connected at connection pad 308b2 in connection pad 308b2.In the case, the 3rd dielectric layer 330 more coats the 3rd semiconductor subassembly 332 except covering the second dielectric layer 214.
Below with the flow chart of Fig. 8 A to 8B and Fig. 9 A to 9G that arranges in pairs or groups the manufacture method of the semiconductor package part 200 of Fig. 4 is described.Fig. 8 A to 8B illustrates the manufacturing flow chart according to the semiconductor package part of second embodiment of the invention, and Fig. 9 A to 9G illustrates the manufacturing schematic diagram of the semiconductor package part of Fig. 4.
In the manufacture method of semiconductor package part 200, step S102 to S108 no longer repeats to give unnecessary details at this similar in appearance to the manufacture method of the semiconductor package part 100 of the first embodiment, below begins explanation from step S210.
In the step S210 of 8A figure, shown in Fig. 9 A, form patterned line layer 218 on the first dielectric layer 206.The formation method of the first dielectric layer 206 is not repeated similar in appearance to the formation method of the first dielectric layer 106 of Fig. 3 D.
Then, in step S212, shown in Fig. 9 B, form the second line construction 210 overlay pattern line layers 218 and the first dielectric layer 206.
Then, in step S214, shown in Fig. 9 C, the second semiconductor subassembly 112 is set on the second line construction 210.Wherein, the second semiconductor subassembly 112 is electrically connected at the second conductive structure 210b of the second line construction 210.
Then, in step S216, shown in Fig. 9 D, form the second dielectric layer 214 and coat the second semiconductor subassembly 112.
Then, in the step S218 of 8B figure, shown in Fig. 9 E, formation one runs through section 242 and once runs through the second dielectric layer 214, the second line construction 210, patterned line layer 218 and the first dielectric layer 206.Run through after section 242 forms, the first dielectric layer 206, the second line construction 210, the second dielectric layer 214 and patterned line layer 218 form respectively first and run through section 228, second and run through section 238, the 3rd and run through section 240 and the 4th and run through section 232.Wherein, the first dielectric layer 206 has corresponding first and runs through first of section 228 and run through the wall 206w of section, the second line construction 210 and have corresponding second and run through second of section 238 and run through the wall 210w of section, the second dielectric layer 214 and have the corresponding the 3rd and run through the 3rd of section 240 and run through the wall 214w of section, patterned line layer 218 and have the corresponding the 4th and run through the 4th of section 232 and run through the wall 218w of section.
Although first of the present embodiment runs through section 228, second and runs through section 238, the 3rd and run through section 240 and the 4th and run through section 232 once to form example explanation, so this is non-in order to limit the present invention.In other enforcement aspect, first runs through section 228, second runs through section 238, the 3rd and runs through section 240 and the 4th and run through section 232 and also can form respectively.
Then, in step S220, shown in Fig. 9 F, application examples is electroless plating method in this way, forms perforation conductive structure 208.Wherein, perforation conductive structure 208 comprises perforation line construction 208a and surface lines layer 208b.Perforation line construction 208a covers first to be run through the wall 206w of section, second and runs through the wall 210w of section, the 3rd and run through the wall 214w of section and the 4th and run through the wall 218w of section, and surface lines layer 208b is formed on the upper surface 214a of the second dielectric layer 214.
In addition, in another embodiment, the routing layer 308b of semiconductor package part 300 as shown in Figure 6 can finish in this step S220; Then, behind subsequent step S222, setting the 3rd semiconductor subassembly 332 as shown in Figure 6 is on the connection pad 308b2 of routing layer 308b; Then, in subsequent step S224, the 3rd dielectric layer 330 that forms as shown in Figure 6 covers the second dielectric layer 214 and coats the 3rd semiconductor subassembly 332.
After the step S220, enter step S222, shown in Fig. 9 G, form dielectric interstitital texture 236 in the section of running through 242.
Then, in step S224, the 3rd dielectric layer 230 that forms as shown in Figure 4 covers the second dielectric layer 214.
Then, in step S226, setting reinforced structure 216 as shown in Figure 4 is on the second dielectric layer 214.
Then, in step S228, separate support plate 126 and First Line line structure 102.When support plate 126 with after First Line line structure 102 separates, formed structure still firmly is incorporated into together among the step S204 to S226.
Then, in step S228, along the position (along the scope of packaging part district R) between those first semiconductor subassemblies 104, cutting reinforced structure 216, the 3rd dielectric layer 230, the second dielectric layer 214, the second line construction 210, the first dielectric layer 206 and First Line line structure 102.
Reinforced structure 216, three dielectric layer 230, second dielectric layer 214, second line construction 210, first dielectric layer 206 and the First Line line structure 102 of cutting path through overlapping trims lateral surface, the lateral surface of the 3rd dielectric layer 230, the lateral surface of the second dielectric layer 214, the lateral surface of the second line construction 210, the lateral surface of the first dielectric layer 206 and the lateral surface of First Line line structure 102 of the reinforced structure 216 after the cutting haply.
In addition, after step S228 or S230, formation electrical contact 120 as shown in Figure 4 is on First Line line structure 102.So far, formation semiconductor package part 200 as shown in Figure 4.
In sum, although the present invention discloses as above with preferred embodiment, so it is not to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (14)
1. semiconductor package part comprises:
One First Line line structure;
One first semiconductor subassembly is located on this First Line line structure;
One first dielectric layer defines one first and runs through section and coat this first semiconductor subassembly, and this first dielectric layer has and runs through section's wall to should first running through one first of section, and this First Line line structure exposes in this first section of running through;
One perforation conductive structure is formed at least this and first runs through on section's wall and be electrically connected at this First Line line structure;
One second line construction covers this first dielectric layer and is electrically connected at this perforation conductive structure;
One second semiconductor subassembly is located on this second line construction, and this second semiconductor subassembly sees through this second line construction and is electrically connected at the perforation conductive structure;
One second dielectric layer coats this second semiconductor subassembly; And
One reinforced structure, in order to strengthen the intensity of this semiconductor package part, wherein this second dielectric layer is between this First Line line structure and this reinforced structure.
2. semiconductor package part as claimed in claim 1, wherein this perforation conductive structure more is formed on the upper surface of this first dielectric layer.
3. semiconductor package part as claimed in claim 1, wherein this second line construction defines one second and runs through section and have and run through section's wall to should second running through one second of section, and this second dielectric layer defines one the 3rd to be run through section and have and run through section's wall to should the 3rd running through one the 3rd of section;
Wherein, this perforation conductive structure more is formed at this and second runs through section's wall and the 3rd and run through on section's wall.
4. semiconductor package part as claimed in claim 3 more comprises:
One the 3rd dielectric layer covers this second dielectric layer;
Wherein, this reinforced structure is located on the 3rd dielectric layer.
5. semiconductor package part as claimed in claim 3 more comprises:
One patterned line layer is formed on the upper surface of this first dielectric layer, and this patterned line layer defines one the 4th and runs through section and have and run through section's wall to should the 4th running through one the 4th of section, and this perforation conductive structure more is formed at the 4th and runs through section's wall.
6. semiconductor package part as claimed in claim 3, wherein this perforation conductive structure comprises a perforation line construction and a routing layer, this routing layer is connected in this perforation line construction, this perforation line construction is formed at that this first runs through section's wall, this second runs through section's wall and the 3rd and run through on section's wall, and this routing layer is formed on the upper surface of this second dielectric layer.
7. semiconductor package part as claimed in claim 6, wherein this routing layer comprises a cabling and a connection pad, this connection pad is connected in this cabling and is positioned at the zone of being located in of this second semiconductor subassembly.
8. the manufacture method of a semiconductor package part comprises:
One support plate is provided;
Form a First Line line structure on this support plate;
One first semiconductor subassembly is set on this First Line line structure;
Form one first dielectric layer and coat this first semiconductor subassembly;
Form the section of running through and run through this first dielectric layer, wherein, this First Line line structure exposes in this section of running through, and this first dielectric layer has and runs through section's wall to running through one first of section;
Form a perforation conductive structure, this perforation conductive structure is formed at this at least first to be run through on section's wall;
Form one second line construction and cover this first dielectric layer, wherein this second line construction is electrically connected at this perforation conductive structure;
One second semiconductor subassembly is set on this second line construction, wherein this second semiconductor subassembly is electrically connected at this second line construction;
Form one second dielectric layer and coat this second semiconductor subassembly;
Contiguous this second dielectric layer arranges a reinforced structure;
Separate this support plate and this First Line line structure; And
Cut this reinforced structure, this second dielectric layer, this second line construction, this first dielectric layer and this First Line line structure.
9. manufacture method as claimed in claim 8 wherein comprises in this step that forms this first dielectric layer:
One solid dielectric film is set on this first semiconductor subassembly;
One metal level is set on this solid dielectric film; And
Exert pressure and heat on this metal level, make this metal level push this solid dielectric film, this solid dielectric film coats this first semiconductor subassembly after pressurized and melted by heat, to form this first dielectric layer.
10. manufacture method as claimed in claim 9 more comprises:
In exert pressure and heat on this metal level after, this metal level of patterning.
11. the manufacture method of a semiconductor package part comprises:
One support plate is provided;
Form a First Line line structure on this support plate;
One first semiconductor subassembly is set on this First Line line structure;
Form one first dielectric layer and coat this first semiconductor subassembly;
Form the section of running through and run through this first dielectric layer, wherein, this First Line line structure exposes in this section of running through, and this first dielectric layer has and runs through section's wall to running through one first of section;
Form a perforation conductive structure, this perforation conductive structure is formed at this at least first to be run through on section's wall;
Form a patterned line layer on this first dielectric layer;
One second semiconductor subassembly is set on this second line construction, wherein this second semiconductor subassembly is electrically connected at this second line construction;
Form one second dielectric layer and coat this second semiconductor subassembly;
Form one second line construction and cover this first dielectric layer, wherein this second line construction is electrically connected at this perforation conductive structure;
Wherein, in this step that forms this second line construction, this second line construction more covers this patterned line layer;
Run through in this step of section in forming this, this second line construction, this second dielectric layer and this patterned line layer are more run through in this section of running through, and wherein this second line construction has and runs through section's wall, this second dielectric layer and have and run through section's wall and this patterned line layer and have and run through section's wall to running through one the 4th of section running through one the 3rd of section running through one second of section;
In this step that forms this perforation conductive structure, this perforation conductive structure more is formed at this second to be run through section's wall, the 3rd and runs through section's wall and the 4th and run through on section's wall;
Wherein, this manufacture method more comprises:
Form one the 3rd dielectric layer and cover this second dielectric layer;
One reinforced structure is set on the 3rd dielectric layer; And
Cut this reinforced structure, the 3rd dielectric layer, this second dielectric layer, this second line construction, this first dielectric layer and this First Line line structure.
12. manufacture method as claimed in claim 11, wherein after this step that forms this perforation conductive structure, this manufacture method more comprises:
Form a dielectric interstitital texture within this runs through section.
13. manufacture method as claimed in claim 11, wherein in this step that forms this perforation conductive structure, this perforation conductive structure comprises a perforation line construction and a routing layer, this perforation line construction is formed at that this first runs through section's wall, this second runs through section's wall, the 3rd and run through section's wall and the 4th and run through on section's wall, and this routing layer is formed on the upper surface of this second dielectric layer.
14. manufacture method as claimed in claim 13, wherein in this step that forms this perforation conductive structure, this routing layer comprises a cabling and a connection pad, and this connection pad is connected in this cabling, and the position of this connection pad is corresponding to the zone of being located in of this second semiconductor subassembly.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010102863407A CN101982876B (en) | 2010-09-07 | 2010-09-07 | Semiconductor packaging part and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010102863407A CN101982876B (en) | 2010-09-07 | 2010-09-07 | Semiconductor packaging part and manufacturing method thereof |
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| CN101982876A CN101982876A (en) | 2011-03-02 |
| CN101982876B true CN101982876B (en) | 2013-03-06 |
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| CN104966709B (en) * | 2015-07-29 | 2017-11-03 | 恒劲科技股份有限公司 | Package substrate and preparation method thereof |
| CN109425812B (en) * | 2017-08-28 | 2021-03-12 | 创意电子股份有限公司 | Detection system of semiconductor packaging element and thermal barrier layer element thereof |
| CN113130468A (en) * | 2021-04-15 | 2021-07-16 | 上海安略永信信息技术有限公司 | Flip chip semiconductor package and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7396703B1 (en) * | 2003-11-20 | 2008-07-08 | Bridge Semiconductor Corporation | Method of making a semiconductor chip assembly with a bumped terminal and a filler |
| CN101819951A (en) * | 2010-05-07 | 2010-09-01 | 日月光半导体制造股份有限公司 | Base plate, semiconductor packaging piece applying same and manufacture method of base plate |
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2010
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7396703B1 (en) * | 2003-11-20 | 2008-07-08 | Bridge Semiconductor Corporation | Method of making a semiconductor chip assembly with a bumped terminal and a filler |
| CN101819951A (en) * | 2010-05-07 | 2010-09-01 | 日月光半导体制造股份有限公司 | Base plate, semiconductor packaging piece applying same and manufacture method of base plate |
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| CN101982876A (en) | 2011-03-02 |
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