CN101819951A - Base plate, semiconductor packaging piece applying same and manufacture method of base plate - Google Patents
Base plate, semiconductor packaging piece applying same and manufacture method of base plate Download PDFInfo
- Publication number
- CN101819951A CN101819951A CN201010177535A CN201010177535A CN101819951A CN 101819951 A CN101819951 A CN 101819951A CN 201010177535 A CN201010177535 A CN 201010177535A CN 201010177535 A CN201010177535 A CN 201010177535A CN 101819951 A CN101819951 A CN 101819951A
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- layer
- contacts
- dielectric protection
- metal
- substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
The invention relates to a base plate, a semiconductor packaging piece applying the same and a manufacture method of the base plate. The base plate comprises a patterning line layer, a first dielectric protection layer, a second dielectric protection layer, a metal supporting layer and a metal shielding layer. The patterning line layer is provided with a first face and a second face which are opposite. The first face is provided with a plurality of first junctions, and the second face is provided with a plurality of second junctions. The first dielectric protection layer is formed on the first face and exposes the plurality of first junctions, and the second dielectric protection layer is formed on the second face and exposes the plurality of second junctions. The metal supporting layer is burned in the second dielectric protection layer so as to strengthen the structural strength of the base plate. The metal shielding layer is clamped between the metal supporting layer and the patterning line layer.
Description
Technical field
The invention relates to a kind of substrate and use its semiconductor package part and its manufacture method, and particularly relevant for a kind of semiconductor package part and its manufacture method that has the substrate of the supporting construction that can strengthen substrate intensity and use it.
Background technology
Traditional substrate comprises base material, last patterned line layer and following patterned line layer and has the conducting perforation.Lay scope and increase output for the circuit that increases substrate and go into the contact number, last patterned line layer and down patterned line layer be formed at relative two of base material respectively, and be electrically connected to each other through the conducting perforation.One chip can be located on the substrate to form semiconductor package part.
Yet, traditional base material one monoblock plastic base, its thickness is thicker, volume is bigger, and the volume of the semiconductor package part of last formation can't effectively be dwindled.And, on base material, form the structural strength that the conducting perforation also can reduce the material plate.In the case,, need select the thicker base material of thickness for use, so will make the volume of traditional semiconductor package part effectively to dwindle in order to keep the structural strength of substrate.
Summary of the invention
The present invention is relevant for a kind of substrate and use its semiconductor package part and its manufacture method, and substrate has metal supporting layer, can strengthen the structural strength of substrate.
According to a first aspect of the invention, a kind of substrate is proposed.Substrate comprises a patterned line layer, one first dielectric protection layer, one second dielectric protection layer, a metal supporting layer and a metal shielding layer.Patterned line layer has relative one first and one second.First mask has several first contacts, and second mask has several second contacts.First dielectric protection layer is formed at first and goes up and expose those first contacts.Second dielectric protection layer is formed at second and goes up and expose those second contacts.Metal supporting layer is embedded in this second dielectric protection layer, in order to strengthen the structural strength of substrate.The metal shielding layer is located between metal supporting layer and the patterned line layer.
According to a second aspect of the invention, a kind of semiconductor package part is proposed.Semiconductor package part comprises a substrate, several soldered balls and semiconductor assembly.Substrate comprises a patterned line layer, one first dielectric protection layer, one second dielectric protection layer, a metal supporting layer and a metal shielding layer.Patterned line layer has relative one first and one second.First mask has several first contacts, and second mask has several second contacts.First dielectric protection layer is formed at first and goes up and expose those first contacts.Second dielectric protection layer is formed at second and goes up and expose those second contacts.Metal supporting layer is embedded in this second dielectric protection layer, in order to strengthen the structural strength of substrate.The metal shielding layer is located between metal supporting layer and the patterned line layer.Those soldered balls are electrically connected at those second contacts.Semiconductor subassembly is electrically connected at those first contacts.
A kind of manufacture method of substrate is proposed according to a third aspect of the invention we.Manufacture method may further comprise the steps: a support plate is provided, and support plate has one first support plate surface; Form a board structure in the first support plate surface; Separate support plate and second and paste film; And, remove second on first dielectric protection layer and paste film.Wherein, may further comprise the steps in this step that forms this board structure: a metal profile is pasted film in being arranged on this support plate via one first; Form an etch barrier (Etching Stop Layer) on metal profile; Form one and cover pattern on etch barrier; Form a patterned line layer in etch barrier on the not crested pattern covers top, wherein patterned line layer has relative one first and one second, first mask of patterned line layer has second mask of several first contacts and patterned line layer that several second contacts are arranged, and second of patterned line layer towards etch barrier; Remove and cover pattern; Form one first dielectric protection layer first in patterned line layer, first dielectric protection layer is also exposed those first contacts; Paste one second and paste film on first dielectric protection layer; Be inverted metal profile, first and paste film, patterned line layer, etch barrier, first dielectric protection layer and second and paste film, and make second to paste film and stick on the support plate; Remove first and paste film; A part that removes metal profile is to form a metal supporting layer, and metal supporting layer is exposed the part of etch barrier; Remove this part of etch barrier, to form a metal shielding layer, this metal shielding layer exposes those second contacts; Form one second dielectric protection layer in second, second dielectric protection layer is also exposed those second contacts.
For foregoing of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:
Description of drawings
Figure 1A illustrates the cutaway view according to the semiconductor package part of preferred embodiment of the present invention.
Figure 1B illustrates the top view of the patterned line layer of Figure 1A.
Fig. 2 A and 2B illustrate the manufacture method flow chart according to the substrate of preferred embodiment of the present invention.
Fig. 3 A to 3O illustrates the manufacturing schematic diagram of the substrate of Fig. 1.
Fig. 4 illustrates the top view of the board structure that past direction V1 watches among Fig. 3 O.
The primary clustering symbol description
100: semiconductor package part
102: substrate
104: the first surface processing layer
106: the second soldered balls
108: semiconductor subassembly
110: the second surface processing layer
112: patterned line layer
114: the first dielectric protection layer
116: etch barrier
118: metal profile
120: the second dielectric protection layer
122: the first
124: the second
Perforate in 126: the first
128: support plate
130: the first support plate surfaces
132: the second support plate surfaces
134,134a: cabling
Paste film at 136: the first
138: the patterning strengthening layer
146: cover pattern
Paste film at 152: the second
164: metal supporting layer
166: the part of etch barrier
172: the metal shielding layer
Perforate in 176: the second
178: the first contacts
182: the second contacts
192: the first soldered balls
194,196,198: the side
S102-S132: step
Embodiment
Preferred embodiment is below proposed as explanation of the present invention, however the content that embodiment proposed, usefulness only for illustrating, and graphicly illustrating for cooperating of drawing not is the usefulness as limit protection range of the present invention.Moreover the diagram of embodiment is also omitted unnecessary assembly, in order to clear demonstration technical characterstic of the present invention.
Please refer to Figure 1A and Figure 1B, Figure 1A illustrates the cutaway view according to the semiconductor package part of preferred embodiment of the present invention, and Figure 1B illustrates the top view of the patterned line layer of Figure 1A.Wherein, the patterned line layer 112 of Figure 1A analyses and observe direction 1A-1A ' among direction Figure 1B.
Shown in Figure 1A, semiconductor package part 100 comprises substrate 102, several second soldered balls 106 and semiconductor subassembly 108.
A wherein cabling 134a of those cablings 134 is electrically connected at patterning strengthening layer 138.Patterning strengthening layer 138 can be electrically connected at an earth terminal (not illustrating), makes cabling 134a become ground connection (grounding) cabling.
Having 178, the second 124 of several first contacts for first 122 has several second contact, 182, the first contacts 178 and second contact 182 and is defined in respectively in the cabling 134 on relative two surfaces.Wherein, first contact 178 on every cabling 134 and second contact 182 distance that can stagger along the bearing of trend of patterned line layer 112.
First dielectric protection layer 114 has several first perforates 126, and those first contacts 178 are exposed in those first perforates 126 accordingly.Second dielectric protection layer 120 has several second perforates 176, and those second contacts 182 are exposed in those second perforates 176 accordingly.First contact 178 and second contact 182 become electrical contact relative two in the substrate 102 respectively.
Below explanation forms the manufacture method of the substrate of Figure 1A.Please refer to Fig. 2 A and 2B and Fig. 3 A to 3O, Fig. 2 A and 2B illustrate the manufacture method flow chart according to the substrate of preferred embodiment of the present invention, and Fig. 3 A to 3O illustrates the manufacturing schematic diagram of the substrate of Figure 1A.
In the step S102 of Fig. 2 A, as shown in Figure 3A, provide support plate 128.Support plate 128 has the relative 130 and second support plate surface 132, first support plate surface.Wherein, support plate 128 can be epoxy glass fiber plate (FR-4), BT substrate, other plastics or metal support plate.
In the ensuing processing step, can be simultaneously in support plate 128, form two groups of similar structures respectively on relative first support plate surface 130 and the second support plate surface 132, production capacity is doubled.Be that example explains only below with the board structure that is formed on the first support plate surface 130.
Then, in step S104, shown in Fig. 3 B, metal profile 118 is pasted film 136 via first be located on the first support plate surface 130 of support plate 128.Wherein, first material of pasting film 136 for example is dry film photoresistance (dry film photoresist).
The material of above-mentioned metal profile 118 for example is copper (Cu).For example, metal profile 118 can be Copper Foil (copper foil), copper sheet (copper sheet) or copper coin (copper plate).
Then, in step S106, shown in Fig. 3 C, use electroplating technology and form etch barrier 116 on metal profile 118.Wherein, the material of etch barrier 116 for example is nickel (Ni) or any selective etch metal (selectively etchable metal) layer.When metal profile 118 and etch barrier 116 were in etching environment simultaneously, etching solution is etching selectivity etch metal layers and can etching metal supporting bracket 118 optionally, shown in subsequent step S122.
Then, in step S108, shown in Fig. 3 D, form and cover pattern 146 on the part of etch barrier 116.The pattern 146 that covers herein for example is to use lithography process (photolithography) by dry film photoresistance or photoresist layer to be formed.
Before above-mentioned lithography process, can be coated with (apply) photoresist on etch barrier 116, after toasting this photoresist then and forming photoresist layer, again this photoresist layer is carried out lithography process and cover pattern 146 with formation.
Then, in step S110, shown in Fig. 3 E, use electroplating technology and form patterned line layer 112 on another part of etch barrier 116.
Owing to be subjected to covering stopping of pattern 146, patterned line layer 112 is formed on the part that crested pattern 146 does not cover in the etch barrier 116.Say the distribution of patterned line layer 112 and the distribution complementation of covering pattern 146 further.
Then, after step S110, remove and cover pattern 146.
Then, in step S112, shown in Fig. 3 F, form first dielectric protection layer 114 on first 122 of patterned line layer 112.First dielectric protection layer 114 also has several first perforates 126, and those first contacts 178 are exposed in those first perforates 126 accordingly.
In the process that forms first dielectric protection layer 114; can be coated with a protective layer material (not illustrating) earlier on first 122 of patterned line layer 112; and then use this protective layer material of lithography process patterning to form first perforate 126, form first dielectric protection layer 114 shown in Fig. 3 F by this.Protective layer material herein for example is a dielectric material.
Then, in step S114, shown in Fig. 3 G, paste second and paste film 152 on first dielectric protection layer 114.
Then; in step S116; shown in Fig. 3 H, be inverted (invert) metal profile 118, first and paste film 136, patterned line layer 112, etch barrier 116, first dielectric protection layer 114 and second and paste film 152, and make second to paste film 152 and stick on the first support plate surface 130.
Then, in the step S118 of Fig. 2 B, shown in Fig. 3 I, divest first and paste film 136, remove on metal profile 118 to paste film 136, to expose metal profile 118 with first.
Then, in step S120, shown in Fig. 3 J, a part of using etching technique selective removal metal profile 118 is to form metal supporting layer 164.Metal supporting layer 164 centers on those second contacts 182 and exposes the part 166 of etch barrier 116.
In the process of etching metal supporting bracket 118, etch barrier 116 can be protected the patterned line layer 112 of its below.
Then, in step S122, shown in Fig. 3 K, use etching technique and remove this part 166 (this part 166 is illustrated in Fig. 3 J) that is exposed to metal supporting layer 164 in the etch barrier 116, to form metal shielding layer 172.Metal shielding layer 172 exposes those second contacts 182 of these part 166 coverings of etched barrier layer 116.
Then, in step S124, shown in Fig. 3 L, form second dielectric protection layer 120 on second 124 of patterned line layer 112 and cover metal supporting layer 164.Second dielectric protection layer 120 has several second perforates 176, and those second contacts 182 are exposed in those second perforates 176 accordingly.
The technology that forms second dielectric protection layer 120 can no longer repeat to give unnecessary details at this similar in appearance to the technology that forms first dielectric protection layer 114.
Then, in step S126, shown in Fig. 3 M, form second surface processing layer 110 on second contact 182.
The material profit of second surface processing layer 110 in this way in nickel, palladium (Pa) and the gold (Au) at least one, but its application examples in this way electroplating technology form; Perhaps, in another enforcement aspect, second surface processing layer 110 also can be the organizational security layer (Organic Solderability Preservative, OSP).
Then, in step S128, shown in Fig. 3 N, separate support plate 128 and second and paste film 152, make second to paste film 152 and expose out.
The mode of above-mentioned separation for example is to divest mode.Say further, paste on the film 152 because metal supporting layer 164, patterned line layer 112, metal shielding layer 172, first dielectric protection layer 114 and second dielectric protection layer 120 closely link together and closely stick in second.So, after film 152 and support plate 128 are pasted in separation second, the still complete reservation of above-mentioned close-connected structure.
Then, in step S130, shown in Fig. 3 O, paste film 152 with second and on first dielectric protection layer 114, remove to divest mode, to expose first perforate 126.
Then, in step S132, the first surface processing layer 104 of formation shown in Figure 1A is on first contact 178 (first contact 178 is illustrated in Fig. 3 O).The material of first surface processing layer 104 and generation type no longer repeat to give unnecessary details at this similar in appearance to second surface processing layer 110 herein.So far, form two groups of similar board structures.
Then, please be simultaneously with reference to Fig. 4, it illustrates the top view of the board structure that past direction V1 watches among Fig. 3 O.Can be along cutting path P cutting aforesaid substrate structure, to form several substrates 102 shown in Figure 1A.For not making diagram too complicated, Fig. 4 only shows the metal supporting layer 164 and second perforate 176.
Because cutting path P by metal supporting layer 164, makes the side 194 of the metal supporting layer 164 after the cutting become the side, edge of substrate 102.That is, metal supporting layer 164 is positioned at the peripheral position of substrate 102 haply, can significantly strengthen the overall construction intensity of substrate 102.
In addition; in aspect an enforcement; after cutting step or before, can form several second soldered balls 106 shown in Figure 1A accordingly in those second perforates 176 of second dielectric protection layer 120, so that second soldered ball 106 is electrically connected at patterned line layer 112.
In addition, in another enforcement aspect, after cutting step or before, can provide the semiconductor subassembly 108 shown in Figure 1A.Those first soldered balls 192 of semiconductor subassembly 108 dock with those first perforates 126 of substrate 102 (first perforate 126 is illustrated in Figure 1A), so that first soldered ball 192 is electrically connected at patterned line layer 112.By this, the semiconductor subassembly 108 and second soldered ball 106 can see through patterned line layer 112 electric connections.
In addition, when first surface processing layer 104 and second surface processing layer 110 when the organizational security layer is arranged, after reflow (reflow) technology that forms soldered ball, first surface processing layer 104 and 110 evaporations of second surface processing layer disappear.That is to say, when first surface processing layer 104 and second surface processing layer 110 when the organizational security layer is arranged, do not have the existence of first surface processing layer 104 and second surface processing layer 110 at the semiconductor package part 100 of Figure 1A.
The disclosed substrate of the above embodiment of the present invention and use its semiconductor package part and its manufacture method, substrate provides electrical contact through relative two surfaces in its patterned line layer, because the thinner thickness of patterned line layer can have the volume and the thickness that dwindle substrate for a short time.In addition, the metal supporting layer of substrate is positioned at the marginal portion of substrate, and it can be formed by metal sheet, can strengthen the structural strength of substrate.
In sum, though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (11)
1. substrate comprises:
One patterned line layer has relative one first and one second, and this first mask has several first contacts, and this second mask has several second contacts;
One first dielectric protection layer is formed at this first and goes up and expose those first contacts;
One second dielectric protection layer is formed at this second and goes up and expose those second contacts;
One metal supporting layer is embedded in this second dielectric protection layer, in order to strengthen the structural strength of this substrate; And
One metal shielding layer is located between this metal supporting layer and this patterned line layer.
2. substrate as claimed in claim 1, wherein this metal supporting layer is in fact around those second contacts.
3. substrate as claimed in claim 1, wherein this second dielectric protection layer more covers this metal supporting layer.
4. substrate as claimed in claim 1, wherein the material nickel of this metal shielding layer.
5. substrate as claimed in claim 1, wherein the material copper of this metal supporting layer and this patterned line layer.
6. substrate as claimed in claim 1 more comprises:
One first surface processing layer is formed on those first contacts; And
One second surface processing layer is formed on those second contacts.
7. semiconductor package part comprises:
One substrate comprises:
One patterned line layer has relative one first and one second, and this first mask has several first contacts, and this second mask has several second contacts;
One first dielectric protection layer is formed at this first and goes up and expose those first contacts;
One metal shielding layer is formed at this second;
One metal supporting layer is formed at this metal shielding layer, in order to strengthen the structural strength of this substrate; And
One second dielectric protection layer is formed at this second and expose those second contacts;
Several soldered balls are electrically connected at those second contacts; And
The semiconductor assembly is electrically connected at those first contacts.
8. the manufacture method of a substrate comprises:
One support plate is provided, and this support plate has one first support plate surface;
Form a board structure in this first support plate surface, may further comprise the steps:
One metal profile is pasted film in being arranged on this support plate via one first;
Form an etch barrier on this metal profile;
Form one and cover pattern on this etch barrier;
Forming a patterned line layer is not covered on the part of pattern covers by this in this etch barrier, wherein this patterned line layer has relative one first and one second, this of this patterned line layer first mask has this second mask of several first contacts and this patterned line layer that several second contacts are arranged, and second of this of this patterned line layer is towards this etch barrier;
Remove this and cover pattern;
Form one first dielectric protection layer this first in this patterned line layer, this first dielectric protection layer is also exposed those first contacts;
Paste one second and paste film on this first dielectric protection layer;
Be inverted this metal profile, this first is pasted film, this patterned line layer, this etch barrier, this first dielectric protection layer and this second and pastes film, and makes this second paste film and stick on this support plate;
Remove this and first paste film;
A part that removes this metal profile is to form a metal supporting layer, and this metal supporting layer is exposed the part of this etch barrier;
This part that removes this etch barrier is to form a metal shielding layer; And
Form one second dielectric protection layer in this second, this second dielectric protection layer is also exposed those second contacts;
Separate this support plate and this second and paste film; And
Remove on this first dielectric protection layer this and second paste film.
9. manufacture method as claimed in claim 8, wherein this support plate has more second a support plate surface surperficial relative with this first support plate, and this manufacture method more comprises:
Form another board structure in this second support plate surface.
10. manufacture method as claimed in claim 8, wherein in this step of this part that removes this metal profile, this metal supporting layer is in fact around those second contacts.
11. manufacture method as claimed in claim 8, wherein in forming this second dielectric protection layer in this this step of second, this second dielectric protection layer more covers this metal supporting layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101775358A CN101819951B (en) | 2010-05-07 | 2010-05-07 | Base plate, semiconductor packaging piece applying same and manufacture method of base plate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101775358A CN101819951B (en) | 2010-05-07 | 2010-05-07 | Base plate, semiconductor packaging piece applying same and manufacture method of base plate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101819951A true CN101819951A (en) | 2010-09-01 |
| CN101819951B CN101819951B (en) | 2012-01-25 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010101775358A Active CN101819951B (en) | 2010-05-07 | 2010-05-07 | Base plate, semiconductor packaging piece applying same and manufacture method of base plate |
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| CN (1) | CN101819951B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101982876A (en) * | 2010-09-07 | 2011-03-02 | 日月光半导体制造股份有限公司 | Semiconductor packaging part and manufacturing method thereof |
| CN103915356A (en) * | 2014-04-08 | 2014-07-09 | 安捷利（番禺）电子实业有限公司 | Chip packaging method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1213754A2 (en) * | 1994-03-18 | 2002-06-12 | Hitachi Chemical Co., Ltd. | Fabrication process of semiconductor package and semiconductor package |
| US7396703B1 (en) * | 2003-11-20 | 2008-07-08 | Bridge Semiconductor Corporation | Method of making a semiconductor chip assembly with a bumped terminal and a filler |
| CN101504937A (en) * | 2005-10-18 | 2009-08-12 | 恩益禧电子股份有限公司 | Method of manufacturing semiconductor device |
-
2010
- 2010-05-07 CN CN2010101775358A patent/CN101819951B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1213754A2 (en) * | 1994-03-18 | 2002-06-12 | Hitachi Chemical Co., Ltd. | Fabrication process of semiconductor package and semiconductor package |
| US7396703B1 (en) * | 2003-11-20 | 2008-07-08 | Bridge Semiconductor Corporation | Method of making a semiconductor chip assembly with a bumped terminal and a filler |
| CN101504937A (en) * | 2005-10-18 | 2009-08-12 | 恩益禧电子股份有限公司 | Method of manufacturing semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101982876A (en) * | 2010-09-07 | 2011-03-02 | 日月光半导体制造股份有限公司 | Semiconductor packaging part and manufacturing method thereof |
| CN101982876B (en) * | 2010-09-07 | 2013-03-06 | 日月光半导体制造股份有限公司 | Semiconductor packaging part and manufacturing method thereof |
| CN103915356A (en) * | 2014-04-08 | 2014-07-09 | 安捷利（番禺）电子实业有限公司 | Chip packaging method |
| CN103915356B (en) * | 2014-04-08 | 2016-07-20 | 安捷利（番禺）电子实业有限公司 | A kind of method for packing of chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101819951B (en) | 2012-01-25 |
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