CN101964210B - Voltage bootstrap circuit and method for decoding low-voltage low-power consumption electrically erasable programmable read-only memory (EEPROM) row - Google Patents
Voltage bootstrap circuit and method for decoding low-voltage low-power consumption electrically erasable programmable read-only memory (EEPROM) row Download PDFInfo
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- CN101964210B CN101964210B CN200910057631.6A CN200910057631A CN101964210B CN 101964210 B CN101964210 B CN 101964210B CN 200910057631 A CN200910057631 A CN 200910057631A CN 101964210 B CN101964210 B CN 101964210B
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Abstract
The invention discloses a voltage bootstrap circuit for decoding a low-voltage low-power consumption electrically erasable programmable read-only memory (EEPROM) row. The voltage bootstrap circuit comprises a medium-voltage eigen N tube M0, a high-voltage eigen N tube M1 and a medium-voltage N tube M2, wherein in the medium-voltage eigen N tube M0, a source electrode is connected with a low voltage power supply, a grid is connected with control signals CVG of the voltage of grid (VG) of the high-voltage eigen N tube M1, a drain electrode is connected with the grid of the high-voltage eigen N tube M1, and the medium-voltage eigen N tube M0 is used for isolating or transmitting low voltage drain drain (VDD); in the high-voltage eigen N tube M1, a drain electrode is connected with inner row decoding signals, a grid is connected with the drain electrode of the medium-voltage eigen N tube M0, a source electrode is connected with word line (WL) signals of the EEPROM, and the high-voltage eigen N tube M1 is used for transmitting and isolating high voltages; and the medium-voltage N tube M2 is connected with the control signals of the VG of the high-voltage eigen N tube M1 and is used for controlling the VG of the high-voltage eigen N tube M1. The voltage bootstrap circuit meets the requirements on reading speed in the design of the low-voltage low-power consumption EEPROM, does not need to switch medium voltages and high voltages, and has a simple circuit and low power consumption.
Description
Technical field
The present invention relates to a kind of decoding circuit for storer and method, be specifically related to a kind of row decoding circuit for storer and method.
Background technology
At present, in low pressure EEPROM design, in order to improve reading speed, need the voltage raised in wordline when reading data, this voltage realizes usually through charge pump, this adds increased power consumption during reading; In addition, then needing the voltage in wordline to be raised to tens volts when carrying out wiping or write data, being referred to as high pressure.In order to realize the switching of the medium and high pressure under different operating in wordline, just needing the commutation circuit by complexity, this adds increased chip area, affect production cost.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of voltage for the capable decoding of low-voltage and low-power dissipation EEPROM bootstrapping (boost) circuit, and can not need the switching of medium and high pressure, circuit realiration is simple, low in energy consumption.
For solving above technical matters, the invention provides a kind of voltage raise circuit for the capable decoding of low-voltage and low-power dissipation EEPROM, comprise: middle pressure intrinsic N pipe M0, its source electrode is connected with low-tension supply, grid is connected with the control signal CVG of the grid voltage VG of high voltage intrinsic N pipe M1, drain electrode is connected with the grid of high voltage intrinsic N pipe M1, for isolation or transmission low-tension supply voltage VDD; High voltage intrinsic N pipe M1, its drain electrode is connected with internal rows decoded signal, and grid is connected with the drain electrode of middle pressure intrinsic N pipe M0, and source electrode is connected with EEPROM word-line signal WL, for transmission and isolated high-voltage; Middle pressure N pipe M2, is connected with the control signal of the grid voltage VG of high voltage intrinsic N pipe M1, for controlling the grid voltage VG of high voltage intrinsic N pipe M1.
Beneficial effect of the present invention is: adopt transistor gate drain capacitance as voltage bootstrap capacitor, and controlled voltage raise circuit by simple logic.Utilize the requirement to reading speed in voltage raise circuit solution low-voltage and low-power dissipation EEPROM design, and do not need the switching of medium and high pressure, circuit is simple, low in energy consumption.
Present invention also offers the using method of the aforesaid voltage raise circuit for the capable decoding of low-voltage and low-power dissipation EEPROM:
When EEPROM reads, require that the wordline chosen is low-tension supply voltage VDD, the wordline do not chosen is zero level.Now, the control signal CVG of the grid voltage VG of high voltage intrinsic N pipe M1 is high level, then the control signal XG of the grid voltage VG of high voltage intrinsic N pipe M1 is no-voltage; If row decode signal XIN is high level, then the anti-RWINB of row decode signal is no-voltage, internal rows decoded signal RWIN is high level, now voltage bootstrap effect works, the grid voltage VG of high voltage intrinsic N pipe M1 pipe is raised to a current potential higher than low-tension supply voltage VDD, and internal rows decoded signal RWIN level is transferred to word-line signal WL through high voltage intrinsic N pipe M1 without loss; If row decode signal XIN is zero level, then the anti-RWINB of row decode signal is high level, internal rows decoded signal RWIN is zero level, now voltage bootstrap effect is inoperative, the grid voltage VG of high voltage intrinsic N pipe M1 pipe is the current potential lower than low-tension supply voltage VDD, but the zero level of internal rows decoded signal RWIN still can pass on word-line signal WL.
When EEPROM programmes, the wordline chosen is high-voltage power voltage VPP level, and the wordline do not chosen is zero level, now, the control signal CVG of VG is high level before high-voltage power voltage VPP starts generation, and starting to produce rear at high-voltage power voltage VPP is zero level; If row decode signal XIN is high level, then the anti-RWINB of row decode signal is zero level, and internal rows decoded signal RWIN is high level; Now before high-voltage power voltage VPP starts generation, the control signal CVG of VG is high level, middle pressure intrinsic N pipe M0 conducting, and the control signal XG of VG is zero level, VG is boosted, the level of internal rows decoded signal RWIN is transferred to word-line signal WL through high voltage intrinsic N pipe M1, and it is high level, and word-line signal WL is pulled to high-voltage power voltage VPP gradually.If row decode signal XIN is zero level, then the anti-RWINB of row decode signal is high level, internal rows decoded signal RWIN is zero level, the control signal XG of VG is zero level, now before high-voltage power voltage VPP starts generation, the control signal CVG of VG is high level, middle pressure intrinsic N pipe M0 conducting, the grid voltage VG of high voltage intrinsic N pipe M1 pipe is boosted, the level of internal rows decoded signal RWIN is transferred to word-line signal WL through high voltage intrinsic N pipe M1, it is zero level, middle pressure intrinsic N pipe M0 turns off, the grid voltage VG of high voltage intrinsic N pipe M1 pipe is floating, word-line signal WL is still zero level.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
Fig. 1 is embodiment of the present invention circuit diagram.
Description of reference numerals in figure:
I1 and I2: low pressure phase inverter;
I3: two input low pressure rejection gates;
M0: middle pressure intrinsic N manages;
M1: high voltage intrinsic N manages;
M2: middle pressure N pipe;
M3 and M5: high pressure P pipe;
M4: high pressure N manages;
XIN: row decode signal;
RWINB: row decode signal anti-;
RWIN: internal rows decoded signal;
WL: word-line signal;
The grid voltage of VG: high voltage intrinsic N pipe M1 pipe;
The control signal of CVG and XG:VG;
LV:Low Voltage low pressure;
Press in MV:Middle Voltage;
HV:High Voltage high pressure;
VDD:Low Voltage Power low-tension supply voltage;
VPP:High Voltage Power high-voltage power voltage.
Embodiment
As shown in Figure 1, one row decoding voltage raise circuit of the present invention, comprises logic control circuit+middle pressure intrinsic N-type transistor+high voltage intrinsic N-type transistor structure.Voltage bootstrapping control circuit is used for the action of control voltage boostrap circuit under different working modes (reading, programming, standby).The decoded signal of row is used as the control signal of voltage bootstrapping.The gate leakage capacitance of high voltage intrinsic N-type transistor is used as the electric capacity of voltage bootstrapping.Middle pressure intrinsic N-type transistor, in order to insulating power supply voltage, ensures the effect of boosting.
As shown in Figure 1, the voltage raise circuit for the capable decoding of low-voltage and low-power dissipation EEPROM described in the present embodiment, comprise: middle pressure intrinsic N pipe M0, its source electrode is connected with low-tension supply, grid is connected with the control signal CVG of the grid voltage VG of high voltage intrinsic N pipe M1, drain electrode is connected with the grid of high voltage intrinsic N pipe M1, for isolation or transmission low-tension supply voltage VDD; High voltage intrinsic N pipe M1, its drain electrode is connected with internal rows decoded signal, and grid is connected with the drain electrode of middle pressure intrinsic N pipe M0, and source electrode is connected with EEPROM word-line signal WL, for transmission and isolated high-voltage; Middle pressure N pipe M2, is connected with the control signal of the grid voltage VG of high voltage intrinsic N pipe M1, for controlling the grid voltage VG of high voltage intrinsic N pipe M1.
Circuit working principle is as follows:
Suppose low-tension supply VDD=1.8V; High-voltage power supply VPP=15V; Threshold voltage=the 0.1V of middle pressure intrinsic N pipe M0, the threshold voltage=0.2V of high voltage intrinsic N pipe M1.
When EEPROM reads, require that the wordline chosen is low-tension supply voltage VDD level (row decode signal XIN is high level), the wordline do not chosen is zero level (row decode signal XIN is zero level).Now, the control signal CVG=1.8V of VG, then the control signal XG=0V of VG.
If row decode signal XIN is high level ' H ', the then anti-RWINB=0V of row decode signal, internal rows decoded signal RWIN=1.8V, now voltage bootstrap effect works, the grid voltage VG of high voltage intrinsic N pipe M1 pipe is raised to a current potential higher than low-tension supply voltage VDD, general at more than 2V, so internal rows decoded signal RWIN level is transferred to word-line signal WL through high voltage intrinsic N pipe M1 without loss, be 1.8V.
If row decode signal XIN is zero level ' L ', the then anti-RWINB=1.8V of row decode signal, internal rows decoded signal RWIN=0V, now voltage bootstrap effect is inoperative, the grid voltage VG=1.7V of high voltage intrinsic N pipe M1 pipe, but the zero level of internal rows decoded signal RWIN still can pass on word-line signal WL easily.
When EEPROM programmes, the wordline chosen is high-voltage power voltage VPP level (row decode signal XIN is high level), and the wordline do not chosen is zero level (row decode signal XIN is zero level).Now, the control signal CVG of VG is high level before high-voltage power voltage VPP starts generation, and starting to produce rear at high-voltage power voltage VPP is zero level.
If row decode signal XIN is high level ' H ', then the anti-RWINB=0V of row decode signal, internal rows decoded signal RWIN=1.8V.Now before high-voltage power voltage VPP starts generation, the control signal CVG of VG is high level ' H ', middle pressure intrinsic N pipe M0 conducting, and the control signal XG=0V of VG, VG is boosted, and the level of internal rows decoded signal RWIN is transferred to word-line signal WL through high voltage intrinsic N pipe M1, its level is 1.8V, then high pressure N pipe M4 conducting, moves high pressure P pipe M5 grid level to zero, high pressure P pipe M5 conducting; Then after high-voltage power voltage VPP starts generation, the control signal CVG of VG is zero level ' L ', the then control signal XG=1.8V of VG, the grid voltage VG=0V of high voltage intrinsic N pipe M1 pipe, high voltage intrinsic N pipe M1 is turned off, high-voltage power voltage VPP starts to produce, and word-line signal WL is pulled to 15V gradually.
If row decode signal XIN is zero level ' L ', then the anti-RWINB=1.8V of row decode signal, internal rows decoded signal RWIN=0V, the control signal XG=0V of VG.Now before high-voltage power voltage VPP starts generation, the control signal CVG of VG is high level ' H ', middle pressure intrinsic N pipe M0 conducting, the grid voltage VG of high voltage intrinsic N pipe M1 pipe is boosted, the level of internal rows decoded signal RWIN is transferred to word-line signal WL through high voltage intrinsic N pipe M1, and its level is 0V, then high pressure P pipe M3 conducting, by equal with source level for high pressure P pipe M5 grid level, high pressure P pipe M5 turns off; Then after high-voltage power voltage VPP starts generation, the control signal CVG of VG is zero level ' L ', and middle pressure intrinsic N pipe M0 turns off, and the grid voltage VG of high voltage intrinsic N pipe M1 pipe is floating, but because do not have leak channel, word-line signal WL is still zero level.
Claims (3)
1. the voltage raise circuit for the capable decoding of low-voltage and low-power dissipation EEPROM; It is characterized in that, comprising:
Middle pressure intrinsic N manages (M0), its source electrode is connected with low-tension supply, grid manages the grid voltage (VG) of (M1) control signal (CVG) with high voltage intrinsic N is connected, (M1) is managed in drain electrode grid with high voltage intrinsic N is connected, for isolation or transmission low-tension supply voltage (VDD);
High voltage intrinsic N manages (M1), and its source electrode is connected with internal rows decoded signal, and the drain electrode that grid manages (M0) with middle pressure intrinsic N is connected, and drain electrode is connected with EEPROM word-line signal (WL), for transmission and isolated high-voltage;
Low pressure rejection gate (I0) and middle pressure N manage (M2), the first input end of low pressure rejection gate manages the grid voltage (VG) of (M1) control signal (CVG) with high voltage intrinsic N is connected, second input end is connected with the designature of internal rows decoded signal, the grid (XG) that output and the middle N of pressure of low pressure rejection gate manage (M2) is connected, (M1) is managed in the drain electrode that middle pressure N manages (M2) grid voltage (VG) with high voltage intrinsic N is connected, the source ground of middle pressure N pipe (M2), the grid voltage (VG) of (M1) is managed for controlling high voltage intrinsic N.
2. the using method for the voltage raise circuit of the capable decoding of low-voltage and low-power dissipation EEPROM as claimed in claim 1; It is characterized in that,
When EEPROM reads, require that the row decode signal (XIN) chosen is low-tension supply voltage (VDD), the row decode signal (XIN) do not chosen is zero level, now, the control signal (CVG) that high voltage intrinsic N manages the grid voltage (VG) of (M1) is high level, then in, the grid (XG) of pressure N pipe (M2) is no-voltage;
If row decode signal (XIN) is high level, then anti-(RWINB) of row decode signal is no-voltage, internal rows decoded signal (RWIN) is high level, now voltage bootstrap effect works, the grid voltage (VG) that high voltage intrinsic N manages (M1) is raised to a current potential higher than low-tension supply voltage (VDD), and internal rows decoded signal (RWIN) level is managed (M1) through high voltage intrinsic N without loss and is transferred to word-line signal (WL);
If row decode signal (XIN) is zero level, then anti-(RWINB) of row decode signal is high level, internal rows decoded signal (RWIN) is zero level, now voltage bootstrap effect is inoperative, the grid voltage (VG) of high voltage intrinsic N pipe (M1) is the current potential lower than low-tension supply voltage (VDD), but the zero level of internal rows decoded signal (RWIN) still can pass on word-line signal (WL).
3. the using method for the voltage raise circuit of the capable decoding of low-voltage and low-power dissipation EEPROM as claimed in claim 1; It is characterized in that,
When EEPROM programmes, the wordline chosen is high-voltage power voltage (VPP) level, the wordline do not chosen is zero level, now, the control signal (CVG) that high voltage intrinsic N manages the grid voltage (VG) of (M1) is high level before high-voltage power voltage (VPP) starts generation, and starting to produce rear at high-voltage power voltage (VPP) is zero level;
If row decode signal (XIN) is high level, then anti-(RWINB) of row decode signal is zero level, and internal rows decoded signal (RWIN) is high level, now before high-voltage power voltage (VPP) starts generation, the control signal (CVG) that high voltage intrinsic N manages the grid voltage (VG) of (M1) is high level, middle pressure intrinsic N manages (M0) conducting, and the grid (XG) of middle pressure N pipe (M2) is zero level, the grid voltage (VG) that high voltage intrinsic N manages (M1) is boosted, the level of internal rows decoded signal (RWIN) is managed (M1) through high voltage intrinsic N and is transferred to word-line signal (WL), word-line signal (WL) is high level, word-line signal (WL) is pulled to high-voltage power voltage (VPP) gradually,
If row decode signal (XIN) is zero level, then anti-(RWINB) of row decode signal is high level, internal rows decoded signal (RWIN) is zero level, the grid (XG) of middle pressure N pipe (M2) is zero level, now before high-voltage power voltage (VPP) starts generation, the control signal (CVG) that high voltage intrinsic N manages the grid voltage (VG) of (M1) is high level, middle pressure intrinsic N manages (M0) conducting, the grid voltage (VG) that high voltage intrinsic N manages (M1) is boosted, the level of internal rows decoded signal (RWIN) is managed (M1) through high voltage intrinsic N and is transferred to word-line signal (WL), word-line signal (WL) is zero level, middle pressure intrinsic N manages (M0) and turns off, the grid voltage (VG) that high voltage intrinsic N manages (M1) pipe is floating, word-line signal (WL) is still zero level.
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| CN200910057631.6A CN101964210B (en) | 2009-07-23 | 2009-07-23 | Voltage bootstrap circuit and method for decoding low-voltage low-power consumption electrically erasable programmable read-only memory (EEPROM) row |
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| CN200910057631.6A CN101964210B (en) | 2009-07-23 | 2009-07-23 | Voltage bootstrap circuit and method for decoding low-voltage low-power consumption electrically erasable programmable read-only memory (EEPROM) row |
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| CN111968692B (en) * | 2020-10-22 | 2021-04-16 | 深圳市芯天下技术有限公司 | Circuit and chip for reducing area of column redundancy replacement circuit |
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| US7924633B2 (en) * | 2009-02-20 | 2011-04-12 | International Business Machines Corporation | Implementing boosted wordline voltage in memories |
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