CN203376978U - Bit line negative voltage circuit capable of improving SRAM writing capacity - Google Patents
Bit line negative voltage circuit capable of improving SRAM writing capacity Download PDFInfo
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- CN203376978U CN203376978U CN201320502113.2U CN201320502113U CN203376978U CN 203376978 U CN203376978 U CN 203376978U CN 201320502113 U CN201320502113 U CN 201320502113U CN 203376978 U CN203376978 U CN 203376978U
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Abstract
The utility model discloses a novel circuit capable of improving SRAM writing capacity. The circuit comprises a bit line voltage tracking circuit, a capacitor charging circuit, a capacitor discharging circuit, a pre-discharging circuit, a pre-discharging control circuit and a coupling capacitor. Bias voltage generated by the pre-discharging control circuit is used for controlling the discharging capacity of the pre-discharging circuit and reducing voltage of a capacitor pushing end coupled with the coupling capacitor in advance, so that the potential of the capacitor pushing end under a high-power-voltage condition is lower than the potential of the capacitor pushing end under a low-power-voltage condition. Therefore, the absolute value of negative voltage generated under the high-power-voltage condition is lower than that of negative voltage generated under the low-power-voltage condition. Under the condition that the writing capacity of an SRAM under the low-power-voltage condition is ensured, the problem of the excessively-high absolute value of the negative voltage generated under the high-power-voltage condition is solved.
Description
Technical field
The utility model relates to a kind of circuit of auxiliary SRAM write operation, particularly relates to a kind of circuit of controlling the negative voltage size produced on bit line.
Background technology
Static RAM (Static Random Access Memory, SRAM) due to its high speed, high integration, low-power consumption and with the favorable compatibility characteristics of technique, become the important ingredient of SOC (system on a chip) (SOC).Therefore area, power consumption, performance and the electric leakage of SRAM become the key factor that affects SOC.Along with the progress of technique, the supply voltage of SRAM is more and more lower, and this demand to more and more faster access speed is a challenge.Therefore read-write auxiliary circuit miscellaneous is suggested, in writing auxiliary circuit, improve the gate source voltage Vgs of transfer tube, it is the voltage difference between word line (word line) and bit line (bit line), particularly bit-line voltage is reduced to the method for negative potential from 0v, because it affects little characteristics to read operation and static noise margin (SNM), becomes the important supplementary means of writing.
The problem that known bit line negative voltage circuit exists is: along with the rising of voltage, the absolute value of the negative voltage of generation is larger, at first, when word line voltage is high level, the gate source voltage Vgs of transfer tube is excessive, affects the serviceable life of transfer tube, also can cause SRAM the reliability variation; Secondly, at word line voltage, when being low level, transfer tube should be in closed condition, but because the absolute value of the negative voltage produced on bit line is excessive, transfer tube may be opened, and even mistake is write to the data in storage unit; Again, the absolute value of the negative voltage of generation is higher, in the process of pairs of bit line precharge, can produce larger power consumption; Finally, may cause PN joint in transistor that forward bias occurs.
The utility model content
Too high for the absolute value that overcomes the negative voltage that existing bit line negative voltage circuit under high pressure produces, the utility model provides a kind of novel negative voltage control circuit, can realize providing stable negative voltage under the condition of different electrical power voltage.
The utility model solves the technical scheme that its technical matters adopts: this control circuit is except comprising coupling capacitance, the capacitor charging circuit in the conventional bit line negative voltage generator, and capacitor discharging circuit has also increased pre-arcing circuit, pre-arcing control circuit, bit line potential tracking method circuit.The pre-arcing circuit is connected on the electric capacity promote-side, according to different supply voltages, the current potential of electric capacity promote-side is bled off, its discharge capability is controlled by the pre-arcing control circuit, realizes that discharge circuit discharge capability under high power supply voltage is strong, the effect under low supply voltage a little less than discharge capability.Bit-line voltage is followed the trail of circuit and can be realized discharging into low level the time and producing negative voltage at bit-line voltage, the absolute value that so both can guarantee the negative voltage that produces when low supply voltage is enough large, write operation is played to booster action, can avoid again for etc. negative voltage to be generated affect the speed of SRAM.
(1) the utility model provides a kind of bit line negative voltage circuit of the SRAM of raising write capability, comprise a coupling capacitance, a capacitor charging circuit, a capacitor discharging circuit, it is characterized in that: also comprise a pre-arcing circuit and a pre-arcing control circuit, wherein coupling capacitance is coupled in the electric capacity promote-side and electric capacity is pushed between end, and electric capacity is pushed end and is connected with bit line; Whether capacitor charging circuit is coupled between supply voltage and electric capacity promote-side, rely on capacitor charge and discharge control end and capacitor charging Enable Pin to control to capacitor charging; Whether capacitor discharging circuit is coupled between electric capacity promote-side and reference voltage, rely on the capacitor charge and discharge control end to control to capacitor discharge; The pre-arcing circuit is coupled between electric capacity promote-side and reference voltage, and the offset signal size produced by the pre-arcing control circuit determines the size of discharge capability; The pre-arcing control circuit is coupled between supply voltage and reference voltage, controls enable signal by pre-arcing and produces offset signal.
(2) according to the bit line negative voltage circuit of (1) described raising SRAM write capability, it is characterized in that: the pre-arcing control circuit comprises a current source and a sectional pressure element.
(3) according to (2) the described bit line negative voltage circuit that improves the SRAM write capability, it is characterized in that: this current source is the first transistor, there is control end, first end and the second end, its control end receives pre-arcing and controls enable signal, its first end is connected to supply voltage, and its second end produces offset signal.
(4) according to the bit line negative voltage circuit of (2) described raising SRAM write capability, it is characterized in that: sectional pressure element is a resistance, first end and the second end, and its first end is connected to reference voltage, and its second end produces offset signal.
(5) according to (1) the described bit line negative voltage circuit that improves the SRAM write capability, it is characterized in that: the pre-arcing circuit is transistor seconds, has control end, first end and the second end, and its control end receives offset signal, its first end is connected to reference voltage, and it second is connected to the electric capacity promote-side.
The beneficial effects of the utility model: purpose is under high power supply voltage, and the current potential of electric capacity promote-side is bled off in advance, and the voltage difference at electric capacity two ends reduces like this, and the absolute value of the negative voltage produced by capacitive coupling reduces; And, under low supply voltage, the discharge capability of pre-arcing circuit is poor, even be in off state, very little on the impact of the current potential of electric capacity promote-side like this, the absolute value that can guarantee to produce negative voltage is enough low.The absolute value of having realized like this negative voltage that produces under high power supply voltage is little, and the absolute value of the negative voltage produced under low supply voltage is large, both guaranteed under the low supply voltage the raising of SRAM write capability, can avoid again the too high problems such as reliability of bringing of absolute value of the negative voltage that produces under high power supply voltage.
Be elaborated the utility model below in conjunction with drawings and Examples in order to illustrate better.
The accompanying drawing explanation
Fig. 1 is the bit line negative voltage circuit that the utility model improves the SRAM write capability.
Fig. 2 is the utility model sequential chart under high power supply voltage and low supply voltage respectively.
11. pre-arcing circuit in Fig. 1,12. pre-arcing control circuits, 13. capacitor charging circuits, 14. capacitor discharging circuits, 15. bit line potential tracking method circuit.
Embodiment
Following examples are with reference to Fig. 1～2.
The bit line negative voltage circuit that the utility model improves the SRAM write capability comprises coupling capacitance CC, pre-arcing path 11, pre-arcing control circuit 12, capacitor charging circuit 13, capacitor discharging circuit 14 and bit line potential tracking method circuit 15.Capacitor C C is coupled in electric capacity promote-side Boost and electric capacity is pushed between end Nboost, and electric capacity is pushed end Nboost and is connected with bit line Bl.First electric capacity promote-side Boost is charged and reaches supply voltage Vdd by capacitor charging circuit 13.Pre-arcing circuit 11 is coupled between electric capacity promote-side Boost and reference voltage Vss, and the bias voltage Vbias produced by pre-arcing control circuit 12 controls the discharge capability of pre-arcing circuit.Discharged into reference voltage Vss by 14 couples of electric capacity promote-side Boost of discharge circuit afterwards, by the coupling of capacitor C C, the voltage that electric capacity is pushed on end Nboost descends simultaneously, and produces bit line negative voltage Vnbl.Dummy bitline Dmy_bl in bit line potential tracking method circuit 15 connects and the as many storage unit of bit line BL, 2 bit lines of bit line being followed the trail of in circuit 15 again connect together, the load of dummy bitline Dmy_bl is exactly 2 times of bit line BL like this, therefore, when the current potential of bit line Bl and dummy bitline Dmy_bl descends simultaneously, when bit line Bl drops to reference voltage Vss, dummy bitline Dmy_bl drops to 50%Vss, controlling the generation of bit line negative voltage by dummy bitline Dmy_bl, the absolute value that so both can guarantee the negative voltage that produces is enough large, can avoid again for etc. negative voltage to be generated affect the speed of SRAM.
The sequential control that produces negative voltage is as follows:
(1) rising edge of writing enable signal Wpg triggers charging circuit 13, and to the electric capacity promote-side, Boost is charged.The rising edge of writing enable signal Wpg triggers the rising edge of bit line discharges enable signal Float simultaneously, and the dummy bitline Dmy_bl in bit line Bl and bit line potential tracking method circuit 15 is discharged simultaneously.Because the load on dummy bitline Dmy_bl is 2 times of load on bit line Bl, therefore, when the current potential of bit line Bl drops to reference voltage Vss, dummy bitline Dmy_bl drops to 50%Vss.
(2) negative edge of dummy bitline Dmy_bl triggers the negative edge that enable signal En is controlled in pre-arcing.
(3) negative edge of pre-arcing control enable signal En makes charge/discharge control circuit 12 produce bias voltage Vbias, and Vbias raises along with the rising of supply voltage, and the negative edge that enable signal En is controlled in pre-arcing simultaneously turn-offs capacitor charging circuit.
(4) bias voltage Vbias will control 11 couples of electric capacity promote-side Boost of pre-arcing circuit and be discharged, the current potential of Boost is dragged down, and under high power supply voltage, due to bias voltage, Vbias is high, the discharge capability of pre-arcing circuit 11 is strong, so the current potential of electric capacity promote-side Boost is lower; And, under low supply voltage, because biased electrical is forced down, a little less than the discharge capability of pre-arcing circuit 11, so the current potential of electric capacity promote-side Boost is higher.It should be noted that electric capacity Partner Nboost is connected with reference voltage Vss because now bit line discharges enable signal Float is also in high level state, so the decline of the current potential of electric capacity promote-side Boost can not produce bit line negative voltage Vnbl.
(5) by chain of inverters, dummy bitline Dmy_bl is postponed to obtain Dmy_bl_buf with shaping.
(6) at first, the negative edge of Dmy_bl_buf triggers the negative edge of bit line discharges enable signal Float, and bit line Bl and reference voltage Vss are disconnected; Secondly, the negative edge of Dmy_bl_buf triggers the rising edge that enable signal En is controlled in pre-arcing, and the current potential of bias voltage Vbias is dropped to electronegative potential, turn-offs pre-arcing circuit 11; Finally, the negative edge of Dmy_bl_buf turn-offs charging circuit 13 simultaneously, and open discharge circuit 14, to the electric capacity promote-side, Boost is discharged, the current potential of Boost is dropped to reference voltage Vss, by the coupling of capacitor C C, electric capacity is pushed to end Nboost and moves negative potential to, therefore produce bit line negative voltage Vnbl.Under high power supply voltage, because electric capacity promote-side Boost is lower, the absolute value of the bit line negative voltage Vnbl of generation is low; And, under low supply voltage, because electric capacity promote-side Boost is higher, the absolute value of the bit line negative voltage Vnbl of generation is high.
In sum, the utility model is the current potential discharging in advance to the electric capacity promote-side by pre-arcing circuit and pre-arcing control circuit, under high power supply voltage, discharge many, and electric discharge is few under low supply voltage, thereby the negative voltage on bit line does not significantly change because of the variation of supply voltage.
Claims (5)
1. a bit line negative voltage circuit that improves the SRAM write capability, comprise a coupling capacitance, a capacitor charging circuit, a capacitor discharging circuit, it is characterized in that: also comprise a pre-arcing circuit and a pre-arcing control circuit, wherein coupling capacitance is coupled in the electric capacity promote-side and electric capacity is pushed between end, and electric capacity is pushed end and is connected with bit line; Whether capacitor charging circuit is coupled between supply voltage and electric capacity promote-side, rely on capacitor charge and discharge control end and capacitor charging Enable Pin to control to capacitor charging; Whether capacitor discharging circuit is coupled between electric capacity promote-side and reference voltage, rely on the capacitor charge and discharge control end to control to capacitor discharge; The pre-arcing circuit is coupled between electric capacity promote-side and reference voltage, and the offset signal size produced by the pre-arcing control circuit determines the size of discharge capability; The pre-arcing control circuit is coupled between supply voltage and reference voltage, controls enable signal by pre-arcing and produces offset signal.
2. the bit line negative voltage circuit of raising according to claim 1 SRAM write capability, it is characterized in that: the pre-arcing control circuit comprises a current source and a sectional pressure element.
3. the bit line negative voltage circuit of raising according to claim 2 SRAM write capability, it is characterized in that: this current source is the first transistor, there is control end, first end and the second end, its control end receives pre-arcing and controls enable signal, its first end is connected to supply voltage, and its second end produces offset signal.
4. the bit line negative voltage circuit of raising according to claim 2 SRAM write capability, it is characterized in that: sectional pressure element is a resistance, first end and the second end, its first end is connected to reference voltage, and its second end produces offset signal.
5. the bit line negative voltage circuit of raising according to claim 1 SRAM write capability, it is characterized in that: the pre-arcing circuit is transistor seconds, there is control end, first end and the second end, its control end receives offset signal, its first end is connected to reference voltage, and it second is connected to the electric capacity promote-side.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201320502113.2U CN203376978U (en) | 2013-08-17 | 2013-08-17 | Bit line negative voltage circuit capable of improving SRAM writing capacity |
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| CN201320502113.2U CN203376978U (en) | 2013-08-17 | 2013-08-17 | Bit line negative voltage circuit capable of improving SRAM writing capacity |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106205717A (en) * | 2014-11-28 | 2016-12-07 | 力晶科技股份有限公司 | Internal power source voltage auxiliary circuit, semiconductor storage and semiconductor device |
| CN106409330A (en) * | 2015-07-31 | 2017-02-15 | 展讯通信（上海）有限公司 | Circuit and method for inhibiting negative bit line under high supply voltage |
| CN108665931A (en) * | 2018-05-21 | 2018-10-16 | 上海华力集成电路制造有限公司 | The pre- reducing transformer of bit line |
| CN110033807A (en) * | 2019-03-04 | 2019-07-19 | 上海华力集成电路制造有限公司 | Wordline ladder, which rises device and rises device using the wordline ladder, slows down the method for reading disturbance |
| CN110310690A (en) * | 2015-02-12 | 2019-10-08 | 円星科技股份有限公司 | The write-in control method of SRAM module and SRAM module |
| CN113628648A (en) * | 2020-05-08 | 2021-11-09 | 瑞昱半导体股份有限公司 | Apparatus and method for SRAM write assist |
-
2013
- 2013-08-17 CN CN201320502113.2U patent/CN203376978U/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106205717A (en) * | 2014-11-28 | 2016-12-07 | 力晶科技股份有限公司 | Internal power source voltage auxiliary circuit, semiconductor storage and semiconductor device |
| CN106205717B (en) * | 2014-11-28 | 2019-10-11 | 力晶积成电子制造股份有限公司 | Internal power source voltage auxiliary circuit, semiconductor storage and semiconductor device |
| CN110310690A (en) * | 2015-02-12 | 2019-10-08 | 円星科技股份有限公司 | The write-in control method of SRAM module and SRAM module |
| CN110310690B (en) * | 2015-02-12 | 2022-12-09 | 円星科技股份有限公司 | SRAM module and write control method thereof |
| CN106409330A (en) * | 2015-07-31 | 2017-02-15 | 展讯通信（上海）有限公司 | Circuit and method for inhibiting negative bit line under high supply voltage |
| CN106409330B (en) * | 2015-07-31 | 2019-06-25 | 展讯通信（上海）有限公司 | Inhibit the circuit and method of bit line negative voltage under high power supply voltage |
| CN108665931A (en) * | 2018-05-21 | 2018-10-16 | 上海华力集成电路制造有限公司 | The pre- reducing transformer of bit line |
| CN110033807A (en) * | 2019-03-04 | 2019-07-19 | 上海华力集成电路制造有限公司 | Wordline ladder, which rises device and rises device using the wordline ladder, slows down the method for reading disturbance |
| CN113628648A (en) * | 2020-05-08 | 2021-11-09 | 瑞昱半导体股份有限公司 | Apparatus and method for SRAM write assist |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140101 Termination date: 20140817 |
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| EXPY | Termination of patent right or utility model |