CN101957410A - Personal laboratory system integrating device - Google Patents
Personal laboratory system integrating device Download PDFInfo
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- CN101957410A CN101957410A CN 201010273261 CN201010273261A CN101957410A CN 101957410 A CN101957410 A CN 101957410A CN 201010273261 CN201010273261 CN 201010273261 CN 201010273261 A CN201010273261 A CN 201010273261A CN 101957410 A CN101957410 A CN 101957410A
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Abstract
The invention discloses a personal laboratory system integrating device. The device comprises a power supply (1), a mainboard (2), a drive board (3), a test interface (4) and an operation panel (5), wherein the power supply (1) is used for providing power for a system; the mainboard (2) is used for running an operating system, executing a test program, outputting multipath reference voltage, measuring multipath input voltage and controlling IO (Input/Output) and communication; the drive board (3) is used for realizing the drive of an input and output signal of the mainboard; the test interface (4) is a signal interface for connecting the device with a test object; the operation panel (5) is used for displaying an interactive interface and providing key operation; and a PC (Personal Computer) communication interface (6) is used for providing a data exchange interface of a PC and the device. The device realizes multichannel independent adjustable voltage output, real-time current measurement, multichannel independent adjustable current source, multichannel independent voltage input detection, level adjustable digital IO, PWM (Pulse-Width Modulation) signal generation and I2C and SPI communication protocols under the control of the PC or the panel.
Description
Technical field
The present invention relates to a kind of individual laboratory system integrating device, particularly relate to a kind of hyperchannel independence adjustable voltage output, real-time current measurement, hyperchannel independence adjustable current source, the input of hyperchannel independent voltage detects, level is adjustable Digital I control, produce pwm signal, support I2C, the system integration device of SPI communications protocol.
Background technology
When carrying out the electronic product exploitation, though the developer only wants gordian technique is partly verified and assessed, but tend to do a large amount of repetitions for this reason and seem important work, for example, use communications protocol (I always for system provides multiple voltage, monitors multi-group data, digital level conversion, the external control signal that enables in real time
2C, SPI) driving realize or the like.For realizing that above-mentioned need of work buys multiple instrument and instrument, repeat to draw a design, a large amount of experimental datas of manual measurement devote considerable time, human and material resources and financial resources.
Summary of the invention
The invention provides a kind of device that resource set in the laboratory is become one.The integrated hyperchannel independence adjustable voltage output of this device, real-time current measurements, hyperchannel independence adjustable current source, the input of hyperchannel independent voltage detects, level is adjustable Digital I control, generation pwm signal, support I2C, the SPI communications protocol.Can carry out experiment fast, obtain a large amount of test datas easily, pay close attention to the key point of experiment, reach and economize on resources, simplify experiment or testing procedure, shorten the purpose of experiment or test period.
The present invention solves above-mentioned technical matters by following technical proposals:
A kind of individual laboratory system integrating device, this device can be under the control of PC or guidance panel, realize that the output of hyperchannel independence adjustable voltage, real-time current measurements, hyperchannel independence adjustable current source, the Digital I that the input of hyperchannel independent voltage detects, level is adjustable are controlled, generation pwm signal, I2C, the SPI communications protocol.
Preferably; the output of hyperchannel independence adjustable voltage; this individual's laboratory system integrating device mainboard is provided with CPU and FPGA; wherein CPU receives the instruction of output voltage and converts thereof into steering order; this steering order is passed to FPGA; FPGA produces DAC conversion and control sequential according to this steering order; the output aanalogvoltage; this aanalogvoltage is after voltage, electric current amplify the driver module driving; pass through overcurrent protection and current detection module again, export by the experimental interface voltage output end on the drive plate.
Preferably, real-time hyperchannel current detecting.Current detection module detects the current signal that the voltage output channel flows through in real time, this current detection module comprises sampling resistor and differential amplification module, wherein sampling resistor is obtained current signal, after differential amplification and amplitude conditioning, the A/D converter of sending on the mainboard by analog input channel carries out analog to digital conversion again.Read the ADC transformation result by FPGA, send into CPU, after the CPU compensation is calculated, convert corresponding current value to.
Preferably, multichannel voltage detects.The analog voltage signal of outside input via excess voltage protection after; sending into aanalogvoltage input buffering module again cushions and level conversion; the A/D converter of sending into afterwards on the mainboard carries out analog to digital conversion; read the ADC transformation result by FPGA; send into CPU, after the CPU compensation is calculated, convert the correspondent voltage value to.
Preferably, multiple current source output channel, the instruction of CPU received current source output current calculates the control corresponding amount, and converts thereof into steering order, this steering order is passed to FPGA, FPGA produces the D/A converter control timing according to this steering order, through DAC output analog control voltage value, and the driven with current sources module on this analog voltage input drive plate, this driven with current sources module converts this magnitude of voltage to current source, exports by the current source output interface on the drive plate.
Preferably, this device also comprises input, the digital I/O interface that output level is adjustable, adopt the voltage way of output as described below to export three tunnel Digital I control voltage, it is respectively the digital signal high level voltage, low level voltage and threshold voltage: CPU receives the instruction of output voltage and converts thereof into steering order, this steering order is passed to FPGA, FPGA produces DAC conversion and control sequential according to this steering order, the output aanalogvoltage, this aanalogvoltage is through voltage, after electric current amplifies the driver module driving, pass through overcurrent protection and current detection module again, behind overcurrent protection and current detection module as the reference data of Digital I input and output; Wherein high level voltage, low level voltage switch by the multiway analog switch device, realize the adjusting of Digital I input, output level, and threshold voltage is connected to multiway analog switch and differentiates as Digital I input signal 0 and 1 thresholding.
Preferably, the output of Digital I adopts the high speed analog multichannel switch to be directly connected to high level voltage or low level voltage, the scanning output of utilization Digital I cooperates the current measurement to high level and low level reference data, realizes Digital I is connected the detection of open circuit and short circuit.(Digital I open circuit or short circuit connect detecting)
Preferably, the Digital I of experimental interface, the IO that disposes appointment flexibly by FPGA becomes data, clock line and the control line of I2C, SPI communications protocol, realizes the communication sequential of I2C, SPI under FPGA control, realizes the exchanges data with experimental subjects.
Preferably, it also comprises pwm signal output.CPU receives the instruction of PC or guidance panel, converts corresponding PWM frequency and dutyfactor value to and is sent to FPGA, and FPGA is according to the corresponding pwm signal of controlled quentity controlled variable output of CPU.
Positive progressive effect of the present invention is:
1, realized the output of hyperchannel independence adjustable voltage; and its precision can be controlled in 5 ‰; each passage output voltage is realized independently digital regulated; in output voltage, can measure output current (10uA～1000mA) in real time; and this current information fed back to the user; the user can in time be made a response, also have over-current over-voltage protection in addition, electron device is well protected.
2, realized that hyperchannel independent voltage input detects, can detect the multi-channel analog voltage signal simultaneously, and its precision can be controlled in 5 ‰ precision, and have overvoltage protection.
3, have hyperchannel independence adjustable current source, the maximum current that allows to pass through is 100mA; The multichannel current source can independent regulation.
4, realize that (Digital I of 0V～5V), the output Digital I can be done the test of open circuit, short circuit connection to 40 road level automatic and adjustable.
5, have 2 tunnel PWM passages independently, the output frequency of pwm signal and dutycycle are adjustable separately.
6, support various protocols, as I2C, the SPI agreement.
7. all output voltages, current measurement, Digital I control voltage, input voltage are measured all by demarcating and verification, by being controlled in 5 ‰ behind the software compensation.
Description of drawings
Fig. 1 is the structured flowchart of the present invention individual laboratory system integrating device.
Fig. 2 moves towards synoptic diagram for the signal on the mainboard of embodiments of the invention 1.
Fig. 3 moves towards synoptic diagram for the signal on the drive plate of embodiments of the invention 1.
Fig. 4 is the demarcation and the verification synoptic diagram of embodiments of the invention 1.
Fig. 5 is the breadboard interface structure block diagram of the present invention individual.
Fig. 6 moves towards synoptic diagram for the signal on the mainboard of embodiments of the invention 2.
Fig. 7 moves towards synoptic diagram for the signal on the drive plate of embodiments of the invention 2.
Fig. 8 moves towards synoptic diagram for the signal on the mainboard of embodiments of the invention 3.
Fig. 9 moves towards synoptic diagram for the signal on the drive plate of embodiments of the invention 3.
Figure 10 moves towards synoptic diagram for the signal on the mainboard of embodiments of the invention 4.
Figure 11 moves towards synoptic diagram for the signal on the mainboard of embodiments of the invention 5.
Figure 12 moves towards synoptic diagram for the signal on the drive plate of embodiments of the invention 5.
Figure 12 A is the IO level shifting circuit synoptic diagram of embodiments of the invention 5.
Figure 13 is the short-circuit detecting synoptic diagram of embodiments of the invention 5.
Figure 14 is the detection synoptic diagram that opens circuit of embodiments of the invention 5.
Figure 15 moves towards synoptic diagram for the signal on the mainboard of embodiments of the invention 6.
Figure 16 moves towards synoptic diagram for the signal on the drive plate of embodiments of the invention 6.
Figure 17 is individual laboratory system integrating device application platform synoptic diagram.
Embodiment
Provide preferred embodiment of the present invention below in conjunction with accompanying drawing, clear in order to describe to describe technical scheme of the present invention in detail, the hollow arrow in the accompanying drawing is represented unidirectional connection or the two-way connection between each module, and filled arrows is represented the trend of electric signal.
At first Reference numeral is described.In order to meet those skilled in the art's custom, there is the many places English mark in the accompanying drawing of the present invention, list its Chinese and English term contrast at this:
One of communication interface on the COM RS-232 personal computer is by Electronic Industries Association (Electronic Industries Association, the asynchronous transmission standard interface of EIA) being formulated.Usually RS-232 interface occurs with 9 pins (DB-9) or the kenel of 25 pins (DB-25), has two groups of RS-232 interface on the general personal computer, is called COM1 and COM2.
The RJ-45RJ-45 interface can be used for connecting RJ-45 connector, is applicable to the network that is made up by twisted-pair feeder, and this port is modal, and in general ethernet concentrator all can provide this port.We are usual what mouthful hubs of saying, and what RJ-45 ports what just be meant has.
I
2C I
2C (Inter-Integrated Circuit) bus is a kind of twin wire universal serial bus by the exploitation of PHILIPS company, is used to connect microcontroller and peripherals thereof.
SCL Serial Clock Line serial communication clock line
SDA Serial Data Line serial communication data line
SPI Serial Peripheral Interface Serial Peripheral Interface, SPI is a kind of synchronous serial communication mode that motorola inc releases, and is a kind of four line locking buses.
JTAG JTAG is the writing a Chinese character in simplified form of prefix letter of English " Joint Test Action Group (joint test behavior tissue) ", and this is organized into and stands on 1985, is PCB and the IC testing standard of being initiated formulation by the main electronics manufacturer of several families.JTAG advises being IEEE1149.1-1990 test access port and boundary-scan architecture standard in nineteen ninety by the IEEE approval.This standard code carry out the needed hardware and software of boundary scan.
UART Universal Asynchronous Receiver/Transmitter, universal asynchronous reception/dispensing device, UART are the chips that a parallel input becomes serial output, are integrated on the mainboard usually
256 COLOR LCD, 256 dichroic liquid crystal displays
LCD CONTROL LCD controller
KB﹠LED CONTROL button and LED light control
DATA﹠amp; ADDR BUS data and address bus
The control of MEMORY CONTROL storer
LCD﹠amp; KEYBOARD DRIVER liquid crystal and keypad drive
NOR FLASH nonvolatile flash memory
SDRAM is Synchronous Dynamic Random Access Memory, and synchronous DRAM is meant Memory need of work synchronous clock synchronously, and the transmission of inner order and the transmission of data are benchmark with it all; Being meant dynamically that storage array need constantly refresh guarantees that data do not lose; Be meant that at random data are not that linearity is stored successively, but free assigned address carries out reading and writing data.
NAND FLASH nonvolatile flash memory
EEPROM EEPROM (Electrically Erasable Programmable Read-Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memo)
I
2C EEPROM I
2The EEPROM (Electrically Erasable Programmable Read Only Memo) of C interface
DDR-SDRAM DDR SDRAM is the abbreviation of Double Data Rate Synchronous Dynamic RandomAccess Memory (double data rate random access memory), is the memory standard that is proposed in order to contend with RDRAM by companies such as VIA.DDR SDRAM is the renewal product of SDRAM, adopt the 2.5v operating voltage, it allows in the rising edge of time clock and negative edge transmission data, the frequency that does not need to improve clock so just can double to improve the speed of SDRAM, and have than SDRAM and Duo one times transfer rate and memory bandwidth, for example DDR 266 compares with PC 133 SDRAM, and frequency of operation is 133MHz equally, but memory bandwidth has reached 2.12GB/s, doubles than PC 133 SDRAM.The chipset of main flow is all supported DDR SDRAM at present, is present the most frequently used type of memory.
DATA[63...0] data line (63...0 position)
DQS is a Bi-directional Data Strobe bi-directional data control pin
DM is the synchronous mark in the data mask data stream
The Addr address signal is write a Chinese character in simplified form
The Ctrl control signal wire
DAC Digitalto Analog Converter digital-to-analog conversion
ADC Analog to Digital Converter analog to digital conversion
The JTAG debugging interface of FPGA_JTAG FPGA
The program storage of FPGA program flashFPGA
PLL phaselocked loop (phase-locked loop):
ARM CLKARM chip clock
The output of PLL_CLK_out phase-locked loop clock
Analog out analog output channel
Analog in analog input channel
Realize the independent voltage output of 8 passages
With reference to figure 1-5, individual laboratory system integrating device of the present invention, it comprises power supply 1, it also comprises: mainboard 2 that links to each other with power supply 1 and drive plate 3, and the voltage output interface VOUT0-VOUT7 on the drive plate 3, this mainboard 2 is provided with CPU201 and FPGA202, the wherein execution of CPU operation system (for example LINUX) and application software (user can write as required voluntarily), application software are responsible for the instruction of interprets external input equipment (communication port or panel operation) and its conversion and control are instructed; FPGA accepts the steering order that CPU sends, and produces various control timing, control D/A converter 203, A/D converter 204 read-writes, pwm signal, I
2C, SPI agreement sequential etc.In the present embodiment, CPU receives the instruction of output voltage and converts thereof into steering order, this steering order is passed to FPGA by control channel, this FPGA produces the voltage output timing with control D/A converter output analog voltage according to this steering order, this D/A converter amplifies driver module 301 by the analog output channel with the electric current and voltage on this analog voltage input drive plate, the signal that this analog voltage amplifies driver module through this electric current and voltage amplifies and drives the back by the output of the voltage output interface VOUT0-VOUT7 on the drive plate, the electric signal trend referring to figs. 2 and 3 the filled arrows direction.D/A converter (can produce 4 road voltage signals) cooperates multi-way switch (figure does not show) can distinguish the voltage output that produces 8 passages simultaneously in the present embodiment, and every road voltage is adjustable separately, promptly voltage parameter is imported simultaneously during user input instruction.The voltage output of 8 passages can be satisfied most electronic circuit experiment demand.In the present embodiment, the experimental interface that the user only needs experimental subjects is connected on this drive plate promptly can be used as voltage source, if and need adjust voltage swing in the experimentation, the user only needs the instruction input CPU that will adjust magnitude of voltage to get final product, need not to buy a plurality of regulated power supplies, carry out the voltage adjustment by coarse adjustment micromatic settings such as knobs, as for concrete voltage input mode, can be undertaken by PC or the control panel that is connected with mainboard, user's instruction is by the USB interface of PC, the control channel of serial ports etc. or control panel is transferred into the CPU of mainboard, here only illustrate, those skilled in the art can select other known approaches to carry out instruction control according to self needs.
In order to prevent that the output voltage overcurrent-overvoltage from damaging load and peripheral components and parts, the voltage source after voltage, electric current amplify the driver module driving behind overcurrent protection and current detection module 302, is exported by the voltage output interface on the drive plate.In the present embodiment, voltage output in every road all is provided with over-current over-voltage protection, to prevent the damage to experimental subjects or peripheral electronic devices and components.The specific implementation of overcurrent and overvoltage protective module can be by those skilled in the art according to the suitable known approaches of self needs selection.
In the time of the voltage of this external output certain value; the user can also measure the size of current of current time voltage output channel in real time; described analog voltage signal after overcurrent and overvoltage protective module detects is sent to a current detection module 303; current detection module detects the current signal that the voltage output channel flows through in real time; this current detection module comprises sampling resistor and differential amplification module; wherein sampling resistor is obtained current signal; after differential amplification and amplitude conditioning, the A/D converter of sending on the mainboard by analog input channel carries out analog to digital conversion again.Read the ADC transformation result by FPGA, send into CPU, convert corresponding current value to through the CPU compensation with after calculating.
Output voltage described in this enforcement, output current are measured, Digital I is controlled voltage, input voltage is measured all by demarcating and verification, and its precision can be controlled in 5 ‰, can be that benchmark is demarcated by adopting a high-precision digital multimeter for the control of precision.The output of individual's laboratory system integrating device and measure each input and output passage and all need demarcate respectively, with reference to figure 4, demarcating steps is as follows:
1, computing machine 400 sends output or the instruction of measurement target value to individual laboratory system integrating device 500;
2, individual laboratory system integrating device 500 conversion back export target values are to fictitious load 800 or read in measured value;
3, computing machine 400 reads in the actual value of measurement from high accuracy number multimeter 600;
4, PC calculates a suitable compensation coefficient and it is write individual laboratory system integrating device according to the relation of desired value and actual value, and individual laboratory system integrating device will use the controlled quentity controlled variable of corresponding compensation coefficient correction output and input;
5, repeat above step, can obtain one group of penalty coefficient, deposit in the individual laboratory, the compensation that the input and output amount is carried out with these group data in the laboratory is calculated, and the gap between desired value and the actual value is narrowed down in the minimum scope.
Demarcation with output voltage is an example below, adopt the high precision multimeter of Keithley to demarcate in the present embodiment, as shown in Figure 4, send instruction by computing machine 400 to individual laboratory system integrating device 500, export a magnitude of voltage to fictitious load, adopt the voltage of high precision multimeter 600 these outputs of measurement then and measured value is sent back computing machine, calculate one group of penalty coefficient, this group penalty coefficient after calculating is deposited in the individual laboratory installation, send the instruction of output voltage again by computing machine, new output valve is used the result after compensation is calculated, measure the output voltage values of this moment and feed back to PC with the high precision multimeter once more and verify, so repeatedly, not stopping the correction-compensation coefficient in the scope that the precision of output voltage is requiring, is 5 ‰ in this example.Owing to the difference of experimental subjects, the parameter of electronic devices and components is also different, and those skilled in the art can select other existing scaling method and demarcation benchmark that output voltage is carried out the verification demarcation according to the needs of experiment or research and development.
Output of the voltage of 8 passages and real-time current detection can be applicable to multiple occasion, for example to the characteristic test of electronic components such as diode, triode.With the output characteristic curve of testing a triode is example, and traditional method needs two variable voltage sources, two reometers, and a voltage table is built a test platform, and manually the point-to-point measurement described point takes time and effort.Adopt individual laboratory integrating device, then only need a triode to be tested, three connecting lines and a resistance,, send one group of voltage, Current Control and measurement instruction, finish collection of experiment data simply, fast and automatically by the PC interface.As cooperate drawing show tools (Excel or other software), direct display characteristic curve then.The instruction that the user also can provide according to the laboratory integrating device, (as: VC++, VB Labview), realize the function of multiple instrumentation and instrument to the utilization various development tools fast.
Realize that the input of 8 passage independent voltages detects
With reference to figure 1; Fig. 5-7; in order to realize that the input of 8 passage independent voltages detects; also comprise an aanalogvoltage input buffering module 304 that links to each other with this overcurrent and overvoltage protective module 302 on this drive plate 30; the aanalogvoltage of outside input passes through overvoltage protection successively; the adjustment of buffer compartment information amplitude; promptly outside (experimental subjects) is by voltage input interface AIN_0; AIN_1...AIN_7 input analog voltage signal; behind excess voltage protection; sending into aanalogvoltage input buffering module again cushions and level conversion; the A/D converter of sending into afterwards on the mainboard carries out analog to digital conversion; read the ADC transformation result by FPGA; send into CPU; convert the correspondent voltage value to through CPU compensation with after calculating again, be presented on the guidance panel or deliver among the PC and handle by the PC interface.
With reference to figure 1, Fig. 5, Fig. 8-9, in order to realize 2 passage independent currents, CPU receives the instruction of output current and converts thereof into steering order, this steering order is passed to FPGA, this FPGA is according to this steering order, produce the control timing logic of D/A converter 203, export an analog voltage, driven with current sources module 305 on this analog voltage input drive plate, this driven with current sources module 305 converts this analog voltage to current source, exports from laboratory interface I_Source0, I_Source1.Every road current source output current is all adjustable separately, the user realizes output current regulating by PC communication or panel operation, it is prior art that voltage source changes current source circuit, and those skilled in the art can select suitable functional module or available circuit to realize according to self needs.
In addition, consider practical application, comprised circuit overcurrent protection in the possible current source circuit designs.
With reference to figure 1, Fig. 5 and Figure 10, in order to realize 2 tunnel PWM passages independently, also be provided with the PWM output interface on the mainboard, wherein CPU receives the instruction that produces pwm signal, and this steering order is passed to FPGA, and this FPGA produces pwm signal according to this steering order.The interface circuit of PWM on drive plate directly outputs to the laboratory interface and uses for experimental subjects.The user can regulate the output frequency and the dutycycle of pwm signal at any time by input instruction.
Realize the Digital I that 40 road level are adjustable
With reference to figure 1, Fig. 5, Figure 11-12, the Digital I of Figure 12 A in order to realize that 40 road level are adjustable, the mode of reference example 1 is exported three tunnel Digital I control voltage: high level voltage Vhigh, low level voltage Vlow and threshold voltage Vth, the output of Digital I adopts the high speed analog multichannel switch to be directly connected to the adjusting and the output of high level voltage or low level voltage realization Digital I level, and the Digital I input is then judged supplied with digital signal 1 or 0 according to Vth.For instance, the user is provided with respectively: high level voltage Vhigh is 5V, and low level voltage Vlow is 0.8V, and threshold voltage Vth is 1.3V, and when then exporting digital signal 1, the Digital I of experimental interface is the 5V level, and output 0.8V was to the Digital I of experimental interface in 0 o'clock.When Digital I was done input, input signal was 1 greater than the threshold voltage 1.3V value of reading in, and is 0 less than the threshold voltage 1.3V value of reading in.
When Digital I is connected with external devices, also can be used as the short circuit and the out of circuit test of connection.With reference to Figure 13, be the synoptic diagram of short-circuit test, n IO interface linked to each other with experimental subjects, n is provided with for example 3.3V of Vhight output vdd voltage smaller or equal to 40, and Vlow exports 0V, scan all Digital I successively, scan-data form: 1111110,1111101,1111011, ...., 0111111, test the electric current I _ High of Digital I power supply simultaneously, I_Low. according to I_High, whether I_Low can be had the conclusion of IO short circuit easily.With reference to Figure 14, synoptic diagram for out of circuit test, VHight output vdd voltage is set, very little negative voltage of VLlow output (as-0.4V), scan all Digital I successively, test the electric current I _ High of Digital I power supply simultaneously, I_Low, connecting as this Digital I of the too small then decidable of measuring current is to open circuit.
Support various protocols
With reference to figure 15-16, in order to support various protocols, CPU is according to the configuration-direct of communications protocol, distribute corresponding IO, data layout and data transmission frequency are set, and this agreement steering order is sent into FPGA, and FPGA produces the control corresponding clock signal according to this agreement steering order.When needs pass through the protocol transmission data of setting, only need can finish by the data access instruction, wherein said agreement is I
2C, SPI agreement.Be that the user can dispose arbitrarily and uses which Digital I to be communication interface, with I
2The C agreement is an example, needs clock signal, data-signal, enable signal etc., and the user can define Digital I: IO3, IO20, IO21 are respectively clock signal, data-signal, enable signal, start I2C transmission data afterwards, Digital I: IO3, IO20, IO21 will be according to I
2The C agreement is carried out data transmission.Concrete data directly use the data access instruction to realize.
With reference to Figure 17, be individual laboratory system integrating device application platform synoptic diagram.Wherein PC 400 or guidance panel 300 produce control or operational order, testing laboratory 500 carries out corresponding order, for subjects 900 provides drive signal or test data necessary, and the result returned output to display panel, perhaps the result is returned the self-editing test procedure of user, perhaps be sent to PC by communications protocol.
Though more than described the specific embodiment of the present invention, it will be understood by those of skill in the art that these only illustrate, protection scope of the present invention is limited by appended claims.Those skilled in the art can make numerous variations or modification to these embodiments under the prerequisite that does not deviate from principle of the present invention and essence, but these changes and modification all fall into protection scope of the present invention.
Claims (9)
1. individual laboratory system integrating device, it comprises power supply, and mainboard that links to each other with power supply and drive plate is characterized in that, and this individual's laboratory system integrating device also comprises:
The voltage output module is used to export the independent adjustable voltage of hyperchannel;
The real-time current measurement module is used for the electric current that the measuring voltage passage flows through in output voltage;
Current source module is used to export the independent adjustable current source of hyperchannel electric current;
Voltage input detection module is used to measure the external input voltage of multichannel;
The Digital I level switch module is used to realize the level conversion of Digital I input and output;
The communications protocol control module is used to realize the transmitting-receiving of multiple kinds.
2. individual laboratory system integrating device as claimed in claim 1; it is characterized in that; the independent adjustable voltage of output hyperchannel; this individual's laboratory system integrating device mainboard is provided with CPU and FPGA; wherein CPU receives the instruction of output voltage and converts thereof into steering order; this steering order is passed to FPGA; FPGA produces DAC conversion and control sequential according to this steering order; the output aanalogvoltage; this aanalogvoltage is through voltage; after electric current amplifies the driver module driving; pass through overcurrent protection and current detection module again, export by the experimental interface voltage output end on the drive plate.
3. individual laboratory system integrating device as claimed in claim 2, it is characterized in that, also comprise real-time hyperchannel current detecting, current detection module detects the current signal that the voltage output channel flows through in real time, this current detection module comprises sampling resistor and differential amplification module, wherein sampling resistor is obtained current signal, after differential amplification and amplitude conditioning, the A/D converter of sending on the mainboard by analog input channel carries out analog to digital conversion again, read the ADC transformation result by FPGA, send into CPU, after the CPU compensation is calculated, convert corresponding current value to.
4. individual laboratory system integrating device as claimed in claim 1; it is characterized in that; comprise that also multichannel voltage detects; the analog voltage signal of outside input via excess voltage protection after; send into aanalogvoltage input buffering module again and cushion and level conversion, the A/D converter of sending into afterwards on the mainboard carries out analog to digital conversion, reads the ADC transformation result by FPGA; send into CPU, after the CPU compensation is calculated, convert the correspondent voltage value to.
5. individual laboratory system integrating device as claimed in claim 1, it is characterized in that, this drive plate also comprises a plurality of current source output channels, the instruction of CPU received current source output current, calculate the control corresponding amount, and convert thereof into steering order, this steering order is passed to FPGA, FPGA produces the D/A converter control timing according to this steering order, through DAC output analog control voltage value, driven with current sources module on this analog voltage input drive plate, this driven with current sources module converts this magnitude of voltage to current source, exports by the current source output interface on the drive plate.
6. individual laboratory system integrating device as claimed in claim 1, it is characterized in that, this device also comprises input, the digital I/O interface that output level is adjustable, adopt the voltage way of output as described below to export three tunnel Digital I control voltage, it is respectively the digital signal high level voltage, low level voltage and threshold voltage: CPU receives the instruction of output voltage and converts thereof into steering order, this steering order is passed to FPGA, FPGA produces DAC conversion and control sequential according to this steering order, the output aanalogvoltage, this aanalogvoltage is through voltage, after electric current amplifies driver module and drives, through behind overcurrent protection and the current detection module as the reference data of Digital I input and output; Wherein high level voltage, low level voltage switch by the multiway analog switch device, realize the adjusting of Digital I input, output level, and threshold voltage is connected to multiway analog switch and differentiates as Digital I input signal 0 and 1 thresholding.
7. individual laboratory system integrating device as claimed in claim 6, it is characterized in that, the output of Digital I adopts the high speed analog multichannel switch to be directly connected to high level voltage passage or low level voltage passage, realize the level adjustment of Digital I, the scanning output of utilization Digital I, cooperation realizes Digital I is connected the detection of open circuit and short circuit to the current measurement of high level and low level passage.
8. individual laboratory system integrating device as claimed in claim 1, it is characterized in that, the Digital I of experimental interface, the IO that disposes appointment flexibly by FPGA becomes data, clock line and the control line of I2C, SPI communications protocol, under FPGA control, realize the communication sequential of I2C, SPI, realize exchanges data with experimental subjects.
9. individual laboratory system integrating device as claimed in claim 1, it is characterized in that it also comprises pwm signal output, CPU receives the instruction of PC or guidance panel, convert corresponding PWM frequency and dutyfactor value to and be sent to FPGA, FPGA is according to the corresponding pwm signal of controlled quentity controlled variable output of CPU.
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| CN201010273261A CN101957410B (en) | 2010-09-03 | 2010-09-03 | Personal laboratory system integrating device |
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| CN108255222A (en) * | 2018-02-08 | 2018-07-06 | 中国航发贵州红林航空动力控制科技有限公司 | A kind of control system of multichannel current loading |
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