CN112098740A

CN112098740A - Intelligent comprehensive test instrument

Info

Publication number: CN112098740A
Application number: CN202010703663.5A
Authority: CN
Inventors: 周宇; 王宏臣
Original assignee: Guangzhou Sicheng Technology Co ltd
Current assignee: Guangzhou Sicheng Technology Co ltd
Priority date: 2020-07-21
Filing date: 2020-07-21
Publication date: 2020-12-18

Abstract

The invention discloses an intelligent comprehensive test instrument which comprises a main chip CPU, a storage, a flash memory, an FPGA chip and a service module, wherein the main chip CPU is connected with the FPGA chip, the FPGA chip is connected with the service module, a plurality of pin connectors are connected on the service module, a temperature sensor is arranged on the main chip CPU and is connected with a cooling fan, the main chip is connected with a power module, an SPI host I, an SPI host II and an SPI host III are arranged on the main chip, an SPI slave I, an SPI slave II and an SPI slave III are arranged on the FPGA chip, and the SPI host I, the SPI slave II and the SPI slave III are correspondingly connected. The invention has the advantages of diversified functions, flexible test, small volume, light weight, strong expansibility and low cost.

Description

Intelligent comprehensive test instrument

Technical Field

The invention belongs to the technical field of test equipment, and particularly relates to an intelligent comprehensive test instrument.

Background

In order to obtain various parameters of the equipment, a testing instrument is generally required. Current test instruments, generally have the following disadvantages:

1. the traditional test instruments are manufactured by specific manufacturers, designed hardware resources are more, and the traditional test instruments are in technical monopoly, so that the cost is higher, and the basic test equipment of brand test equipment manufacturers, namely Thireda and Agilent, are tens of thousands, hundreds of thousands or even millions, so that common buyers are difficult to bear;

2. traditional test instrument is bulky, generally places in specific place, and if need carry out to go out to test can be very inconvenient, and bulky volume can make the inconvenient test of tester moreover.

The traditional instrument has more keys, for example, a digital oscilloscope has buttons of scanning frequency, longitudinal resolution, signal triggering and the like, and the buttons need to be familiar with by professionals, and if an operator is relatively careless, the instrument can be damaged due to misoperation.

Disclosure of Invention

In order to solve the technical problems, the invention provides an intelligent comprehensive test instrument with diversified functions and flexible test.

In order to solve the technical problems, the invention adopts the following technical scheme:

the utility model provides an intelligent comprehensive test instrument, including main chip CPU, the accumulator, the flash memory, FPGA chip and service module, main chip CPU is connected with the FPGA chip, the FPGA chip is connected with the service module, be connected with a plurality of pin connector on the service module, be equipped with temperature sensor on the main chip CPU, this temperature sensor and radiator fan, main chip is connected with power module, be equipped with SPI host computer I on the main chip, SPI host computer II, SPI host computer III, be equipped with SPI slave machine I on the FPGA chip, SPI slave machine II, SPI slave machine III, SPI host computer I, SPI host computer II, SPI host computer III and SPI slave machine I, SPI slave machine II, SPI slave machine III corresponds the connection.

The main chip CPU is a four-core full log A40i main control chip, and is connected with a plurality of DDR3 through a double-speed random access memory interface on the main chip, the DDR3 form a storage, the four-core full log A40i main control chip is provided with four processors, one of the processors is responsible for running a waveform generator, and the other processor is used for running wave data.

The number 1 IO port on the main chip CPU is connected with the interrupt controller on the FPGA and used for receiving signals of the interrupt controller, the number 2 IO port is connected with a reset key on the FPGA and used for receiving reset signals, the number 3 IO port is used for reading whether signals read by the FPGA are effective or not, the number 4 IO port is used for reading whether signals written by the FPGA are effective or not, and the number 6 IO port is connected with a loading port of the FPGA and used for directly loading engineering inside the FPGA chip when the system is powered on.

The FPGA chip comprises a main register, a sub-register and a vector generator, wherein the sub-register is connected with the main register and comprises a version register, a reset register, an LED register, a PWM register, a user relay register, a switch switching register, a time measuring unit register, an I2C main equipment register, an SPI relay switching register, an SPI writing register, an SDIO slave wave data register and an SDIO slave vector register, the FPGA is connected with a 24MHZ clock, the clock signal is multiplied to 125MHZ in the FPGA chip, the vector generator is connected with the SDIO slave wave data register through a double-channel wave data memory, the SDIO slave vector register is connected with the vector generator through the double-channel vector generator memory, and the SPI writing register is connected with the SPI relay switching register;

the master control chip of the whole log A40i is controlled by the SPI host I and the master register and the sub-register of the FPGA chip, and is communicated with the FPGA chip through the SPI host II, the record of the waveform is read back from the dual-channel wave storage in the FPGA, and the command of the waveform generator to be executed is written into the memory of the FPGA chip by using the SPI host III.

And the main chip is provided with a USB interface, a network interface and a JTAG interface.

The service module comprises a user relay module, a level conversion module, a time measurement module, a device power supply module, a precision measurement unit module, a digital multimeter module, 32 paths of pattern channels, 2 paths of I2C channels and 1 path of SPI channel, and the service module is connected and communicated with the FPGA chip through the SPI bus, the I2C bus and the IO interface.

The power module comprises a switching power supply, the switching power supply is connected with three output circuits, each output circuit is connected with a voltage stabilizer, the voltage stabilizer is connected with a secondary voltage stabilizer, and the output voltage of the secondary voltage stabilizer is connected with a power utilization tail end.

The invention has the following beneficial effects:

1. the multifunctional integrated tester integrates multiple functions, realizes functional diversity and testing flexibility, and even realizes measurement which cannot be realized by a traditional instrument;

2. each chip is integrated on one board, so that the size is small, the weight is light, the expansibility is strong, and the cost is low;

3. the problems of resource configuration, repetition and the like are well solved by using a modularized instrument based on software configuration;

4. the universal interface is used for communication with the computer, and the virtual operation interface of the computer is used, so that the method is simple and flexible.

Drawings

FIG. 1 is a schematic diagram of the module connection of the present invention;

FIG. 2 is a schematic diagram of the structure of an FPGA chip in the invention;

fig. 3 is a schematic diagram of the power module of the present invention.

Detailed Description

For further understanding of the features and technical means of the present invention, as well as the specific objects and functions attained by the present invention, the present invention will be described in further detail with reference to the accompanying drawings and detailed description.

As shown in attached figures 1-3, the invention discloses an intelligent comprehensive test instrument which comprises a main chip CPU, a storage, a flash memory, an FPGA chip and a service module, wherein the main chip CPU is connected with the FPGA chip, the FPGA chip is connected with the service module, a plurality of pin connectors are connected on the service module, a temperature sensor is arranged on the main chip CPU, the temperature sensor is connected with a cooling fan, the main chip is connected with a power module, an SPI host I, an SPI host II and an SPI host III are arranged on the main chip, an SPI slave I, an SPI slave II and an SPI slave III are arranged on the FPGA chip, and the SPI host I, the SPI host II, the SPI slave III and the SPI slave I, the SPI slave II and the SPI slave III are correspondingly connected. The temperature sensor is used for detecting the heat productivity on the main chip, controlling the operation power of the cooling fan and ensuring timely and effective cooling treatment.

The main chip CPU selects a domestic four-core anzhi A40i chip, and is connected with a plurality of DDR3 through a double-speed random access memory interface on the main chip, the DDR3 form a storage, the four-core anzhi A40i chip is provided with four processors, one of the processors is responsible for running a waveform generator, and the real-time communication between A40 and FPGA is ensured not to be interrupted abnormally, so that the communication is abnormal; one of the processors is used for operating wave data, and the real-time communication between the CPU of the main chip and the FPGA chip is guaranteed not to be interrupted abnormally. In this embodiment, 2 DDR3 double-rate synchronous dynamic random access memories of 1G size are selected, and a 4G EMMC chip is used as a flash memory. The number 1 IO port on the main chip CPU is connected with the interrupt controller on the FPGA and used for receiving signals of the interrupt controller, the number 2 IO port is connected with a reset key on the FPGA and used for receiving reset signals, the number 3 IO port is used for reading whether signals read by the FPGA are effective or not, the number 4 IO port is used for reading whether signals written by the FPGA are effective or not, and the number 6 IO port is connected with a loading port of the FPGA and used for directly loading engineering inside the FPGA chip when the system is powered on.

A reset key is also arranged in the main chip CPU, and the reset is realized when the control system is powered off.

The main chip is provided with a USB2.0 interface, a network interface and a JTAG interface, and is convenient to be butted with an external device.

The FPGA chip includes the main register and the minute register of being connected with this main register, the vector generator, divide the register to include the version register, reset register, the LED register, the PWM register, user relay register, the switch switches over the register, the time measurement unit register, I2C master register, SPI relay switches over the register, SPI writes the register, SDIO subordinate wave data register, SDIO subordinate vector register, the vector generator passes through the binary channels wave data memory and is connected with SDIO subordinate wave data register, SDIO subordinate vector register passes through the binary channels vector generator memory and is connected with the vector generator, SPI writes the register and switches over the register with SPI relay and is connected.

In addition, the FPGA chip is externally connected with a 24MHZ clock, and the frequency of a clock signal is multiplied to 125MHZ through the frequency multiplication of a phase-locked loop in the FPGA chip, so that the running speed in the chip is improved.

The whole log A40i chip is controlled by the SPI host I and the main register and the sub-register of the FPGA chip, and is communicated with the FPGA chip by the SPI host II, the record of the waveform is read back from the dual-channel wave storage in the FPGA, and the command of the waveform generator to be executed is written into the memory of the FPGA chip by using the SPI host III.

The service module comprises a user relay module, a level conversion module, a time measurement module, a device power supply module, a precision measurement unit module, a digital multimeter module, 32 paths of pattern channels, 2 paths of I2C channels and 1 path of SPI channel, and the service module is connected and communicated with the FPGA chip through the SPI bus, the I2C bus and the IO interface. The SPI channel includes a 1 channel and a 0 channel.

As shown in fig. 3, the power module includes a switch power supply LRS-150-48, which inputs 220V ac power to the switch power supply, and outputs 3 paths of 48V voltages after voltage reduction and stabilization, one path of 2A current, one path of 0.35A current, and one path of 0.83A current; the output 3 circuits are subjected to voltage stabilization again through an LMR16030 voltage stabilizer, 5V2A output by the LMR16030 is connected to an A40i chip, 5V0.3A is connected to a cooling fan, 28V2A directly supplies power to A4-circuit power supply unit DSP, other output voltages are respectively connected to TPS54202, TPS54260 and TPS54202 type voltage stabilizers to output voltage and current of 5V2A to other modules, the TPS54260 outputs negative voltage, and output signals are output to other modules through an MC78M05 module. Through the series of current-voltage conversion, the voltage of 220V is reduced and rectified to supply power to devices with different voltages and currents, and the requirements of each module are efficiently and stably met. According to different requirements, different currents can be output, and the voltage regulators used in the method are all known existing products.

The management circuit of the network interface and the like are conventional circuits and are not described in detail herein.

In the invention, the FPGA chip creates various types of registers, the A40i chip configures a main register and a sub-register of the FPGA chip for service control through a 0 channel of an SPI channel, and controls an SDIO slave wave data register, a dual-channel wave data memory, a vector generator and a dual-channel vector generator memory of the FPGA chip through the 0 channel and a 1 channel of an SDIO to realize the vector data exchange of a service interface.

The version information is obtained by reading the line level in the version register, and different values of the register read by the A40i chip represent different version information.

In the reset register, six reset modes are provided according to different pressing time of the external key, and the output register values after reset are different and reset to different states.

In the LED register, the control signal is input to the LED control register, so that the change of the flicker frequency, the inversion of the polarity level, the change of the initial state, the change of the mode and the enable bit can be realized, and the LED control register has multiple control functions.

The PWM register can be used for duty ratio setting, frequency setting and enabling bit setting. The PWM can be changed by writing the value of the register.

The UR user relay register controls 32 IO ports with 32 bits, UR output 1 controls IO port to be high level, and output 0 controls to be low level.

The switch switching module is provided with TTL (level conversion) control, DPS (device power supply unit) enabling, PMU (precision measurement Unit) voltage or current gear adjusting, PE (analog generator) voltage gear adjusting, DMM (digital multimeter) configuration and self-calibration switch configuration.

The I2C master register comprises a control register and a data register, and is an I2C master register configured by an A40I chip through an SPI (serial peripheral interface) so as to control a device to be hung down, and the operation is divided into writing operation and reading operation.

The TMU time measurement unit register may perform duty cycle configuration, wait enable, line test configuration.

And the PE analog generator register can perform functions of driving level output, integral translation of analog signals, signal change moment following, realization of independent configuration waveform of 32 channels and the like.

In addition, the invention adopts the dynamic generation pattern test sequence, and can simulate any waveform output so as to simulate any data transmission protocol. At present, the internal function is provided with a software interface of an I2C protocol and an SPI protocol, and a user can directly use the interface to directly test the read-write erasing function of a corresponding chip; and a corresponding interface is provided for the user to write the waveform by himself, and any protocol is simulated. The method can also enter a waveform comparison mode so as to accurately measure the waveform period, the frequency and the duty ratio, and can also measure the edge change time of a rising edge and a falling edge to form a corresponding waveform periodic chart. The MODE of the MODE register may be configured.

MODE _ ZERO ═ 4'd 0; the driving level outputs a low level;

MODE _ ONE ═ 4'd 1; the driving level outputs a high level;

MODE _ NRZ ═ 4'd 2; the DT0 rising edge data changes; ignore DT 1; namely, clocks

The phase shifts integrally according to DT 0;

MODE _ DNRZ ═ 4'd 3; high DT0 changes immediately at time, low DT1 waits

Change at any moment;

MODE _ RZ ═ 4'd 4; the high DT0 changes immediately at the moment and continues to DT1

Changing back to a low level;

MODE _ RO ═ 4'd 5; the low level DT0 changes immediately at the moment and continues to change back to the high level at the moment DT 1;

the output waveform format MODE of the 32-channel independent configuration of the SPI channel can be realized, and the time parameters DT0\ DT1 are set.

In addition, the method aims at the function of each module in the business module.

The TMU (time measurement module) has two operating states. Default 0 operating state: the dual channels measure the test signals, and can measure the rising edge, the falling edge, the period, the duty ratio and the frequency of the signals; 1, working state: the dual channel can measure the delay of the test signal, such as time, period, frequency and duty ratio.

DMM (digital multimeter) modules have voltage and current measurement capabilities and, at the same time, can be used to calibrate internal measurement circuitry. The voltage measurement range is plus or minus 50V and the current measurement range is plus or minus 2A.

The UR (user relay) module uses software to directly control the relay to switch different channels, and has 32 UR paths in total.

The PMU (precision measurement Unit) module supports FIMV (output Current measurement Voltage) and FVMI (output Voltage measurement Current) functions, the voltage range is plus or minus 10V, and the current range is plus or minus 200 mA.

And 5, the DPS (device power supply module) module is provided with 4 power supply channels, the power supply voltage ranges from 3V to 24V, the power supply current ranges from 0A to 1A, and meanwhile, the current and the voltage of the DPS module are monitored by the system.

The 6.32 pattern channels, namely PE (pattern generator) modules, have 32 io ports in total, all the io ports have programmable functions so as to be adapted to digital interfaces of different protocols, the serial port level supports 3.3V and 5.0V, and meanwhile the io ports support the requirement of open-short circuit test of the 32 channels.

And 7, a tsensor temperature sensor module for monitoring the temperature of the part with larger internal heat productivity of the intelligent comprehensive tester.

8. And the cooling fan module controls the fan by using one path of PWM and controls the rotating speed of the fan through a temperature sensor.

And the TTL (level conversion) module is used for sorting test products by the sorting machine and has 16 paths of control signals, wherein 8 paths of output and 8 paths of input are realized, and the level of an external interface is 5.0V.

The following is a description of specific test examples.

Example 1

The PCBA (a complete bare board of all electronic components on a PCB) of the SD1100 red wine bottle opener is tested, namely whether the PCBA function of the red wine bottle opener is complete or not is verified, and the required function can be accurately realized.

Implementation content 1, whether the SD3100 battery and the power indicator GPIO are controllable or not and the battery path of the single board.

Firstly, a DPS interface of the comprehensive tester is connected to BAT +/BAT-, and 3.3V to 4.2V voltage is output for simulating the battery power supply of the wine bottle opener.

In the second step, different levels can be obtained by interfacing the PMU to the test points of test points LED1/LED2/LED3/LED 4.

And thirdly, obtaining the level of the LED test point and dividing the level into gears by changing the difference of the analog battery voltage, and obtaining the conclusion that the power indicator lamp is normal in controllability.

Implementing content 2, verifying the charging state and the full-power state of the single board:

in the first step, the DPS interface outputs a 5V voltage to the test point VCC to simulate the charging process.

And secondly, outputting 3.6V to the test point BAT +/BAT-by the DPS interface, simulating the charging state, and measuring the voltages of the test points STDBY and CHRG by using the PMM interface, wherein STDBY can be at a high level and CHRG can be at a low level.

And thirdly, measuring the voltage of the test point Red _ Control to be high level.

And fourthly, outputting 4.2V to the test point BAT +/BAT-by the DPS interface, simulating a fully charged state, and measuring the voltages of the test points STDBY and CHRG by using the PMM interface, wherein STDBY can be a low level and CHRG can be a high level.

The fifth step: and measuring the voltage of the test point Bule _ Control to be high level, and concluding that the charging path of the PCBA is normal, the blue red indicator lamp is controllable, the full-charge signal is normal, and the charging and full-charge test is passed.

Implementation 3, verification of the bottle opening and stopper removal functions:

in the first step, the voltage of 4V is provided for BAT +/BAT-through the DPS interface, and the power supply of a battery is simulated.

And secondly, giving a low-level signal to the test point KEY1 to simulate and trigger the function of an open bottle button.

And thirdly, measuring that the Red _ Control test point is at a high level, the OUTA is at a high level and the current is 2A by using the PMM interface.

And fourthly, giving a low-level signal to a test point KEY2 to simulate and trigger the function of the unplugged KEY.

And fifthly, measuring that the Blue _ Control test point is at a high level, OUTB is at a high level and the current is 2A by using a PMM interface.

And sixthly, concluding that the bottle opening and plug withdrawing functions of the single plate are normal, the red and blue indicator lamps display normal, and the motor has driving current.

Implementation content 4, verification limit switch:

Second, a low level analog trigger limit switch is provided to test point KEY 3.

Third, a low level analog trigger decap button is given to the test point KEY 1.

And fourthly, the test point Red _ Control is at a low level, the OUTA is at 0V, and the current is at 0A, so that the conclusion that the limit switch has a normal function is obtained.

Implementation 5, verification of sleep mode:

in the first step, the voltage 4V is provided for BAT +/BAT-through the DPS interface, and the power supply of the battery is simulated.

And secondly, giving a low level to the test point KEY1, entering an open bottle mode, waiting for 8S, and entering a sleep mode.

And thirdly, measuring the voltages of the test points LED1/LED2/LED3/LED4 to obtain the voltage of 0V.

Fourthly, the test point KEY1 is low-level, the system is awakened from the sleep mode, and the voltages of the test points LED1/LED2/LED3/LED4 are measured to obtain the voltage consistent with the power supply of the DPS.

And fifthly, obtaining a conclusion that the single board sleep mode is normal in function.

Example 2 the chip was tested for its normal logic state.

Firstly, a proper test environment is built.

And secondly, inputting different high and low levels to input pins of the chip to be tested.

And thirdly, reading the level of the output pin, drawing a vector table through the input and output values, and judging whether the logic state of the chip is normal.

Embodiment 3 the pattern waveform generator simulates a communication protocol signal to read and write a test chip, and verifies whether the chip function is complete.

Content 1, test PE simulates I2C communication protocol functionality:

firstly, a testing hardware environment is built, and a testing chip is loaded into a corresponding socket.

In the second step, the chip is powered through the DPS.

And thirdly, issuing an instruction by the user computer end to set a PE module simulation I2C of the intelligent comprehensive tester to communicate with the test chip.

And fourthly, acquiring the True information to indicate that the I2C of the test chip is normal in function.

Test content 2, test PE module simulation SPI communication protocol function:

In the second step, the chip is powered through the DPS.

And thirdly, the user computer terminal issues an instruction to set a PE module of the intelligent comprehensive tester to simulate the SPI to communicate with the test chip.

And fourthly, acquiring the True information to indicate that the SPI function of the test chip is normal.

Although the present invention has been described in detail with reference to the embodiments, it will be apparent to those skilled in the art that modifications, equivalents, improvements, and the like can be made in the technical solutions of the foregoing embodiments or in some of the technical features of the foregoing embodiments, but those modifications, equivalents, improvements, and the like are all within the spirit and principle of the present invention.

Claims

1. The utility model provides an intelligent comprehensive test instrument, a serial communication port, including main chip CPU, the accumulator, flash memory, FPGA chip and service module, main chip CPU is connected with the FPGA chip, the FPGA chip is connected with the service module, be connected with a plurality of pin connector on the service module, be equipped with temperature sensor on the main chip CPU, this temperature sensor and radiator fan, main chip is connected with power module, be equipped with SPI host computer I on the main chip, SPI host computer II, SPI host computer III, be equipped with SPI slave computer I on the FPGA chip, SPI slave computer II, SPI slave computer III, SPI host computer I, SPI host computer II, SPI slave computer I, SPI slave computer III correspond and connect, accumulator and flash memory are connected with main chip CPU respectively.

2. The intelligent integrated test instrument of claim 1, wherein the main chip CPU is a quad-core global lineage a40i master chip, which is connected to a plurality of DDRs 3 through a double data rate random access memory interface on the main chip, the plurality of DDRs 3 form a storage, and the quad-core global lineage a40i master chip has four processors, one of which is responsible for running a waveform generator and one of which is used for running wave data.

3. The intelligent integrated test instrument according to claim 2, wherein the No. 1 IO signal on the CPU of the main chip is connected to an interrupt controller on the FPGA for receiving a signal of the interrupt controller, the No. 2 IO port is connected to a reset key on the FPGA for receiving a reset signal, the No. 3 IO port is used for reading whether a read signal of the FPGA is valid, the No. 4 IO port is used for reading whether a write signal of the FPGA is valid, and the No. 6 IO port is connected to a load port of the FPGA for directly loading an internal project of the FPGA chip when the system is powered on.

4. The intelligent integrated test instrument of claim 3, wherein the FPGA chip comprises a main register and a sub-register and a vector generator connected to the main register, the sub-register comprises a version register, a reset register, an LED register, a PWM register, a user relay register, a switch switching register, a time measurement unit register, an I2C main device register, an SPI relay switching register, an SPI write register, an SDIO slave data register, an SDIO slave vector register, the FPGA is connected with a 24MHZ clock, the clock signal is multiplied to 125MHZ in the FPGA chip, the vector generator is connected with an SDIO (Serial digital input output) slave wave data register through a dual-channel wave data memory, the SDIO slave wave vector register is connected with the vector generator through the dual-channel vector generator memory, and the SPI write register is connected with the SPI relay switching register;

5. The intelligent integrated test instrument of claim 4, wherein the main chip is provided with a USB interface, a network interface, and a JTAG interface.

6. The intelligent integrated test instrument of claim 5, wherein the service module comprises a user relay module, a level conversion module, a time measurement module, a device power supply module, a precision measurement unit module, a digital multimeter module, a 32-way pattern channel, a 2-way I2C channel, and a 1-way SPI channel, and the service module is connected and communicated with the FPGA chip through an SPI bus, an I2C bus, and an IO interface.

7. The intelligent integrated test instrument of claim 6, wherein the power module comprises a switching power supply, the switching power supply is connected with three output circuits, each output circuit is connected with a voltage stabilizer, the voltage stabilizer is connected with a secondary voltage stabilizer, and the output voltage of the secondary voltage stabilizer is connected with the power consumption terminal.