CN101930799A - Non-volatile memory with error checking/correcting circuit and methods thereof for reading and writing data - Google Patents
Non-volatile memory with error checking/correcting circuit and methods thereof for reading and writing data Download PDFInfo
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Abstract
The invention discloses a non-volatile memory with an error checking/correcting (ECC) circuit and methods thereof for reading and writing data. Read-write operations are carried inside the memory, with ECC code words as the unit. The method for writing the data comprises the following steps: acquiring the head address and the end address of external input data and buffering the external input data; acquiring the bytes which are unnecessary to be replaced, namely write-back data, from a memory array of the non-volatile memory if part of the bytes in an ECC data set in which the external input data are included is unnecessary to be replaced; forming a new ECC data set with the external input data or the external input data and the write-back data and buffering the new ECC data set; generating a corresponding check bit for the new ECC data set; and writing the new ECC data set and the corresponding check bit into the memory array. The invention only erases the corresponding ECC code words during writing data and improves the memory flexibility and the utilization efficiency of the memory space.
Description
Technical field
Invention relates to nonvolatile memory, relates in particular to have error detection/correction (Error Checking and Correcting, ECC) nonvolatile memory of circuit and reading/writing method thereof.
Background technology
Along with the develop rapidly of integrated circuit, the integrated level of semiconductor memory is more and more higher, and capacity is also increasing.Thing followed problem is that the reliability and the yield rate of semiconductor memory faces serious challenge, reduce along with the increase of integrated level such as signal to noise ratio (S/N ratio), the reduction of the memory node quantity of electric charge makes the easier influence that is subjected to cosmic rays of storage cell, and process deviation under the deep sub-micron technique and fault in material cause the reduction of storer yield rate etc.
Error correcting code be a kind of not only can detect mistake and also can locate errors present and and then the class of correcting a mistake coding, be a kind of important fault-tolerant technique in the semiconductor memory.Hamming code is a kind of error correcting code commonly used, because it is simple, be easy to characteristics such as realization, is able to widespread use in storer.
According to the theory of Hamming code, the number of check bit need satisfy following relation in the Hamming code:
2
k〉=m+k+1 (formula 1)
Wherein:
K is the check bit number;
M is the data bit number.
By above-mentioned formula 1 as can be seen, the shared ratio of check bit is low more more at most for data bit, that is to say that to adopt the area overhead of ECC circuit more little.Such as, the data bit of 1 byte (byte) needs the check bit of 4 bits, and the area overhead of storage array is 50%; The data bit of 4 bytes then needs the check bit of 6 bits, and the area overhead of storage array is 18.8%.
For external interface is to be the nonvolatile memory with ECC circuit that unit carries out data transmission with the byte, in the prior art in order to solve the problem that reduces the memory area expense, generally adopt the ECC code word of multibyte data position, make check bit can take less ratio.But in realizing process of the present invention, when the inventor finds that memory inside is read and write, what prior art adopted is the ECC code word of multibyte data position, especially when writing new data to internal memory array, be with bigger mikey such as page or leaf (Page, as 128KB) operate, if discontented one page (the present right and wrong of this situation are usually seen) of input data volume, then can increase the write time, greatly reduce the storage dirigibility, very waste the space of write operation, and the serviceable life that unnecessary erase/program operations can reduce storer greatly in the operating process.
Summary of the invention
Technical matters to be solved by this invention is to be to provide a kind of the have nonvolatile memory of error detection/correction circuit and the reading/writing method of this storer, and memory inside is that unit carries out read-write operation with the ECC code word.
In order to solve the problems of the technologies described above, the invention provides and a kind ofly write the method for data continuously to nonvolatile memory with error detection/correction circuit, this method comprises:
Obtain the first address and the last address of outer input data;
According to described first address and the described outer input data of last address caching;
If the error detection/correction data set at described outer input data place has partial bytes not need to be replaced, then obtaining this byte that does not need to be replaced from the storage array of described nonvolatile memory is write-back;
With described outer input data, perhaps described outer input data and described write-back are formed new error detection/correction data set and buffer memory, described new error detection/correction data set of a clock period buffer memory;
For described new error detection/correction data set generates corresponding check bit;
Described new error detection/correction data set and corresponding check bit are written to described storage array.
Preferably, from described storage array, obtain the step of described write-back, comprise that with the error detection/correction code word be unit, from described storage array, read the error detection/correction code word at the data place of described first address and/or last address, therefrom obtain described write-back; Described error detection/correction code word comprises some error detection/correction data sets, and with the corresponding check bit of described some error detection/correction data sets; One of them error detection/correction data set includes some bytes.
Preferably, described outer input data is unit with the byte, and to described outer input data, perhaps described outer input data and described write-back are formed described new error detection/correction data set by latching.
Preferably, obtain the first address of described outer input data in described nonvolatile memory after, be described outer input data continuous dispensing memory address according to described first address, be assigned to till the described last address always.
In order to solve the problems of the technologies described above, the present invention also provides a kind of method from nonvolatile memory reading of data with error detection/correction circuit, it is characterized in that, be unit with the error detection/correction code word, reading of data from the storage array of described nonvolatile memory; Described error detection/correction code word, comprise some error detection/correction data sets and with the corresponding check bit of described some error detection/correction data sets, an error detection/correction data set includes at least two bytes.
Preferably, obtaining the address of the data place error detection/correction code word that will read, is unit reading of data from described storage array with described error detection/correction code word then.
Preferably, the external interface of described nonvolatile memory is that unit exports with the byte.
In order to solve the problems of the technologies described above, the present invention also provides a kind of nonvolatile memory with error detection/correction circuit, comprises storage array, error detection/correction circuit and impact damper, also comprises:
Input latch is used to receive outer input data;
Output latch links to each other with described error detection/correction circuit, is used to latch the error detection/correction data set after the described error detection/correction circuit of process is carried out error detection/correction, and wherein the error detection/correction data set comprises at least two bytes;
Selected cell links to each other with described impact damper, input latch and output latch, in the data writing operation process, from described input latch, in perhaps described input latch and the output latch, obtain data and form the error detection/correction data set, send to described impact damper.
Preferably, described selected cell from described input latch, is that unit obtains data with the error detection/correction data set in perhaps described input latch and the output latch.
Preferably, this nonvolatile memory further comprises storage array and write state machine, and the said write state machine is used to receive read operation instruction or write operation instruction;
According to described read operation instruction, be unit with the error detection/correction code word, reading of data from described storage array; Described error detection/correction code word, comprise some error detection/correction data sets and with the corresponding check bit of described some error detection/correction data sets, an error detection/correction data set includes at least two bytes;
According to described write operation instruction, obtain the first address and the last address of outer input data, and according to described first address and the described outer input data of last address caching; Whether the error detection/correction data set of judging described outer input data place has partial bytes not need to be replaced, be that then to obtain this byte that does not need to be replaced from described storage array be write-back, with described outer input data, perhaps described outer input data and described write-back, form new error detection/correction data set and be cached to described impact damper, described new error detection/correction data set of a clock period buffer memory.
Preferably, after the said write state machine obtains the first address of described outer input data in described nonvolatile memory, according to described first address is described outer input data continuous dispensing memory address, till being assigned to the last address of described outer input data in described storage array.
Preferably, described selected cell is under the selection signal effect that the said write state machine sends, and with described outer input data, perhaps described outer input data and described write-back are formed new error detection/correction data set.
Preferably, the said write state machine indicates described error detection/correction circuit that the data that read from described storage array are carried out error detection/correction by the Different Logic value of a control signal, perhaps is that described new error detection/correction data set produces check bit.
Preferably, described selected cell is made of some alternative MUX.
Preferably, this nonvolatile memory also comprises:
Output unit links to each other with described output latch, and being used for the byte is that unit exports described output latch latched data, comprises MUX.
Compared with prior art, be to be the nonvolatile memory that unit carries out data transmission with the byte for external interface among the present invention with ECC circuit, realized with the ECC code word be unit from storage array read data or in storage array write data, effectively reducing the ratio that check bit takies memory span, when saving the area overhead of check bit in the memory array, data are write fashionable the needs and are all indicated zone bit for each byte, only the ECC code word of correspondence is carried out erase operation, the dirigibility of storage and the utilization ratio of storage space have been improved, accelerated the speed of data write operation, having reduced simultaneously is that unit carries out the influence of read-write operation to the serviceable life of storer with the page or leaf.
Description of drawings
Fig. 1 is the composition synoptic diagram of nonvolatile memory one embodiment of the present invention.
Fig. 2 is the composition synoptic diagram of middle selected cell embodiment illustrated in fig. 1.
Fig. 3 is Data Position synoptic diagram among the read data operation embodiment.
Fig. 4 is the schematic flow sheet of read data operation embodiment.
Fig. 5 is a Data Position synoptic diagram among the data writing operation embodiment.
Fig. 6 is the schematic flow sheet of data writing operation embodiment.
Embodiment
Describe embodiments of the present invention in detail below with reference to drawings and Examples, how the application technology means solve technical matters to the present invention whereby, and the implementation procedure of reaching technique effect can fully understand and implements according to this.
Fig. 1 is the composition synoptic diagram of nonvolatile memory one embodiment of the present invention, and the external interface of this nonvolatile memory is unit transmission data with the byte.In the present embodiment, the ECC code word is 38 (bit), comprises ECC data set (ECC data set) and check bit, and wherein the ECC data set is 32, and check bit is 6.With 8 be 1 byte (byte), the ECC data set has 4 bytes (at least two bytes).Below as special declaration not, 1 ECC data set comprises 4 bytes among following each embodiment of the application, 1 byte comprises 8.
As shown in Figure 1, this storer embodiment mainly comprises storage array (Memory Array) 110, write state machine (Write State Machine, WSM) 120, row address decoder 125, column address decoder and sense amplifier 126, ECC circuit 130, impact damper 140, output latch (Latch) 150, output unit 160, input latch 170 and selected cell 180, wherein:
Storage array 110 links to each other with row address decoder 125 and column address decoder and sense amplifier 126, is used to store data; During read operation, be that unit is to column address decoder and sense amplifier 126 output datas with the ECC code word; During write operation, the ECC data set that reception column address decoder and sense amplifier 126 send over reaches and this ECC data set corresponding check bit and storage;
Write state machine 120 links to each other with row address decoder 125, column address decoder and sense amplifier 126, ECC circuit 130, output unit 160 and selected cell 180, is used for all sequential of control store read-write;
When read data is operated, send row address signal and the column address signal that is used to locate ECC code word address, described target data place according to read operation instruction respectively to row address decoder 125 and column address decoder and sense amplifier 126, sending one to ECC circuit 130 is used for the ECC data set is carried out the error detection/correction signal that error detection/correction is indicated, send one to output unit 160 and be used for carrying out the gating signal that byte is located at the ECC data set, this gating signal includes the byte locating information;
When data writing operation, instruction obtains the first address and the record of data to be written according to write operation, is follow-up input data allocations address and record according to this first address; Detection also judges whether the ECC data set at the data place of first address has partial bytes to be replaced, if then read the ECC code word at this partial bytes place that need be replaced from storage array 110; If the byte in the whole ECC data set all needs to be replaced, then needn't read the ECC code word at this ECC data set place; When receiving the information that stops to write of external control input, obtain the last address and the record of data to be written; Detection also judges whether the ECC data set at the data place of last address has partial bytes to be replaced, if then read the ECC code word at this partial bytes place that need be replaced from storage array 110; Send the selection signal that from input latch 170, reads outer input data according to the write operation instruction to selected cell 180, and the selection signal that from output latch 150, reads write-back, wherein this outer input data is the data to be written of outside input, with the byte is unit, this write-back also is unit with the byte for read and be written back to the data to be written in the storage array 110 from storage array 110; The data of aforesaid first address are outer input data; Also be used for sending a check bit that is used to the ECC data set to produce check bit and produce signal to ECC circuit 130;
Column address decoder and sense amplifier 126, link to each other with storage array 110, write state machine 120, ECC circuit 130 and impact damper 140, receive the column address signal that write state machine 120 is sent, during data writing operation, the ECC data set that reception sends over from impact damper 140 reaches and this ECC data set corresponding check bit, sends to storage in the storage array 110 then;
In the present embodiment, the data of being imported by this selected cell 180 comprise two kinds, a kind of is the outer input data of outside input, another kind is to read from storage array 110 and through the write-back of output latch 150 output, therefore this selected cell 180 is one group of alternative MUX, and they are selected data simultaneously and form the disposable output of ECC data set.
In the present embodiment, the quantity of this alternative MUX is 4, as shown in Figure 2.In selected cell shown in Figure 2 180, four alternative MUX are respectively the first MUX S1, the second MUX S2, the 3rd MUX S3 and the 4th MUX S4.Two input ends of these four alternative MUX link to each other with output latch 150 and input latch 170 respectively.Each alternative MUX, all be used under the selection signal effect that acts on separately, press byte (8bits) reading of data from output latch 150 or input latch 170, as shown in the figure, the selection signal that acts on the first MUX S 1 is the first selection signal Sel[1], the selection signal that acts on the second MUX S2 is the second selection signal Sel[2], the selection signal that acts on the 3rd MUX S3 is the 3rd selection signal Sel[3], the selection signal that acts on the 4th MUX S4 is the 4th selection signal Sel[4].The output terminal of these four alternative MUX links together, and is used for basis output separately, forms the ECC data set of a 32bits.The output latch 150 wherein and the capacity of input latch 170 are 32bits, and output latch 150 once receives the write-back of 32bits, and input latch 170 once receives the outer input data of 8bits.
Need to prove, why want write-back in the write operation process, be because the external interface of storer is that unit carries out read-write operation with the byte, and memory inside is that unit carries out read-write operation with the ECC code word, when the writing data into memory of a byte, its corresponding ECC code word just need write in the storage array 110 again; New ECC code word that the back obtains is accurately in order do not need in the ECC code word to guarantee data (being aforesaid write-back) that are replaced and the data (being aforesaid outer input data) of replacing to recombinate, so handle through error detection/correction earlier when in storage array 110, writing data, guaranteed that the ECC code word that writes is accurate.
As shown in Figure 1, impact damper 140 comprises data buffer (Data Buffer) 142 and check bit impact damper (Check_bit Buffer) 144, wherein:
Check bit impact damper 144, link to each other with column address decoder and sense amplifier 126 and ECC circuit 130, be used for storing the check bit that ECC data set that ECC circuit 130 stored for data buffer 142 is generated, because 32 bit data need 6 bit check positions, therefore in the present embodiment, this check bit is 6.
Below, further describe the characteristics of nonvolatile memory embodiment shown in Figure 1 by a read data operation embodiment and a data writing operation embodiment.
(1) read data operation embodiment
During read data, be unit reading of data from storage array with the ECC code word, wherein this ECC code word comprises ECC data set (ECC data set) and check bit.The present embodiment desire will be read the 3rd byte data1 of ECC data set in M ECC code word of storage array, the byte of band shade promptly shown in Figure 3.
Fig. 4 is the schematic flow sheet of read data operation embodiment, and in conjunction with nonvolatile memory embodiment shown in Figure 1 and Data Position shown in Figure 3 signal, this read data operation embodiment mainly comprises the steps:
Step S410, instruct according to read operation, write state machine 120 sends the row address signal and the column address signal of the ECC code word that is used to locate the data place that will read respectively to row address decoder 125 and column address decoder and sense amplifier 126, send one to ECC circuit 130 and be used for the ECC data set is carried out the error detection/correction signal that error detection/correction is indicated, also send one and be used for from the gating signal of ECC data set localizing objects data data1 to output unit 160;
Step S420, row address decoder 125 and column address decoder and sense amplifier 126 are deciphered this row address signal and column address signal respectively, obtain the row address information and the column address information of target data data1 place ECC code word respectively, and this row address information and column address information are sent to storage array 110;
Step S430, after storage array 110 is received this row address information and column address information of row address decoder 125 and column address decoder and sense amplifier 126 transmissions, according to those address informations (i.e. this row address information and column address information), this M ECC code word that will contain this target data data1 sends to ECC circuit 130 through column address decoder and sense amplifier 126, wherein this M ECC code word comprises ECC data set and check bit, treats that output data data1 is included in this ECC data set;
In this read data embodiment, be the data that will read 1 byte (8bits), the ECC code word of then reading from storage array 110 is 38 (bit); Comprise 32 ECC data set (an ECC data set comprises the byte of four 8bits) and 6 check bit in this ECC code word of 38, the target data data1 of 1 byte that this is to be exported is included in this ECC data set of 32;
Step S440, after ECC circuit 130 receives this M ECC code word, this error detection/correction signal according to 125 transmissions of write state machine, utilize the check bit in this M ECC code word that the ECC data set in this M ECC code word is carried out error detection/correction, the ECC data set after the acquisition error detection/correction;
Step S450, the ECC circuit 130 ECC data set after with this error detection/correction is sent to output latch 150;
Step S460, output unit 160 obtain target data data1 and output according to this gating signal from the ECC data set after this error detection/correction that output latch 150 is stored;
Because an ECC data set comprises the byte of four 8bits, therefore this output unit 160 is one or four to select a MUX, and so that the data in the output latch 150 are selected output by each byte, gating signal adopts the 2bits address signal, typically, choose minimum two bit address A[1:0].
In the embodiment of this read data operation, write state machine 120 is to this row address decoder 125 and column address decoder and sense amplifier 126 transmission address signals, send this error detection/correction signal to this ECC circuit 130, and to this four sequential of selecting this gating signal that a MUX sends, by 120 controls of write state machine, and do not have strict restriction, also be that abovementioned steps S410 and subsequent step do not exist strict sequencing.Such as in other read operation embodiment, write state machine 120 sends this error detection/correction signal to this ECC circuit 130, can be that this ECC circuit 130 receives after this ECC code word in abovementioned steps S420; And for example write state machine 120 is to this four this gating signal of selecting a MUX to send, can be that this ECC circuit carries out after the error detection/correction in abovementioned steps S440, perhaps the ECC data set of this ECC circuit after with this error detection/correction be sent to after this output latch 150 among the abovementioned steps S450.
The ECC data set of 4 bytes is once exported 1 byte, and 2 bit address are selected 1 gating signal as 4, and this 2 bit address is the low two of output data first address, owing to be continued operation, so add up according to this first address and 1 obtain in the address of follow-up data.
More than be to be that a byte is that example illustrates with the data that desire will be read.If the data that desire will be read are included in two, three or four bytes in the ECC code word, then write state machine 120 comprises the address information of these two, three or four bytes respectively to four gating signals of selecting a MUX to send.
If the data that desire will be read are included in a plurality of ECC code words, then when read operation, read an ECC code word at every turn, from this ECC code word, read the data of each byte then successively.By reading this a plurality of ECC code words, obtain this at last and be included in the data that the desire in a plurality of ECC code words will be read.
(2) data writing operation embodiment
In the present embodiment, selected cell 180 is an alternative MUX, the outer input data from the outside input that writes is 9 bytes 72bits altogether, desire will begin to write from second byte of ECC data set of storage array 110 a N ECC code word, ends at second byte of ECC data set of N+2 ECC code word.Certainly, Shu Ru outer input data once can not surpass the capacity of data buffer 142.The byte of band shade shown in Figure 5 is a byte to be written, and the ECC data set of every byte data position correspondence is fixed.
Fig. 6 is the schematic flow sheet of data writing operation embodiment, and in conjunction with nonvolatile memory embodiment shown in Figure 1 and Data Position signal shown in Figure 5, this data writing operation mainly comprises the steps:
Step S610, according to the write operation instruction, write state machine 120 obtains first address and the record of outer input data in nonvolatile memory;
In the present embodiment, the first address of this outer input data is the address of second byte of ECC data set of N ECC code word in the storage array 110;
Step S620, according to this first address, write state machine 120 is that follow-up outer input data is distributed in memory address and the record in the nonvolatile memory;
In the present embodiment, the memory address of this distribution is the address of continuous 9 bytes of beginning from this first address;
Step S630, write state machine 120 obtains last address and the record of outer input data in nonvolatile memory when receiving the information that stops to write of external control input; When also being outer input data memory allocated address, this memory address is assigned to till the last address that is obtained always;
Step S640 according to separately address, is cached to the outer input data of these 9 bytes in the input latch 170;
Step S650, write state machine 120 is according to the first address (i.e. the address of first byte in these 9 bytes) of outer input data, from storage array 110, read the ECC data set of N ECC code word, be cached in output latch 150, and indication selected cell 180 reads first byte in the ECC data set of this N ECC code word from output latch 150;
Step S652, write state machine 120 indication selected cells 180 read outer input data first three byte by address arrangement from input latch 170;
Step S654, selected cell 180 is according to the indication of write state machine 120, from output latch 150, read first byte in the ECC data set of this N ECC code word, from input latch 170, read outer input data first three byte by address arrangement;
Step S656, four bytes that selected cell 180 will read, promptly first byte in the ECC data set of this N ECC code word and this outer input data are by first three byte of address arrangement, form an ECC data set, ECC data set for N new ECC code word, and ECC data set that will this N new ECC code word, in a clock period, send to buffer memory in the data buffer 142; Wherein the byte that reads from output latch 150 is first byte of the ECC data set of this N new ECC code word, and three bytes that read from input latch 170 are second, third and the 4th byte of the ECC data set of this N new ECC code word;
Step S658, write state machine 120 indication selected cells 180 read four to seven byte of outer input data by address arrangement from input latch 170;
Step S660, selected cell 180 is according to 120 indications of write state machine, from input latch 170, read the 4th to the 7th byte in the outer input data, and these four bytes are formed the ECC data set of N+1 new ECC code word in order, in a clock period, send to buffer memory in the data buffer 142;
Step S662, write state machine 120 is according to the last address (i.e. the address of the 9th byte in these 9 bytes) of outer input data, from storage array 110, read the ECC data set of N+2 ECC code word, be cached in output latch 150, and indication selected cell 180 reads the 3rd and the 4th byte in the ECC data set of this N+2 ECC code word from output latch 150;
Step S664, write state machine 120 indication selected cells 180 read eight and nine byte of outer input data by address arrangement from input latch 170;
Step S670, selected cell 180 is according to the indication of write state machine 120, from input latch 170, read eight and nine byte of this outer input data, from output latch 150, read the 3rd and the 4th byte in the ECC data set of this N+2 ECC code word by address arrangement;
Step S675, four bytes that selected cell 180 will read, promptly this outer input data is by the 3rd and the 4th byte in the ECC data set of the 8th and the 9th byte of address arrangement and this N+2 ECC code word, the ECC data set of forming N+2 new ECC code word sends to buffer memory in the data buffer 142 in a clock period; Wherein this outer input data is by the 8th and the 9th byte of address arrangement, first and second byte for the ECC data set of this N+2 new ECC code word, the the 3rd and the 4th byte in the ECC data set of this N+2 ECC code word is the 3rd and the 4th byte of the ECC data set of this N+2 new ECC code word;
The operating process of reading of data from storage array 110 in the above-mentioned flow process please refer to read data operation embodiment shown in Figure 4, repeats no more herein.Be that the data in the output latch 150 are sent to selected cell 180 by byte during write-back, send to impact damper 142 after forming new ECC data set by selected cell 180.
In the present embodiment, because the first address of outer input data, be the position of second byte of ECC data set in N the ECC code word,, first byte of ECC data set in this N ECC code word need be read out and carry out write-back for the accuracy that guarantees to write; Because the last address of outer input data is second byte of ECC data set in N+2 the ECC code word, the 3rd, the 4th byte of ECC data set in this N+2 ECC code word need be read out and carries out write-back;
Three new ECC data sets that step S680, ECC circuit 130 are respectively storage in the data buffer 142 generate corresponding check bit separately, then the check bit that is generated are sent to check bit impact damper 144 buffer memorys;
Step S690 with these three new ECC data sets and corresponding check bit separately, sends to storage array 110 to next code word (an ECC data set and corresponding check bit), stores according to corresponding address.
Owing to be that second byte of ECC data set from storage array 110 a N ECC code word begins to write, and end at second byte of ECC data set of N+2 ECC code word, therefore need first byte of ECC data set, and data buffer 142 is read and be written back to the ECC data set the 3rd of this N+2 ECC code word, the 4th byte with this N ECC code word.
Among this data writing operation embodiment, in the ECC data set of N the ECC code word that this is new, first byte is for reading the also byte of write-back from storage array 110, and back three bytes are tactic first, second and third byte in the outer input data; The ECC data set of N+1 the ECC code word that this is new, the 4th to the 7th byte of series arrangement outer input data; First and second byte of ECC data set of N+2 the ECC code word that this is new is respectively the 8th and the 9th byte of outer input data, and latter two byte is for reading from storage array 110 and the byte of write-back.
To each byte of whole page data to be written, all need to adopt zone bit to indicate the address in the prior art.In the present invention, adopt the first address to determine the method for back, do not need all to indicate zone bit for each byte according to this address, first place continuous data.Compared to existing technologies, need twice sign address information (first address and last address) to get final product among the present invention at most.
Need to prove, among the above-mentioned data writing operation embodiment, be to distribute to add 1 mode continuously during for outer input data memory allocated address, and in fact can also adopt modes such as record is outer input data memory allocated address.In addition, above-mentioned data writing operation embodiment describes in the mode that writes (promptly the memory address of outer input data is continuous in storage array) continuously, outer input data for discontinuous writing (promptly the memory address of outer input data is discontinuous in storage array), it can be regarded as the data segment that plurality of continuous writes, write thereby adopt the step of above-mentioned write operation embodiment to finish.
By write operation embodiment shown in Figure 6 as can be known, in the write operation process, write state machine 120 need judge whether need be from storage array 110 sense data to carry out write-back, then from storage array 110, read corresponding ECC code word if desired and deposit in latch 150 is shown, and the indication selected cell therefrom reads corresponding byte.
When receiving outer input data, obtain the first address and the record of outer input data, and be that outer input data distributes the address according to first address.When receiving the information that stops to write of external control input, obtain the last address and the record of outer input data.
Locate the ECC data set at this first address data place according to this first address addressing, locate the ECC data set at this address date place, end according to this end addressing of address; Whether the ECC data set of judging this first address data place then respectively has partial bytes not need to be replaced, and whether ECC data set that should address date place, end has partial bytes not need to be replaced.
If the ECC data set at this first address data place and/or ECC data set that should address date place, end, there is partial bytes not need to be replaced, then by row address decoder 125, column address decoder and sense amplifier 126 and ECC circuit 130 etc., the ECC data set is cached to output latch 150, and indication selected cell 180 reads therefrom and does not need the byte that is replaced.Selected cell 180 reads write-back from output latch 150 under the effect of selecting signal, read outer input data from input latch 170, forms to send to data buffer 142 behind the new ECC data set and store.If whole bytes of whole ECC data set all need to be replaced, then need not sense data from storage array 110.
After data buffer 142 has been stored whole needs and is written to data (comprising outer input data, if there is write-back also to comprise write-back) in the storage array 110, send check bit to ECC circuit 130 and produce signals.ECC circuit 130 produces signal according to this check bit, for each ECC data set of storing in the data buffer 142 generates check bit respectively and sends to storage in the check bit impact damper 144, then each ECC data set and corresponding check bit are sent to storage array 110 through column address decoder and sense amplifier 126.When mailing to storage array 110, ECC data set and corresponding check bit can be sent to storage in the storage array 110, ECC code word of write-once.
In data writing operation embodiment shown in Figure 6, storage is ECC data set in new N, N+1 and N+2 the ECC code word in the data buffer 142, accordingly, store the check bit of the ECC data set in this new N, N+1 and N+2 the ECC code word in the check bit impact damper 144 respectively, wherein, each ECC data set is 32, and corresponding check bit is 6.
Above-mentioned this write operation embodiment has realized second byte of N ECC code word ECC data set in the storage array begun, and to totally 9 bytes that second byte of N+2 ECC code word ECC data set finishes, replaces with the outer input data of new input.
In conjunction with shown in Figure 2, in the process of carrying out write data, an alternative MUX once only sends the data of 1 byte to data buffer 142, no matter be the outer input data of importing from the outside, the still write-back of reading from storage array and the combination of outer input data.In the present embodiment, a selected cell 180 contains four alternative MUX, therefore sends four bytes a clock period to data buffer 142.In above-mentioned write operation embodiment, because an ECC data set comprises 4 bytes, therefore for an ECC data set, selected cell 180 comprises the write-back of three bytes at most in the ECC code word that data buffer 142 sends.
Need to prove, the various embodiments described above of the present invention, with an ECC code word comprise 4 bytes, a byte is that 8bits is that example describes, do not constitute restriction to ECC code word or byte, ECC code word specifically comprises how many bytes or how many bits are a byte comprise, and the present invention does not limit.
Technical scheme of the present invention is a unit with the ECC code word much smaller than page or leaf, finishes data write.Technical solution of the present invention is applicable to that external interface is the nonvolatile memory that unit carries out data transmission, especially EEPROM with the byte.Adopt the data bit of some bytes and corresponding check bit to form an ECC code word, and be that unit reads and writes, reduced the area overhead of ECC circuit with the ECC code word.Storer can be by address reading of data or write data continuously, only need the corresponding instruction of input read-write and the start address of operation to get final product, memory inside can automatically perform continuous operation and needn't re-enter instruction and address, because subsequent address produces automatically, so interface can be very simple.When storer was imported the data of a byte at random, memory inside only needed the ECC code word with this byte correspondence to write again to get final product, and was that unit reads or writes data and compares with the page or leaf with prior art, had effectively prolonged the serviceable life of storer.And, in data writing process, at most only need the ECC code words that from storage array, read several byte lengths twice, compared with prior art, also reduced data and write fashionable time and power consumption.
Though the disclosed embodiment of the present invention as above, the embodiment that described content just adopts for the ease of understanding the present invention is not in order to limit the present invention.Technician in any the technical field of the invention; under the prerequisite that does not break away from the disclosed spirit and scope of the present invention; can do any modification and variation what implement in form and on the details; but scope of patent protection of the present invention still must be as the criterion with the scope that appending claims was defined.
Claims (15)
1. one kind writes the method for data continuously to the nonvolatile memory with error detection/correction circuit, it is characterized in that this method comprises:
Obtain the first address and the last address of outer input data;
According to described first address and the described outer input data of last address caching;
If the error detection/correction data set at described outer input data place has partial bytes not need to be replaced, then obtaining this byte that does not need to be replaced from the storage array of described nonvolatile memory is write-back;
With described outer input data, perhaps described outer input data and described write-back are formed new error detection/correction data set and buffer memory, described new error detection/correction data set of a clock period buffer memory;
For described new error detection/correction data set generates corresponding check bit;
Described new error detection/correction data set and corresponding check bit are written to described storage array.
2. the method for claim 1, it is characterized in that, from described storage array, obtain the step of described write-back, comprise that with the error detection/correction code word be unit, from described storage array, read the error detection/correction code word at the data place of described first address and/or last address, therefrom obtain described write-back; Described error detection/correction code word comprises some error detection/correction data sets, and with the corresponding check bit of described some error detection/correction data sets; One of them error detection/correction data set includes some bytes.
3. the method for claim 1 is characterized in that, described outer input data is unit with the byte, and to described outer input data, perhaps described outer input data and described write-back are formed described new error detection/correction data set by latching.
4. the method for claim 1, it is characterized in that, after obtaining the first address of described outer input data in described nonvolatile memory, be described outer input data continuous dispensing memory address, be assigned to till the described last address always according to described first address.
5. the method from nonvolatile memory reading of data with error detection/correction circuit is characterized in that, is unit with the error detection/correction code word, reading of data from the storage array of described nonvolatile memory; Described error detection/correction code word, comprise some error detection/correction data sets and with the corresponding check bit of described some error detection/correction data sets, an error detection/correction data set includes at least two bytes.
6. the method for claim 1 is characterized in that, obtains the address of the data place error detection/correction code word that will read, and is unit reading of data from described storage array with described error detection/correction code word then.
7. the method for claim 1 is characterized in that, the external interface of described nonvolatile memory is that unit exports with the byte.
8. the nonvolatile memory with error detection/correction circuit comprises storage array, error detection/correction circuit and impact damper, it is characterized in that, also comprises:
Input latch is used to receive outer input data;
Output latch links to each other with described error detection/correction circuit, is used to latch the error detection/correction data set after the described error detection/correction circuit of process is carried out error detection/correction, and wherein the error detection/correction data set comprises at least two bytes;
Selected cell links to each other with described impact damper, input latch and output latch, in the data writing operation process, from described input latch, in perhaps described input latch and the output latch, obtain data and form the error detection/correction data set, send to described impact damper.
9. nonvolatile memory as claimed in claim 8 is characterized in that, described selected cell from described input latch, is that unit obtains data with the error detection/correction data set in perhaps described input latch and the output latch.
10. nonvolatile memory as claimed in claim 8 is characterized in that, this nonvolatile memory further comprises storage array and write state machine, and the said write state machine is used to receive read operation instruction or write operation instruction;
According to described read operation instruction, be unit with the error detection/correction code word, reading of data from described storage array; Described error detection/correction code word, comprise some error detection/correction data sets and with the corresponding check bit of described some error detection/correction data sets, an error detection/correction data set includes at least two bytes;
According to described write operation instruction, obtain the first address and the last address of outer input data, and according to described first address and the described outer input data of last address caching; Whether the error detection/correction data set of judging described outer input data place has partial bytes not need to be replaced, be that then to obtain this byte that does not need to be replaced from described storage array be write-back, with described outer input data, perhaps described outer input data and described write-back, form new error detection/correction data set and be cached to described impact damper, described new error detection/correction data set of a clock period buffer memory.
11. nonvolatile memory as claimed in claim 10, it is characterized in that, after the said write state machine obtains the first address of described outer input data in described nonvolatile memory, according to described first address is described outer input data continuous dispensing memory address, till being assigned to the last address of described outer input data in described storage array.
12. nonvolatile memory as claimed in claim 10, it is characterized in that described selected cell is under the selection signal effect that the said write state machine sends, with described outer input data, perhaps described outer input data and described write-back are formed new error detection/correction data set.
13. nonvolatile memory as claimed in claim 10, it is characterized in that, the said write state machine is by the Different Logic value of a control signal, indicating described error detection/correction circuit that the data that read from described storage array are carried out error detection/correction, perhaps is that described new error detection/correction data set produces check bit.
14. nonvolatile memory as claimed in claim 8 is characterized in that, described selected cell is made of some alternative MUX.
15., it is characterized in that this nonvolatile memory also comprises as the described nonvolatile memory of each claim in the claim 8 to 14:
Output unit links to each other with described output latch, and being used for the byte is that unit exports described output latch latched data, comprises MUX.
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