CN105895162B - Read-only memory and its method for reading data - Google Patents
Read-only memory and its method for reading data Download PDFInfo
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- CN105895162B CN105895162B CN201610191833.XA CN201610191833A CN105895162B CN 105895162 B CN105895162 B CN 105895162B CN 201610191833 A CN201610191833 A CN 201610191833A CN 105895162 B CN105895162 B CN 105895162B
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- check bit
- read
- memory
- output module
- data
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/18—Auxiliary circuits, e.g. for writing into memory
Abstract
The invention discloses a kind of read-only memory, comprising: storage array, multidigit output module and central control logic circuit；Every output module is one in check bit output module and non-check bit output module；Central control logic circuit is provided with check bit module control signal, and check bit module control signal is input in each check bit output module and its value is according to whether output verification position is configured；Read-only memory is in operating mode, each non-check bit output module is all in operating mode, when read-only memory needs output verification position data, check bit control signal makes each check bit output module all in operating mode, when read-only memory does not need output verification position data, check bit control signal makes each check bit output module all in standby mode.The invention also discloses a kind of method for reading data of read-only memory.The present invention can reduce power consumption.
Description
Technical field
The present invention relates to semiconductor integrated circuit fields, more particularly to a kind of read-only memory (Read-
OnlyMemorym, ROM).The invention further relates to a kind of method for reading data of read-only memory.
Background technique
Read-only memory is a kind of memory that can only read data.In wafer manufacturing process, usually client is provided
Data manufactured in ROM circuit with one layer of special light shield (Mask), data just cannot change again once write-in.
Smart card (Smart Card): it is embedded with the common name of the plastic clip of microchip.Integrated circuit in card includes center
Processor (CPU), programmable read only memory (EEPROM0, card random access memory (RAM) and be solidificated in read-only memory
Internal operating system COS (Chip Operating System).
The data that read-only memory is stored in smart card are generally divided into check bit data and non-check bit data.
As shown in Figure 1, being the structural schematic diagram of existing read-only memory；Storage array, multidigit output module 101 and center
Control logic circuit 102.Storage array is formed by the arrangement of multiple storage units 103.The output module 101 in Fig. 1 is distinguished
It is indicated with output [0], [1], [N], [N+1], [N+2] and [M] etc., M indicates highest order, and N indicates 0 any one position into M-2.
A multiple selector 104 and a sense amplifier 105 have been respectively included in everybody output module 101；The multichannel
Data of the selector 104 for selecting the storage unit 103 of specified address to be stored in the storage array, it is described sensitive to put
Big device 105 is for amplifying data selected signal.For existing read-only memory in operating mode, each clock cycle is every
A output module 101 can all export the data of specified address according to the instruction of central control logic circuit 102.Due to existing read-only
Memory when reading data every time each output module 101 will work, i.e., each output module 101 can generate function
Consumption.In the application for being similar to smart card, the power consumption of ROM is the smaller the better, therefore it is necessary to reduces the power consumption of ROM.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of read-only memory, can reduce power consumption.For this purpose, the present invention is also
A kind of method for reading data of read-only memory is provided.
In order to solve the above technical problems, read-only memory provided by the invention includes: storage array, multidigit output module and
Central control logic circuit.
Each described output module is for exporting a data；Everybody output module be check bit output module and
One in non-check bit output module.
The central control logic circuit is provided with check bit module control signal, the check bit module control signal
For value according to whether output verification position is configured, the check bit control signal is input to each check bit output module
In.
Read-only memory in operating mode each non-check bit output module all in operating mode and each described non-
Check bit output module can export specified address according to the instruction of the central control logic circuit in each clock cycle
Non- check bit data.
The read-only memory is in operating mode: described when the read-only memory needs output verification position data
Check bit control signal makes each check bit output module all in operating mode and each check bit output module is every
A clock cycle can all export the check bit data of specified address according to the instruction of the central control logic circuit；When described
Memory is read when not needing output verification position data, the check bit control signal make each check bit output module all in
Standby mode.
It is formed a further improvement is that the storage array is arranged by multiple storage units, each described storage unit
Store a data.
A further improvement is that a multiple selector has been respectively included in everybody output module, the multichannel choosing
Select data of the device for selecting the storage unit of specified address to be stored in the storage array.
It is described sensitive to put a further improvement is that respectively included a sense amplifier in everybody output module
Big device is for amplifying selected data-signal.
It is described sensitive to put a further improvement is that respectively included a sense amplifier in everybody output module
Big device is for amplifying selected data-signal.
A further improvement is that the read-only memory is the read-only memory in intelligent card chip.
A further improvement is that in each check bit output module include a NAND gate and a NOT gate, it is described with
Two input terminals of NOT gate are separately connected the check bit control signal and read-only memory internal clock cycles pulse signal, institute
The output end for stating NAND gate connects the input terminal of the NOT gate, and the clock period pulse signal of the output end output of the NOT gate is made
For the internal clock cycles pulse signal of each check bit output module.
When the read-only memory needs output verification position data, the check bit control signal is 1, each verification
The internal clock cycles pulse signal of position output module is the read-only memory internal clock cycles pulse signal.
When the read-only memory does not need output verification position data, the check bit control signal is 0, each school
Test the internal clock cycles pulse signal low level of an output module.
A further improvement is that the internal clock cycles pulse signal of each non-check bit output module is described read-only
Memory inside clock period pulse signal.
In order to solve the above technical problems, read-only memory packet in the method for reading data of read-only memory provided by the invention
It includes: storage array, multidigit output module and central control logic circuit.
Each described output module is for exporting a data；Everybody output module be check bit output module and
One in non-check bit output module.
The central control logic circuit is provided with check bit module control signal, the check bit module control signal
For value according to whether output verification position is configured, the check bit control signal is input to each check bit output module
In.
Read-only memory carries out following reading data in operating mode:
Each non-check bit output module is all switched to operating mode, and each non-check bit output module is when each
The clock period exports the non-check bit data of specified address according to the instruction of the central control logic circuit；
When the read-only memory needs output verification position data, the check bit control signal makes each check bit
Output module is all switched to operating mode and each check bit output module can be according to the center in each clock cycle
The instruction of control logic circuit exports the check bit data of specified address；When the read-only memory does not need output verification digit
According to when, the check bit control signal makes each check bit output module all in standby mode.
The present invention is by classifying output module according to check bit output module and non-check bit output module, simultaneously
Check bit module control signal is set in central control logic circuit, the value of check bit module control signal is according to whether defeated
Check bit is configured out, can make check bit output module all when read-only memory does not need output verification position in operating mode
In standby mode, middle read-only memory all output modules in operating mode require to work compared with the existing technology
And output phase ratio, the present invention is due to making check bit output module only when needing output verification position just to work, do not need check bit
With regard to standby, standby mode can substantially reduce the power consumption of output module compared to operating mode, can finally reduce entire read-only storage
The power consumption of device.
Detailed description of the invention
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
Fig. 1 is the structural schematic diagram of existing read-only memory；
Fig. 2 is the structural schematic diagram of read-only memory of the embodiment of the present invention；
Fig. 3 is the circuit of the check bit control signal control portion of check bit output module in present pre-ferred embodiments
Figure.
Specific embodiment
As shown in Fig. 2, being the structural schematic diagram of read-only memory of the embodiment of the present invention；Read-only memory of the embodiment of the present invention
Read-only memory is the read-only memory in intelligent card chip, and read-only memory of the embodiment of the present invention includes: storage array, multidigit
Output module 1 and central control logic circuit 2.
Storage array is arranged by multiple storage units 3, is stored with a data in each storage unit 3.
Each described output module 1 is for exporting a data；Everybody output module 1 is check bit output module
1 and non-check bit output module 1 in one.The output module 1 in Fig. 2 respectively with output [0], [1], [N], [N+1],
[N+2] and [M] etc. indicate that M indicates highest order, and N indicates 0 any one position into M-2.In everybody output module 1 respectively
It include a multiple selector 4 and a sense amplifier 5, the multiple selector 4 in the storage array for selecting
Select the data that the storage unit 3 of specified address is stored；The sense amplifier 5 is for putting selected data-signal
Greatly.
The central control logic circuit 2 is provided with check bit module control signal, the check bit module control signal
Value according to whether output verification position is configured, the check bit control signal is input to each check bit output mould
In block 1.
Read-only memory in operating mode each non-check bit output module 1 all in operating mode and each described non-
Check bit output module 1 can export specified address in each clock cycle according to the instruction of the central control logic circuit 2
Non- check bit data.
The read-only memory is in operating mode: described when the read-only memory needs output verification position data
Check bit control signal makes each check bit output module 1 all in operating mode and each check bit output module 1 exists
Each clock cycle can export the check bit data of specified address according to the instruction of the central control logic circuit 2；Work as institute
When stating read-only memory and not needing output verification position data, the check bit control signal makes each check bit output module 1
All in standby mode.
As shown in figure 3, being the check bit control signal control portion of check bit output module in present pre-ferred embodiments
Circuit diagram, preferably, in each check bit output module 1 include a NAND gate 6 and a NOT gate 7, the NAND gate 6
Two input terminals be separately connected the check bit control signal and read-only memory internal clock cycles pulse signal, it is described with
The output end of NOT gate 6 connects the input terminal of the NOT gate 7, and the clock period pulse signal of the output end output of the NOT gate 7 is made
For the internal clock cycles pulse signal of each check bit output module 1.
It can be seen that the check bit control signal is 1 when the read-only memory needs output verification position data,
The internal clock cycles pulse signal of each check bit output module 1 is read-only memory internal clock cycles pulse letter
Number；
When the read-only memory does not need output verification position data, the check bit control signal is 0, each school
Test the internal clock cycles pulse signal low level of an output module 1.
In the embodiment of the present invention, the internal clock cycles pulse signal of each non-check bit output module 1 is described
Read memory inside clock period pulse signal.
The read-only memory of the method for reading data of read-only memory of the embodiment of the present invention is read-only in intelligent card chip
Memory, comprising:
Storage array is arranged by multiple storage units 3, is stored with a data in each storage unit 3.
Each described output module 1 is for exporting a data；Everybody output module 1 is check bit output module
1 and non-check bit output module 1 in one.The output module 1 in Fig. 2 respectively with output [0], [1], [N], [N+1],
[N+2] and [M] etc. indicate that M indicates highest order, and N indicates 0 any one position into M-2.In everybody output module 1 respectively
It include a multiple selector 4 and a sense amplifier 5, the multiple selector 4 in the storage array for selecting
Select the data that the storage unit 3 of specified address is stored；The sense amplifier 5 is for putting selected data-signal
Greatly.
The central control logic circuit 2 is provided with check bit module control signal, the check bit module control signal
Value according to whether output verification position is configured, the check bit control signal is input to each check bit output mould
In block 1.
Read-only memory carries out following reading data in operating mode:
Each non-check bit output module 1 is all switched to operating mode, and each non-check bit output module 1 is each
Clock cycle exports the non-check bit data of specified address according to the instruction of the central control logic circuit 2.
When the read-only memory needs output verification position data, the check bit control signal makes each check bit
Output module 1 is all switched to operating mode and each check bit output module 1 can be according in described in each clock cycle
The instruction of control logic circuit 2 is entreated to export the check bit data of specified address；When the read-only memory does not need output verification
When the data of position, the check bit control signal makes each check bit output module 1 all in standby mode.
Preferably, as shown in figure 3, including a NAND gate 6 and a NOT gate 7, institute in each check bit output module 1
Two input terminals for stating NAND gate 6 are separately connected the check bit control signal and read-only memory internal clock cycles pulse letter
Number, the output end of the NAND gate 6 connects the input terminal of the NOT gate 7, the clock cycle arteries and veins of the output end output of the NOT gate 7
Rush internal clock cycles pulse signal of the signal as each check bit output module 1；It can be seen that
When the read-only memory needs output verification position data, the check bit control signal is 1, each verification
The internal clock cycles pulse signal of position output module 1 is the read-only memory internal clock cycles pulse signal；
When the read-only memory does not need output verification position data, the check bit control signal is 0, each school
Test the internal clock cycles pulse signal low level of an output module 1.
The internal clock cycles pulse signal of each non-check bit output module 1 is the read-only memory internal clocking
Periodic pulse signal.
By taking one read-only memory being specifically applied in intelligent card chip of the embodiment of the present invention as an example, the read-only memory
38 output modules are used, wherein the storage of 6 output modules is check bit data.Check bit module of the embodiment of the present invention
Control signal controls this 6 output modules, when not needing check bit output, so that this 6 modules is entered standby mode, is used to
Save power consumption.From the point of view of the test result of test chip, (FF Corner, -40 are taken the photograph under the conditions of dynamic power consumption worst silicon wafer
Family name's degree), as supply voltage 1.65V:
Each 38 output modules of duty cycle can all work at the same time in existing structure shown in FIG. 1, power consumption are as follows: 48 μ
A/MHz。
And after using structure of the embodiment of the present invention, when 6 check bit output modules can be under the standby mode, power consumption
Are as follows: 42uA/MHz.As can be seen that work of the embodiment of the present invention can save 12.5% power consumption in this mode.
The present invention has been described in detail through specific embodiments, but these are not constituted to limit of the invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered
It is considered as protection scope of the present invention.
Claims (16)
1. a kind of read-only memory characterized by comprising storage array, multidigit output module and central control logic circuit；
Each described output module is for exporting a data；Everybody output module is check bit output module and non-school
Test one in an output module；
The central control logic circuit is provided with check bit module control signal, the value root of the check bit module control signal
Whether according to needing output verification position to be configured, the check bit control signal is input in each check bit output module；
Read-only memory in operating mode each non-check bit output module all in operating mode and each non-verification
Position output module can export the non-school of specified address in each clock cycle according to the instruction of the central control logic circuit
Test a data；
The read-only memory is in operating mode: when the read-only memory needs output verification position data, the verification
Position control signal makes each check bit output module all in operating mode and each check bit output module is when each
The clock period can all export the check bit data of specified address according to the instruction of the central control logic circuit；It read-only is deposited when described
When reservoir does not need output verification position data, the check bit control signal makes each check bit output module all in standby
Mode.
2. read-only memory as described in claim 1, it is characterised in that: the storage array arranges shape by multiple storage units
At each described storage unit stores a data.
3. read-only memory as claimed in claim 1 or 2, it is characterised in that: respectively included one in everybody output module
A multiple selector, the multiple selector in the storage array for selecting the storage unit of specified address to be stored
Data.
4. read-only memory as claimed in claim 1 or 2, it is characterised in that: respectively included one in everybody output module
A sense amplifier, the sense amplifier is for amplifying selected data-signal.
5. read-only memory as claimed in claim 3, it is characterised in that: respectively included a spirit in everybody output module
Quick amplifier, the sense amplifier is for amplifying selected data-signal.
6. read-only memory as described in claim 1, it is characterised in that: the read-only memory is read-only in intelligent card chip
Memory.
7. read-only memory as described in claim 1, it is characterised in that: in each check bit output module include one with it is non-
Door and a NOT gate, two input terminals of the NAND gate are separately connected inside the check bit control signal and read-only memory
Clock period pulse signal, the output end of the NAND gate connect the input terminal of the NOT gate, the output end output of the NOT gate
Internal clock cycles pulse signal of the clock period pulse signal as each check bit output module；
When the read-only memory needs output verification position data, the check bit control signal is 1, and each check bit is defeated
The internal clock cycles pulse signal of module is the read-only memory internal clock cycles pulse signal out；
When the read-only memory does not need output verification position data, the check bit control signal is 0, each check bit
The internal clock cycles pulse signal low level of output module.
8. read-only memory as described in claim 1, it is characterised in that: the internal clocking week of each non-check bit output module
Phase pulse signal is the read-only memory internal clock cycles pulse signal.
9. a kind of method for reading data of read-only memory, which is characterized in that read-only memory includes: storage array, and multidigit is defeated
Module and central control logic circuit out；
Each described output module is for exporting a data；Everybody output module is check bit output module and non-school
Test one in an output module；
The central control logic circuit is provided with check bit module control signal, the value root of the check bit module control signal
Whether according to needing output verification position to be configured, the check bit control signal is input in each check bit output module；
Read-only memory carries out following reading data in operating mode:
Each non-check bit output module is all switched to operating mode, and each non-check bit output module is in each clock week
Phase exports the non-check bit data of specified address according to the instruction of the central control logic circuit；
When the read-only memory needs output verification position data, the check bit control signal makes each check bit output
Module is all switched to operating mode and each check bit output module can be controlled in each clock cycle according to the center
The instruction of logic circuit exports the check bit data of specified address；When the read-only memory does not need output verification position data
When, the check bit control signal makes each check bit output module all in standby mode.
10. the method for reading data of read-only memory as claimed in claim 9, it is characterised in that: the storage array is by multiple
Storage unit arranges to be formed, each described storage unit stores a data.
11. the method for reading data of read-only memory as described in claim 9 or 10, it is characterised in that: everybody output mould
A multiple selector is respectively included in block, the multiple selector in the storage array for selecting specified address
The data that storage unit is stored.
12. the method for reading data of read-only memory as described in claim 9 or 10, it is characterised in that: everybody output mould
A sense amplifier is respectively included in block, the sense amplifier is for amplifying selected data-signal.
13. the method for reading data of read-only memory as claimed in claim 11, it is characterised in that: in everybody output module
A sense amplifier is respectively included, the sense amplifier is for amplifying selected data-signal.
14. the method for reading data of read-only memory as claimed in claim 9, it is characterised in that: the read-only memory is intelligence
Read-only memory in energy card chip.
15. the method for reading data of read-only memory as claimed in claim 9, it is characterised in that: each check bit exports mould
It include a NAND gate and a NOT gate in block, two input terminals of the NAND gate are separately connected the check bit control signal
With read-only memory internal clock cycles pulse signal, the output end of the NAND gate connects the input terminal of the NOT gate, described
Internal clock cycles pulse of the clock period pulse signal of the output end output of NOT gate as each check bit output module
Signal；
When the read-only memory needs output verification position data, the check bit control signal is 1, and each check bit is defeated
The internal clock cycles pulse signal of module is the read-only memory internal clock cycles pulse signal out；
When the read-only memory does not need output verification position data, the check bit control signal is 0, each check bit
The internal clock cycles pulse signal low level of output module.
16. the method for reading data of read-only memory as claimed in claim 9, it is characterised in that: each non-check bit output
The internal clock cycles pulse signal of module is the read-only memory internal clock cycles pulse signal.
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| CN201610191833.XA CN105895162B (en) | 2016-03-30 | 2016-03-30 | Read-only memory and its method for reading data |
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|---|---|---|---|---|
| CN1083962A (en) * | 1992-07-30 | 1994-03-16 | 三星电子株式会社 | The semiconductor memory that comprises multiple-error check and correcting circuit |
| CN1909114A (en) * | 2005-08-01 | 2007-02-07 | 株式会社日立制作所 | Semiconductor memory device |
| CN101930799A (en) * | 2009-06-23 | 2010-12-29 | 北京芯技佳易微电子科技有限公司 | Non-volatile memory with error checking/correcting circuit and methods thereof for reading and writing data |
| CN103426482A (en) * | 2012-05-14 | 2013-12-04 | 株式会社东芝 | Memory controller, storage device and error correction method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9136012B1 (en) * | 2014-05-05 | 2015-09-15 | Apple Inc. | Reliable readout of fuse data in an integrated circuit |
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2016
- 2016-03-30 CN CN201610191833.XA patent/CN105895162B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1083962A (en) * | 1992-07-30 | 1994-03-16 | 三星电子株式会社 | The semiconductor memory that comprises multiple-error check and correcting circuit |
| CN1909114A (en) * | 2005-08-01 | 2007-02-07 | 株式会社日立制作所 | Semiconductor memory device |
| CN101930799A (en) * | 2009-06-23 | 2010-12-29 | 北京芯技佳易微电子科技有限公司 | Non-volatile memory with error checking/correcting circuit and methods thereof for reading and writing data |
| CN103426482A (en) * | 2012-05-14 | 2013-12-04 | 株式会社东芝 | Memory controller, storage device and error correction method |
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