CN105895162A - Read-only memory and data reading method thereof - Google Patents
Read-only memory and data reading method thereof Download PDFInfo
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- CN105895162A CN105895162A CN201610191833.XA CN201610191833A CN105895162A CN 105895162 A CN105895162 A CN 105895162A CN 201610191833 A CN201610191833 A CN 201610191833A CN 105895162 A CN105895162 A CN 105895162A
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- check bit
- memory
- read
- output module
- data
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/18—Auxiliary circuits, e.g. for writing into memory
Abstract
The invention discloses a read-only memory which comprises a storage array, multiple bit output modules and a central control logic circuit. Each bit output module is a check bit output module or a non-check bit output module. The central control logic circuit is provided with check bit module control signals. The check bit module control signals are input to the check bit output modules, and values of the check bit module control signals are set according to the judgment whether check bits need to be output or not; when the read-only memory is in the working mode, the non-check bit output modules are in the working mode; when the read-only memory needs to output check bit data, the check bit control signals enable the check bit output modules to be in the working mode; when the read-only memory does not need to output check bit data, the check bit control signals enable the check bit output modules to be in the standby mode. The invention further discloses a data reading method of the read-only memory. The read-only memory can lower power consumption.
Description
Technical field
The present invention relates to semiconductor integrated circuit field, particularly relate to a kind of read only memory (Read-Only
Memorym, ROM).The invention still further relates to the method for reading data of a kind of read only memory.
Background technology
Read only memory is a kind of memorizer that can only read data.In wafer manufacturing process, generally client is provided
Data manufacture in ROM circuit with one layer of special light shield (Mask), data, once write, just can not change again.
Smart card (Smart Card): be embedded with the common name of the plastic clip of microchip.Integrated circuit in card includes
Central processing unit (CPU), programmable read only memory (EEPROM0, random access memory (RAM) and be solidificated in read-only
Card internal operating system COS (Chip Operating System) in memorizer.
The data being stored in read only memory in smart card are generally divided into check bit data and non-check bit data.
As it is shown in figure 1, be the structural representation of existing read only memory；Storage array, multidigit output module 101 He
Central control logic circuit 102.Storage array is arranged by multiple memory element 103 and is formed.Described output in Fig. 1
Module 101 represents with output [0], [1], [N], [N+1], [N+2] and [M] etc. respectively, and M represents highest order,
N represents any one position in 0 to M-2.Everybody described output module 101 includes a MUX respectively
104 and a sense amplifier 105；Described MUX 104 is for selecting appointment ground in described storage array
The data that the memory element 103 of location is stored, described sense amplifier 105 is for putting data selected signal
Greatly.Existing read only memory is when mode of operation, and each output module of each clock cycle 101 can be controlled according to central authorities
The data of address are specified in the instruction output of logic circuit 102 processed.When reading data due to existing read only memory every time every
Individual output module 101 will be operated, and the most each output module 101 can produce power consumption.It is being similar to smart card
Application in, the power consumption of ROM is the smaller the better, the power consumption of the most necessary reduction ROM.
Summary of the invention
The technical problem to be solved is to provide a kind of read only memory, can reduce power consumption.To this end, the present invention
Also provide for the method for reading data of a kind of read only memory.
For solving above-mentioned technical problem, the read only memory that the present invention provides includes: storage array, multidigit output module
With central control logic circuit.
Each described output module is used for exporting a data；Everybody described output module be check bit output module and
In non-check bit output module one.
Described central control logic circuit is provided with check bit module control signal, described check bit module control signal
Value is according to whether output verification position is configured, and described check bit control signal is input to the output of each described check bit
In module.
Read only memory when mode of operation each described non-check bit output module all in mode of operation and each described non-
Check bit output module can export according to the instruction of described central control logic circuit in each clock cycle and specify ground
The non-check bit data of location.
Described read only memory is when mode of operation: when described read only memory needs output verification bit data, described
Check bit control signal makes each described check bit output module all in mode of operation and each described check bit output module
The check bit data of address can be specified according to the instruction output of described central control logic circuit in each clock cycle；
When described read only memory need not output verification bit data, described check bit control signal makes each described check bit defeated
Go out module all in standby mode.
Further improving and be, described storage array is formed by the arrangement of multiple memory element, each described memory element
Storage a data.
Further improving is to include a MUX in everybody described output module respectively, and described multichannel is selected
Select device for the data selecting the memory element specifying address to be stored in described storage array.
Further improve and be, everybody described output module includes a sense amplifier respectively, described sensitive put
Big device is for being amplified selected data signal.
Further improve and be, everybody described output module includes a sense amplifier respectively, described sensitive put
Big device is for being amplified selected data signal.
Further improving is that described read only memory is the read only memory in intelligent card chip.
Further improving and be, each described check bit output module includes a NAND gate and a not gate, described with
Two inputs of not gate connect described check bit control signal and read only memory internal clock cycles pulse letter respectively
Number, the outfan of described NAND gate connects the input of described not gate, the clock cycle of the outfan output of described not gate
Pulse signal is as the internal clock cycles pulse signal of each described check bit output module.
When described read only memory needs output verification bit data, described check bit control signal is 1, each described school
The internal clock cycles pulse signal testing an output module is described read only memory internal clock cycles pulse signal.
When described read only memory need not output verification bit data, described check bit control signal is 0, each described
The internal clock cycles pulse signal low level of check bit output module.
Further improving is that the internal clock cycles pulse signal of each described non-check bit output module is described read-only
Memory inside clock period pulse signal.
For solving above-mentioned technical problem, read only memory bag in the method for reading data of the read only memory that the present invention provides
Include: storage array, multidigit output module and central control logic circuit.
Each described output module is used for exporting a data；Everybody described output module be check bit output module and
In non-check bit output module one.
Described central control logic circuit is provided with check bit module control signal, described check bit module control signal
Value is according to whether output verification position is configured, and described check bit control signal is input to the output of each described check bit
In module.
Read only memory carries out following digital independent when mode of operation:
Each described non-check bit output module all switches to mode of operation, and each described non-check bit output module is when each
The clock cycle specifies the non-check bit data of address according to the instruction output of described central control logic circuit；
When described read only memory needs output verification bit data, described check bit control signal makes each described check bit
Output module all switches to mode of operation and each described check bit output module can be according to described in each clock cycle
The check bit data of address are specified in the instruction output of central control logic circuit；When described read only memory need not output
During check bit data, described check bit control signal makes each described check bit output module all in standby mode.
The present invention is by classifying output module, simultaneously according to check bit output module and non-check bit output module
Arranging check bit module control signal at central control logic circuit, the value of check bit module control signal is according to whether need
Want output verification position to be configured, check bit when read only memory need not output verification position in mode of operation, can be made defeated
Going out module all in standby mode, relative to read only memory in prior art, when mode of operation, all output modules are all
Needs are operated and export and compare, and due to the fact that and make check bit output module only in needs output verification position ability work
Making, need not during check bit the most standby, standby mode can be substantially reduced the power consumption of output module compared to mode of operation,
The last power consumption that can reduce whole read only memory.
Accompanying drawing explanation
The present invention is further detailed explanation with detailed description of the invention below in conjunction with the accompanying drawings:
Fig. 1 is the structural representation of existing read only memory；
Fig. 2 is the structural representation of embodiment of the present invention read only memory；
Fig. 3 is the circuit of the check bit control signal control portion of check bit output module in present pre-ferred embodiments
Figure.
Detailed description of the invention
As in figure 2 it is shown, be the structural representation of embodiment of the present invention read only memory；The read-only storage of the embodiment of the present invention
Device read only memory is the read only memory in intelligent card chip, and embodiment of the present invention read only memory includes: storage battle array
Row, multidigit output module 1 and central control logic circuit 2.
Storage array is formed by the arrangement of multiple memory element 3, and in each memory element 3, storage has a data.
Each described output module 1 is used for exporting a data；Everybody exports mould for check bit by described output module 1
In block 1 and non-check bit output module 1 one.Described output module 1 in Fig. 2 use output [0], [1] respectively,
[N], [N+1], [N+2] and [M] etc. represent, M represents that highest order, N represent any one position in 0 to M-2.
Everybody described output module 1 includes a MUX 4 and a sense amplifier 5, described multichannel respectively
The data that selector 4 is stored for selecting the memory element 3 specifying address in described storage array；Described sensitive
Amplifier 5 is for being amplified selected data signal.
Described central control logic circuit 2 is provided with check bit module control signal, described check bit module control signal
Value according to whether output verification position is configured, it is defeated that described check bit control signal is input to each described check bit
Go out in module 1.
Read only memory when mode of operation each described non-check bit output module 1 all in mode of operation and each described non-
Check bit output module 1 can export according to the instruction of described central control logic circuit 2 in each clock cycle and specify
The non-check bit data of address.
Described read only memory is when mode of operation: when described read only memory needs output verification bit data, described
Check bit control signal makes each described check bit output module 1 all in mode of operation and each described check bit output module
1 can specify the verification figure place of address in each clock cycle according to the instruction output of described central control logic circuit 2
According to；When described read only memory need not output verification bit data, described check bit control signal makes each described verification
Position output module 1 is all in standby mode.
As it is shown on figure 3, be the check bit control signal control portion of check bit output module in present pre-ferred embodiments
Circuit diagram, preferably, each described check bit output module 1 includes a NAND gate 6 and a not gate 7, institute
Two inputs stating NAND gate 6 connect described check bit control signal and read only memory internal clock cycles arteries and veins respectively
Rushing signal, the outfan of described NAND gate 6 connects the input of described not gate 7, the outfan output of described not gate 7
Clock period pulse signal as the internal clock cycles pulse signal of each described check bit output module 1.
It can be seen that when described read only memory needs output verification bit data, described check bit control signal is 1,
The internal clock cycles pulse signal of each described check bit output module 1 is described read only memory internal clock cycles arteries and veins
Rush signal；
When described read only memory need not output verification bit data, described check bit control signal is 0, each described
The internal clock cycles pulse signal low level of check bit output module 1.
In the embodiment of the present invention, the internal clock cycles pulse signal of each described non-check bit output module 1 is described
Read memory inside clock period pulse signal.
The read only memory of the method for reading data of embodiment of the present invention read only memory is read-only in intelligent card chip
Memorizer, including:
Storage array is formed by the arrangement of multiple memory element 3, and in each memory element 3, storage has a data.
Each described output module 1 is used for exporting a data；Everybody exports mould for check bit by described output module 1
In block 1 and non-check bit output module 1 one.Described output module 1 in Fig. 2 use output [0], [1] respectively,
[N], [N+1], [N+2] and [M] etc. represent, M represents that highest order, N represent any one position in 0 to M-2.
Everybody described output module 1 includes a MUX 4 and a sense amplifier 5, described multichannel respectively
The data that selector 4 is stored for selecting the memory element 3 specifying address in described storage array；Described sensitive
Amplifier 5 is for being amplified selected data signal.
Described central control logic circuit 2 is provided with check bit module control signal, described check bit module control signal
Value according to whether output verification position is configured, it is defeated that described check bit control signal is input to each described check bit
Go out in module 1.
Read only memory carries out following digital independent when mode of operation:
Each described non-check bit output module 1 all switches to mode of operation, and each described non-check bit output module 1 is often
The individual clock cycle specifies the non-check bit data of address according to the instruction output of described central control logic circuit 2.
When described read only memory needs output verification bit data, described check bit control signal makes each described check bit
Output module 1 all switches to mode of operation and each described check bit output module 1 can be according to institute in each clock cycle
The check bit data of address are specified in the instruction output stating central control logic circuit 2；When described read only memory need not
During output verification bit data, described check bit control signal makes each described check bit output module 1 all in standby mode.
Preferably, as it is shown on figure 3, each described check bit output module 1 includes a NAND gate 6 and a not gate
7, two inputs of described NAND gate 6 connect described check bit control signal and read only memory internal clocking respectively
Periodic pulse signal, the outfan of described NAND gate 6 connects the input of described not gate 7, the output of described not gate 7
The clock period pulse signal of end output is as the internal clock cycles pulse signal of each described check bit output module 1；
It can be seen that
When described read only memory needs output verification bit data, described check bit control signal is 1, each described school
The internal clock cycles pulse signal testing an output module 1 is described read only memory internal clock cycles pulse signal；
When described read only memory need not output verification bit data, described check bit control signal is 0, each described
The internal clock cycles pulse signal low level of check bit output module 1.
The internal clock cycles pulse signal of each described non-check bit output module 1 is described read only memory internal clocking
Periodic pulse signal.
As a example by one read only memory being specifically applied in intelligent card chip of the embodiment of the present invention, this read only memory
Having used 38 output modules, what wherein 6 output modules were deposited is check bit data.The embodiment of the present invention verifies
Position module control signal controls this 6 output modules, when need not check bit output, making these 6 modules enter and treating
Machine pattern, is used for saving power consumption.From the point of view of the test result of test chip, under the conditions of the silicon chip that dynamic power consumption is worst
(FF Corner ,-40 degrees Celsius), as supply voltage 1.65V:
In existing structure shown in Fig. 1, each 38 output modules of working cycle all can work simultaneously, and its power consumption is:
48μA/MHz。
And after using embodiment of the present invention structure, when 6 check bit output modules can be under standby mode, its power consumption
For: 42uA/MHz.It can be seen that embodiment of the present invention work can save the power consumption of 12.5% in this mode.
Above by specific embodiment, the present invention is described in detail, but these have not constituted the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art it may also be made that many deformation and improves, this
Also should be regarded as protection scope of the present invention a bit.
Claims (16)
1. a read only memory, it is characterised in that including: storage array, multidigit output module and central authorities control
Logic circuit；
Each described output module is used for exporting a data；Everybody described output module be check bit output module and
In non-check bit output module one；
Described central control logic circuit is provided with check bit module control signal, described check bit module control signal
Value is according to whether output verification position is configured, and described check bit control signal is input to the output of each described check bit
In module；
Read only memory when mode of operation each described non-check bit output module all in mode of operation and each described non-
Check bit output module can export according to the instruction of described central control logic circuit in each clock cycle and specify ground
The non-check bit data of location；
Described read only memory is when mode of operation: when described read only memory needs output verification bit data, described
Check bit control signal makes each described check bit output module all in mode of operation and each described check bit output module
The check bit data of address can be specified according to the instruction output of described central control logic circuit in each clock cycle；
When described read only memory need not output verification bit data, described check bit control signal makes each described check bit defeated
Go out module all in standby mode.
2. read only memory as claimed in claim 1, it is characterised in that: described storage array is by multiple memory element
Arrangement is formed, each described memory element storage a data.
3. read only memory as claimed in claim 1 or 2, it is characterised in that: in everybody described output module respectively
Including a MUX, described MUX is for selecting to specify the storage of address in described storage array
The data that unit is stored.
4. read only memory as claimed in claim 1 or 2, it is characterised in that: in everybody described output module respectively
Including a sense amplifier, described sense amplifier is for being amplified selected data signal.
5. read only memory as claimed in claim 3, it is characterised in that: everybody described output module includes respectively
Having a sense amplifier, described sense amplifier is for being amplified selected data signal.
6. read only memory as claimed in claim 1, it is characterised in that: described read only memory is intelligent card chip
In read only memory.
7. read only memory as claimed in claim 1, it is characterised in that: each described check bit output module includes
One NAND gate and a not gate, two inputs of described NAND gate connect described check bit control signal and only respectively
Reading memory inside clock period pulse signal, the outfan of described NAND gate connects the input of described not gate, described
The clock period pulse signal of the outfan output of not gate is as the internal clock cycles of each described check bit output module
Pulse signal；
When described read only memory needs output verification bit data, described check bit control signal is 1, each described school
The internal clock cycles pulse signal testing an output module is described read only memory internal clock cycles pulse signal；
When described read only memory need not output verification bit data, described check bit control signal is 0, each described
The internal clock cycles pulse signal low level of check bit output module.
8. as claimed in claim 1 read only memory, it is characterised in that: each described non-check bit output module interior
Portion's clock period pulse signal is described read only memory internal clock cycles pulse signal.
9. the method for reading data of a read only memory, it is characterised in that read only memory includes: storage array,
Multidigit output module and central control logic circuit；
Each described output module is used for exporting a data；Everybody described output module be check bit output module and
In non-check bit output module one；
Described central control logic circuit is provided with check bit module control signal, described check bit module control signal
Value is according to whether output verification position is configured, and described check bit control signal is input to the output of each described check bit
In module；
Read only memory carries out following digital independent when mode of operation:
Each described non-check bit output module all switches to mode of operation, and each described non-check bit output module is when each
The clock cycle specifies the non-check bit data of address according to the instruction output of described central control logic circuit；
When described read only memory needs output verification bit data, described check bit control signal makes each described check bit
Output module all switches to mode of operation and each described check bit output module can be according to described in each clock cycle
The check bit data of address are specified in the instruction output of central control logic circuit；When described read only memory need not output
During check bit data, described check bit control signal makes each described check bit output module all in standby mode.
10. the method for reading data of read only memory as claimed in claim 9, it is characterised in that: described storage array
Formed by the arrangement of multiple memory element, each described memory element storage a data.
11. as described in claim 9 or 10 method for reading data of read only memory, it is characterised in that: Ge Weisuo
Stating and include a MUX in output module respectively, described MUX is for selecting in described storage array
Select the data specifying the memory element of address to be stored.
12. as described in claim 9 or 10 method for reading data of read only memory, it is characterised in that: Ge Weisuo
Stating and include a sense amplifier in output module respectively, described sense amplifier is for selected data signal
It is amplified.
The method for reading data of 13. read only memory as claimed in claim 11, it is characterised in that: everybody is described defeated
Going out to include respectively in module a sense amplifier, described sense amplifier is for carrying out selected data signal
Amplify.
The method for reading data of 14. read only memory as claimed in claim 9, it is characterised in that: described read-only storage
Device is the read only memory in intelligent card chip.
The method for reading data of 15. read only memory as claimed in claim 9, it is characterised in that: each described check bit
Output module includes a NAND gate and a not gate, and two inputs of described NAND gate connect described verification respectively
Position control signal and read only memory internal clock cycles pulse signal, the outfan of described NAND gate connects described not gate
Input, described not gate outfan output clock period pulse signal as each described check bit output module
Internal clock cycles pulse signal；
When described read only memory needs output verification bit data, described check bit control signal is 1, each described school
The internal clock cycles pulse signal testing an output module is described read only memory internal clock cycles pulse signal；
When described read only memory need not output verification bit data, described check bit control signal is 0, each described
The internal clock cycles pulse signal low level of check bit output module.
The method for reading data of 16. read only memory as claimed in claim 9, it is characterised in that: each described non-verification
The internal clock cycles pulse signal of position output module is described read only memory internal clock cycles pulse signal.
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| CN201610191833.XA CN105895162B (en) | 2016-03-30 | 2016-03-30 | Read-only memory and its method for reading data |
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| CN201610191833.XA CN105895162B (en) | 2016-03-30 | 2016-03-30 | Read-only memory and its method for reading data |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024000911A1 (en) * | 2022-06-28 | 2024-01-04 | 长鑫存储技术有限公司 | Data conversion circuit and memory device |
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| US20150348645A1 (en) * | 2014-05-05 | 2015-12-03 | Apple Inc. | Reliable readout of fuse data in an integrated circuit |
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| CN1083962A (en) * | 1992-07-30 | 1994-03-16 | 三星电子株式会社 | The semiconductor memory that comprises multiple-error check and correcting circuit |
| CN1909114A (en) * | 2005-08-01 | 2007-02-07 | 株式会社日立制作所 | Semiconductor memory device |
| CN101930799A (en) * | 2009-06-23 | 2010-12-29 | 北京芯技佳易微电子科技有限公司 | Non-volatile memory with error checking/correcting circuit and methods thereof for reading and writing data |
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