CN101916017A - Pixel array, LCD (Liquid Crystal Display) panel and driving method of pixel array - Google Patents
Pixel array, LCD (Liquid Crystal Display) panel and driving method of pixel array Download PDFInfo
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Abstract
The invention relates to a pixel array which comprises a plurality of scanning lines, a plurality of data lines and a plurality of sub-pixels. The sub-pixels are respectively and electrically connected with the corresponding scanning lines and the data lines, each sub-pixel arranged in the nth column comprises a first switch, a first pixel electrode, a second switch, a third switch and a second pixel electrode, the first switch and the second switch are electrically connected with the nth scanning line and the mth data line, the first switch is electrically connected with the first pixel electrode, the second switch is provided with a first signal output end, and the third switch is electrically connected with the (n+i)th scanning line and provided with a second signal output end and a signal input end electrically connected with the first signal output end, and the first signal output end is electrically insulated from the first pixel electrode and the second pixel electrode and extends to below the second pixel electrode so as to form a coupled capacitor with the second pixel electrode. The invention also discloses an LCD (Liquid Crystal Display) panel and a driving method of the pixel array.
Description
Technical field
The present invention relates to a kind of pel array, and particularly relevant for a kind of pel array with good display quality.
Background technology
Along with LCD constantly develops towards large-sized demonstration specification, in order to overcome the visual angle problem under the large scale demonstration, the wide viewing angle technology of display panels also must ceaselessly improve and break through.Wherein, multidomain vertical alignment type (Multi-domain Vertical Alignment, MVA) (Polymer stabilized alignment, PSA) display panels is existing common wide viewing angle technology for display panels and polymer-stabilized alignment.In order to improve the colour cast problem (color washout) in the display panels, having into, rank type multidomain vertical alignment type (Advanced-MVA) display panels is suggested, it mainly is that each sub-pixel area is divided into main viewing area (main display region) and sub-viewing area (sub-displayregion), and by suitable circuit design and driving method, make main viewing area and sub-viewing area in the same sub-pixel have different cross-pressures respectively, to improve the colour cast problem.In the prior art, the design concept that each sub-pixel area is divided into main viewing area and sub-viewing area is applied in the polymer-stabilized alignment liquid crystal display panel.
Fig. 1 is a kind of equivalent circuit diagram of pel array, and Fig. 2 is the synoptic diagram of single sub-pixel among Fig. 1.Please refer to Fig. 1 and Fig. 2, pel array 100 comprises a plurality of sub-pixel P1, and each sub-pixel P1 comprises a first film transistor T FT1, one second thin film transistor (TFT) TFT2, one the 3rd thin film transistor (TFT) TFT3, the first pixel electrode ITO1 that electrically connects with the first film transistor T FT1 and the second pixel electrode ITO2 that electrically connects with the second thin film transistor (TFT) TFT2.The first pixel electrode ITO1 can and form one first storage capacitors Cs1 with common line COM1 coupling, and the first pixel electrode ITO1 can and form one first liquid crystal capacitance CLC1 with a common electrode (indicating) coupling on the subtend substrate (as colored optical filtering substrates).Similarly, the second pixel electrode ITO2 can and form one second storage capacitors Cs2 with common line COM2 coupling, and the second pixel electrode ITO2 can and form one second liquid crystal capacitance CLC2 with common electrode (indicating) coupling on the subtend substrate (as colored optical filtering substrates).
From Fig. 1 and Fig. 2 as can be known, in the sub-pixel P1 that electrically connects with sweep trace SL (n-1), the grid G 1 of the first film transistor T FT1 and the second thin film transistor (TFT) TFT2, G2 can electrically connect with sweep trace SL (n-1), and the grid G 3 of the 3rd thin film transistor (TFT) TFT3 can electrically connect with next bar sweep trace SL (n).In addition, the source S 3 of the 3rd thin film transistor (TFT) TFT3 and the second pixel electrode ITO2 electrically connect, and the drain D 3 of the 3rd thin film transistor (TFT) TFT3 and the first pixel electrode ITO1 are coupled into the first capacitor C cs-a, and the common line COM1 of the drain D 3 of the 3rd thin film transistor (TFT) TFT3 and first pixel electrode ITO1 below is coupled into the second capacitor C cs-b.When applying a high voltage (Vgh) when sweep trace SL (n-1), image data can write in the sub-pixel that is connected with sweep trace SL (n-1) by data line DL (m-1), DL (m), at this moment, the first pixel electrode ITO1 is identical with the voltage of the second pixel electrode ITO2.Then, when applying a high voltage when sweep trace SL (n), the first capacitor C cs-a and the second capacitor C cs-b can make the voltage of the voltage of the first pixel electrode ITO1 and the second pixel electrode ITO2 different.
Because the drain D 2 of the second thin film transistor (TFT) TFT2 can stride across the first pixel electrode ITO1 and be connected with the second pixel electrode ITO2, therefore just produce a stray capacitance Cx1 between the drain D 2 of the second thin film transistor (TFT) TFT2 and the first pixel electrode ITO1.In addition, because the drain D 3 of the 3rd thin film transistor (TFT) TFT3 can stride across the second pixel electrode ITO2, therefore just produce a stray capacitance Cx2 between the drain D 3 of the 3rd thin film transistor (TFT) TFT3 and the second pixel electrode ITO2.Stray capacitance Cx1, Cx2 can make the voltage differences of the first pixel electrode ITO1 and the second pixel electrode ITO2 draw back amplitude to reduce, cause the colour cast problem to improve effectively.Hold above-mentionedly, how to avoid among the sub-pixel P1 stray capacitance Cx1, Cx2, its necessity is arranged in fact for the influence of display quality.
Summary of the invention
The invention provides the driving method of a kind of pel array, polymer-stabilized alignment liquid crystal display panel (PSA-LCD panel) and pel array, it has good display quality.
The invention provides a kind of pel array, it comprises multi-strip scanning line, many data lines and a plurality of sub-pixel.Data line and sweep trace are staggered to define a plurality of subpixel area.Subpixel configuration in subpixel area, each sub-pixel respectively with wherein electric connection of adjacent two sweep traces and data line.Each sub-pixel that is arranged in the n row comprises one first switch, one first pixel electrode, a second switch, one the 3rd switch and one second pixel electrode.First pixel electrode and first switch electrically connect.First switch and second switch and n bar sweep trace and m bar data line electrically connect, and second switch has one first signal output part.The 3rd switch and (n+i) bar sweep trace electrically connect, and wherein the 3rd switch has a signal input part and the secondary signal output terminal that one and first signal output part electrically connects, and i is a positive integer.Second pixel electrode and secondary signal output terminal electrically connect.First signal output part and first pixel electrode and second pixel electrode are electrically insulated.First signal output part extends to second pixel electrode below, to form coupling capacitance with second pixel electrode.
The present invention provides a kind of polymer-stabilized alignment liquid crystal display panel (PSA-LCD panel) in addition, and it comprises one first substrate, one second substrate, two polymkeric substance stable alignment layers and a liquid crystal layer.First substrate has aforesaid pel array, and second substrate is disposed at first substrate top, and two polymkeric substance stable alignment layers are disposed at respectively on first substrate and second substrate.Liquid crystal layer is disposed between the polymer-stabilized alignment layer.
The present invention provides a kind of driving method of pel array again, is suitable for driving aforesaid pel array.The driving method of pel array may further comprise the steps.Open aforesaid sweep trace in regular turn, and image data is recorded in each sub-pixel by aforesaid data line.When n bar sweep trace is applied in a cut-in voltage when opening first switch and second switch, be arranged in first pixel electrode and first signal output part and corresponding data line conducting in each sub-pixels of n row, and the voltage of second pixel electrode is subjected to first signal output part and is coupled and changes.When (n+i) bar sweep trace is applied in a cut-in voltage when opening the 3rd switch, be arranged in second pixel electrode and the first signal output part conducting in each sub-pixels of n row.
Based on above-mentioned, since first signal output part of second switch of the present invention with electrically connect with the 3rd switch, wherein the 3rd switch and second pixel electrode electrically connect, and first signal output part and second pixel electrode can form coupling capacitance, and therefore the voltage difference of first pixel electrode and second pixel electrode is apart from being drawn back effectively because of capacitance coupling effect.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate appended graphic being described in detail below.
Description of drawings
Fig. 1 is a kind of equivalent circuit diagram of pel array;
Fig. 2 is the synoptic diagram of single sub-pixel among Fig. 1;
Fig. 3 is the synoptic diagram of the pel array of first embodiment of the invention;
Fig. 4 A is the schematic layout pattern of the pel array of first embodiment of the invention;
Fig. 4 B is the schematic layout pattern of the pel array of another embodiment of the present invention;
Fig. 4 C is the schematic layout pattern of the pel array of another embodiment of the present invention;
Fig. 5 is the change in voltage synoptic diagram of first pixel electrode, second pixel electrode and first signal output part;
Fig. 6 is the schematic layout pattern of the pel array of second embodiment of the invention;
Fig. 7 A is the schematic layout pattern of the pel array of second embodiment of the invention;
Fig. 7 B is the schematic layout pattern of the pel array of another embodiment of the present invention;
Fig. 8 is the synoptic diagram of polymer-stabilized alignment liquid crystal display panel of the present invention.
Wherein, Reference numeral
100,200a, 200b, 200c, 200 ', 200 ": pel array
210: coupling conductors
SL, SL (n), SL (n+1), SL (n+i-1), SL (n+i): sweep trace
P1, P2: sub-pixel
DL, DL (m), DL (m+1): data line R: subpixel area
TFT1, TFT2, TFT3: on-off element G1, G2, G3: grid
S1, S2, S3: source electrode D1, D2, D3: drain electrode
D2 ': the first signal output part D3 ': signal input part
S3 ': secondary signal output terminal Ccs-a, Ccs-c: first electric capacity
Ccs-b: the second capacitor C x1, Cx2, Cx4, Cx5: stray capacitance
Cx3: coupling capacitance Cs1, Cs2: storage capacitors
CLC1, CLC2: liquid crystal capacitance ITO1: first pixel electrode
ITO2: the second pixel electrode COM, COM1, COM2: common line
300: 310: the first substrates of polymer-stabilized alignment liquid crystal display panel
320: the second substrate 330a, 330b: polymer-stabilized alignment layer
340: liquid crystal layer 400: electrooptical device
AP: opening BR: branch
Embodiment
[first embodiment]
Fig. 3 is the synoptic diagram of the pel array of first embodiment of the invention, and Fig. 4 A is layout (layout) synoptic diagram of the pel array of first embodiment of the invention.Please refer to Fig. 3 and Fig. 4 A, the pel array 200a of present embodiment comprises multi-strip scanning line SL (only showing sweep trace SL (n), SL (n+1), SL (n+i-1), SL (n+i) among Fig. 3 and Fig. 4 A), many data line DL (only showing data line DL (m), DL (m+1) among Fig. 3 and Fig. 4 A) and a plurality of sub-pixel P2.Aforesaid data line DL and sweep trace SL are interlaced with each other, and defining a plurality of subpixel area R, and each sub-pixel P2 is disposed at respectively in the subpixel area R.It should be noted that the sub-pixel P2 that only shows part among Fig. 3 and Fig. 4 A, and the quantity of sub-pixel P2 arranged into an array can be done suitable variation according to the image analytic degree of required demonstration.
Each sub-pixel P2 respectively with wherein electric connection of adjacent two sweep trace SL and data line DL.In the present embodiment, sub-pixel P2 is arranged in multiple row, and is arranged in sub-pixel P2 and n bar sweep trace SL (n), (n+1) bar sweep trace SL (n+1) and data line DL (m) electric connection of n row.In detail, each sub-pixel P2 that is arranged in the n row comprises one first switching TFT 1, one first pixel electrode ITO1, a second switch TFT2, one the 3rd switching TFT 3 and one second pixel electrode ITO2.First switching TFT 1 and second switch TFT2 and n bar sweep trace SL (n) and m bar data line DL (m) electrically connect, and second switch TFT2 has one first signal output part D2 '.The 3rd switching TFT 3 and (n+i) bar sweep trace SL (n+i) electrically connect, and wherein the 3rd switching TFT 3 has a signal input part D3 ' and the secondary signal output terminal S3 ' that the one and first signal output part D2 ' electrically connects, and i is a positive integer.In the present embodiment, i=1, that is the 3rd switching TFT 3 and (n+1) bar sweep trace SL (n+1) electrically connect.
The second pixel electrode ITO2 and secondary signal output terminal S3 ' electrically connect.The first signal output part D2 ' extends to second pixel electrode ITO2 below, to form coupling capacitance Cx3 with the second pixel electrode ITO2.In addition, the first signal output part D2 ' of present embodiment more extends to first pixel electrode ITO1 below, to form a stray capacitance Cx4 with the first pixel electrode ITO1.In addition, in the present embodiment, be arranged in sub-pixel P2 and n bar sweep trace SL (n) and (n+1) bar sweep trace SL (n+1) electric connection of n row.In addition, the first pixel electrode ITO1 and the second pixel electrode ITO2 that is arranged among the sub-pixel P2 of n row for example is positioned between n bar sweep trace SL (n) and (n+1) bar sweep trace SL (n+1).
From Fig. 3 and Fig. 4 A as can be known, each first switching TFT 1 that is arranged in the n row is a first film transistor, and the first film transistor has a first grid G1, one first source S 1 and one first drain D 1.First grid G1 and n bar sweep trace SL (n) electrically connect, wherein electric connection of first source S 1 and data line DL, and first drain D 1 then electrically connects with the first pixel electrode ITO1.
In addition, each second switch TFT2 that is arranged in the n row is one second thin film transistor (TFT), and second thin film transistor (TFT) has a second grid G2, second source S 2 and the aforesaid first signal output part D2 '.Second grid G2 and n bar sweep trace SL (n) electrically connect, and wherein electric connection of second source S 2 and aforementioned data line DL.Second drain D 2 that it should be noted that second thin film transistor (TFT) is the aforesaid first signal output part D2 '.
Each the 3rd switching TFT 3 that is arranged in the n row is one the 3rd thin film transistor (TFT), and the 3rd thin film transistor (TFT) has one the 3rd grid G 3, signal input part D3 ' and secondary signal output terminal S3 '.The 3rd grid G 3 and (n+1) bar sweep trace SL (n+1) electrically connect, and the 3rd source S 3 and the second pixel electrode ITO2 electrically connect.Signal input part D3 ' that it should be noted that the 3rd thin film transistor (TFT) is the 3rd drain D 3, and secondary signal output terminal S3 ' is the 3rd source S 3.
Can know from Fig. 4 A and to learn that the pel array 200a of present embodiment can further comprise many common line COM that are electrically connected to each other that these common line COM are distributed in each first pixel electrode ITO1 and each second pixel electrode ITO2 below.In detail, the common line COM of each bar extends along column direction respectively.
Fig. 5 is the voltage V1 of first pixel electrode, the voltage V2 of second pixel electrode and the voltage V of first signal output part
O1The variation synoptic diagram.Please be simultaneously with reference to Fig. 4 A and Fig. 5, when applying a cut-in voltage (Vgh) at time t (n) when sweep trace SL (n), image data is write by first switching TFT 1 in the sub-pixel that is connected with sweep trace SL (n) by data line DL (m), and at this moment, the voltage of the first pixel electrode ITO1 can rise.On the other hand, image data also can be write in the first signal output part D2 ' by second switch TFT2 by data line DL (m), and at this moment, the voltage of the first signal output part D2 ' is identical in fact with the voltage of the first pixel electrode ITO1.In addition, because the first signal output part D2 ' extends to second pixel electrode ITO2 below, form coupling capacitance Cx3 with the second pixel electrode ITO2, so the voltage of the second pixel electrode ITO2 can be promoted synchronously because of coupling effect.And when stopping to apply cut-in voltage (Vgh) when sweep trace SL (n), the voltage of the first pixel electrode ITO1, the second pixel electrode ITO2 and the first signal output part D2 ' can slightly descend because of feedthrough effect (feed through).
Then, when applying cut-in voltage (Vgh) at time t (n+1) when sweep trace SL (n+1), the voltage of the first pixel electrode ITO1, the second pixel electrode ITO2 and the first signal output part D2 ' can be raised because of applying once again of cut-in voltage.On the other hand, the 3rd switching TFT 3 can be unlocked, and makes the signal output part D2 ' that wins be in conducting state with the second pixel electrode ITO2.Under the situation that electric charge is redistributed, the voltage of the first signal output part D2 ' can descend gradually, and the voltage of the second pixel electrode ITO2 can rise gradually, till the voltage in fact of the first signal output part D2 ' equals the voltage of the second pixel electrode ITO2.At last, as shown in Figure 5, when stopping to apply cut-in voltage when sweep trace SL (n+1), the first pixel electrode ITO1 and the second pixel electrode ITO2 can slightly descend because of the feedthrough effect, and the two voltage is inequality.
From the above, by the coupling effect of coupling capacitance Cx3, the voltage of the second pixel electrode ITO2 can be promoted synchronously, but still less than the voltage of the first pixel electrode ITO1.In other words, the voltage of the first pixel electrode ITO1 is different with the voltage that the second pixel electrode ITO2 is presented, and can improve the colour cast problem.
Watch from another angle, embodiments of the invention also provide a kind of method that drives pel array, and it may further comprise the steps.Open sweep trace SL in regular turn, and image data is recorded among each sub-pixel P2 by data line DL.When n bar sweep trace SL (n) is applied in cut-in voltage when opening first switching TFT 1 with second switch TFT2, be arranged in the first pixel electrode ITO1 and the first signal output part D2 ' and corresponding data line DL (m) conducting among each sub-pixel P2 of n row, and the voltage of the second pixel electrode ITO2 is subjected to the first signal output part D2 ' coupling and changes.When (n+i) bar sweep trace SL (n+i) is applied in cut-in voltage when opening the 3rd switching TFT 3, be arranged in the second pixel electrode ITO2 and the first signal output part D2 ' conducting in each sub-pixels of n row, wherein i is the i=1 of positive integer and present embodiment.In addition, in the present embodiment, when (n+i) bar sweep trace is applied in cut-in voltage when opening the 3rd switching TFT 3, the voltage of the second pixel electrode ITO2 rises, and the voltage of the first signal output part D2 ' descends.
Fig. 4 B is the schematic layout pattern of the pel array of another embodiment of the present invention.The pel array 200b of present embodiment and the pel array 200a of Fig. 4 A are similar, but the two main difference part is: the first signal output part D2 ' that is positioned at first pixel electrode ITO1 top has an opening AP, with first signal output part D2 ' among effective minimizing Fig. 4 A and the formed stray capacitance Cx4 of the first pixel electrode ITO1.That is, present embodiment be by the pairing first pixel electrode ITO1 in the first signal output part D2 ' top is hollowed out or the first signal output part D2 ' and the first pixel electrode ITO1 between the dielectric layer pad thick in minimizing stray capacitance Cx4.
Fig. 4 C is the schematic layout pattern of the pel array of another embodiment of the present invention.The pel array 200c of present embodiment and the pel array 200a of Fig. 4 A are similar, but the two main difference part is: have a BR of branch between the first signal output part D2 ' and the signal input part D3 '.The BR of branch makes the first signal output part D2 ' of part and the common line COM of second pixel electrode ITO2 below can be coupled into the first capacitor C cs-c.
[second embodiment]
Fig. 6 is the synoptic diagram of the pel array of second embodiment of the invention, and Fig. 7 A is the schematic layout pattern of the pel array of second embodiment of the invention.Please refer to Fig. 6 and Fig. 7 A, the pel array 200 ' of present embodiment is similar with the pel array 200c of Fig. 4 C, and only the two main difference part is: pel array 200 ' further comprises at least one coupling conductors 210 (Fig. 7 A only schematically illustrates 2).The coupling conductors 210 and the first pixel electrode ITO1 electrically connect, and wherein coupling conductors 210 extends to second pixel electrode ITO2 below, to form stray capacitance Cx5 with the second pixel electrode ITO2.
From Fig. 7 A as can be known, this coupling conductors of present embodiment extends along the edge of the second pixel electrode ITO2.In the pel array 200 ' of Fig. 6 and Fig. 7 A, coupling capacitance Cx3 is the main electric capacity that improves the colour cast problem, and the stray capacitance Cx5 of the coupling conductors 210 and the second pixel electrode ITO2 can effectively reduce the stray capacitance Cx4 between the first signal output part D2 ' and the first pixel electrode ITO1, therefore the voltage of the first pixel electrode ITO1 and the voltage of the second pixel electrode ITO2 more can be drawn back effectively, and have good display quality.
Fig. 7 B is the schematic layout pattern of the pel array of another embodiment of the present invention.The pel array 200 of present embodiment " similar with pixel array 200 '; but the two main difference part is: the coupling conductors 210 and the second pixel electrode ITO2 electrically connect; wherein coupling conductors 210 extends to first pixel electrode ITO1 below, to form stray capacitance Cx5 with the first pixel electrode ITO1.
In a further embodiment, can be similar with the represented embodiment of Fig. 7 A and Fig. 7 B, but the two main difference part is: the first signal output part D2 ' that is positioned at first pixel electrode ITO1 top has an opening AP, with first signal output part D2 ' among effective minimizing Fig. 7 A and Fig. 7 B and the formed stray capacitance Cx4 of the first pixel electrode ITO1.
[the 3rd embodiment]
Fig. 8 is the synoptic diagram of polymer-stabilized alignment liquid crystal display panel of the present invention.Please refer to Fig. 8, the polymer-stabilized alignment liquid crystal display panel 300 of present embodiment comprises one first substrate 310, one second substrate 320, two polymkeric substance stable alignment layer 330a, 330b and a liquid crystal layer 340.First substrate 310 has the pel array (200 or 200 ') among aforementioned first embodiment or second embodiment, second substrate 320 is disposed at first substrate, 310 tops, and two polymkeric substance stable alignment layer 330a, 330b are disposed at respectively on first substrate 310 and second substrate 320.In addition, liquid crystal layer 340 is disposed between two polymkeric substance stable alignment layer 330a, the 330b.It should be noted that, liquid crystal layer 340 employing on making includes can be by the liquid crystal material of the monomer of energy source polymerization, when energy source (as ultraviolet light) when being applied in liquid crystal layer 340, these can be distinguished polymerization on the surface of first substrate 310 and second substrate 320 by the monomer of energy source polymerization, to form two polymkeric substance stable alignment layer 330a, 330b.
Based on above-mentioned, because first signal output part of second switch of the present invention and the 3rd switch electrically connect, wherein the 3rd switch and second pixel electrode electrically connect, and first signal output part and second pixel electrode can form coupling capacitance, therefore the voltage difference distance of first pixel electrode and second pixel electrode can be because of capacitance coupling effect be drawn back effectively, and then makes pel array of the present invention that preferable image quality can be provided.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.
Claims (14)
1. a pel array is characterized in that, comprising:
The multi-strip scanning line;
Many data lines, staggered with these sweep traces to define a plurality of subpixel area;
A plurality of sub-pixels, be disposed in these subpixel area, respectively this sub-pixel respectively with wherein electric connections of adjacent two sweep traces and these data lines, respectively this sub-pixel that wherein is arranged in the n row comprises one first switch, one first pixel electrode, a second switch, one the 3rd switch and one second pixel electrode, wherein:
This first switch;
This first pixel electrode electrically connects with this first switch;
This second switch, this first switch and this second switch and n bar sweep trace and m bar data line electrically connect, and this second switch has one first signal output part;
The 3rd switch electrically connects with (n+i) bar sweep trace, and wherein the 3rd switch has a signal input part and a secondary signal output terminal that electrically connects with this first signal output part, and i is a positive integer; And
This second pixel electrode, electrically connect with this secondary signal output terminal, wherein this first signal output part and this first pixel electrode and this second pixel electrode are electrically insulated, and this first signal output part extends to this second pixel electrode below, to form a coupling capacitance with this second pixel electrode.
2. pel array according to claim 1 is characterized in that these arrangement of subpixels become multiple row, and is arranged in sub-pixel and the n bar sweep trace and the electric connection of (n+1) bar sweep trace of n row.
3. pel array according to claim 1 is characterized in that, this first pixel electrode and this second pixel electrode that are arranged in the sub-pixel of n row are positioned between n bar sweep trace and (n+1) bar sweep trace.
4. pel array according to claim 1, it is characterized in that, respectively this first switch that is arranged in the n row is a first film transistor, and this first film transistor have a first grid that electrically connects with n bar sweep trace, one with first source electrode of the wherein electric connection of these data lines and one and first the draining of this first pixel electrode electric connection.
5. pel array according to claim 1, it is characterized in that, respectively this second switch that is arranged in the n row is one second thin film transistor (TFT), and this second thin film transistor (TFT) have one with the second grid of n bar sweep trace electric connection, one and second source electrode and this first signal output part of the wherein electric connection of these data lines.
6. pel array according to claim 1, it is characterized in that, respectively the 3rd switch that is arranged in the n row is one the 3rd thin film transistor (TFT), and the 3rd thin film transistor (TFT) have one with the 3rd grid, this signal input part and this secondary signal output terminal of (n+1) bar sweep trace electric connection.
7. pel array according to claim 1 is characterized in that, this first signal output part more extends to this first pixel electrode below, to form one first stray capacitance with this first pixel electrode.
8. pel array according to claim 7, it is characterized in that, more comprise at least one coupling conductors, electrically connect with this first pixel electrode, wherein this coupling conductors extends to this second pixel electrode below, to form one second stray capacitance with this second pixel electrode.
9. pel array according to claim 8 is characterized in that, this coupling conductors extends along the edge of this second pixel electrode.
10. described pel array according to claim 7, it is characterized in that, more comprise at least one coupling conductors, electrically connect with this second pixel electrode, wherein this coupling conductors extends to this first pixel electrode below, to form one second stray capacitance with this first pixel electrode.
11. pel array according to claim 10 is characterized in that, this coupling conductors extends along the edge of this first pixel electrode.
12. a polymer-stabilized alignment liquid crystal display panel is characterized in that, comprising:
One first substrate has the described pel array of claim 1;
One second substrate is disposed at this first substrate top;
Two polymkeric substance stable alignment layers are disposed at respectively on this first substrate and this second substrate; And
One liquid crystal layer is disposed between these polymer-stabilized alignment layers.
13. the driving method of a pel array is characterized in that, is suitable for driving the described pel array of claim 1, the driving method of this pel array comprises:
Open these sweep traces in regular turn, and image data is recorded in respectively in this sub-pixel by these data lines; When n bar sweep trace is applied in a cut-in voltage when opening this first switch and this second switch, be arranged in these first pixel electrodes and these first signal output parts and corresponding data line conducting in respectively this sub-pixels of n row, and the voltage of this second pixel electrode is subjected to this first signal output part and is coupled and changes; When (n+i) bar sweep trace is applied in a cut-in voltage when opening the 3rd switch, be arranged in these second pixel electrodes and this first signal output part conducting in respectively this sub-pixels of n row.
14. the driving method of pel array according to claim 13 is characterized in that, when (n+i) bar sweep trace is applied in a cut-in voltage when opening the 3rd switch, the voltage of this second pixel electrode rises, and the voltage of this first signal output part descends.
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| CN102540528A (en) * | 2011-11-14 | 2012-07-04 | 友达光电股份有限公司 | Display panel and driving method thereof |
| CN103091923A (en) * | 2013-01-31 | 2013-05-08 | 深圳市华星光电技术有限公司 | Array substrate and liquid crystal display device |
| CN103969909A (en) * | 2013-01-25 | 2014-08-06 | 达意科技股份有限公司 | Electrophoretic display |
| CN105652547A (en) * | 2016-04-15 | 2016-06-08 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof as well as display panel and display device |
| CN106842743A (en) * | 2017-02-09 | 2017-06-13 | 深圳市华星光电技术有限公司 | A kind of liquid crystal pixel circuit and liquid crystal display device |
| US10163412B2 (en) | 2014-11-19 | 2018-12-25 | Au Optronics Corporation | Pixel structure |
| CN111381406A (en) * | 2018-12-29 | 2020-07-07 | 咸阳彩虹光电科技有限公司 | Pixel unit, pixel array and liquid crystal panel thereof |
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| CN102540528A (en) * | 2011-11-14 | 2012-07-04 | 友达光电股份有限公司 | Display panel and driving method thereof |
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| CN103091923B (en) * | 2013-01-31 | 2015-02-18 | 深圳市华星光电技术有限公司 | Array substrate and liquid crystal display device |
| US10163412B2 (en) | 2014-11-19 | 2018-12-25 | Au Optronics Corporation | Pixel structure |
| CN105652547A (en) * | 2016-04-15 | 2016-06-08 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof as well as display panel and display device |
| CN106842743A (en) * | 2017-02-09 | 2017-06-13 | 深圳市华星光电技术有限公司 | A kind of liquid crystal pixel circuit and liquid crystal display device |
| CN106842743B (en) * | 2017-02-09 | 2019-11-15 | 深圳市华星光电技术有限公司 | A kind of liquid crystal pixel circuit and liquid crystal display device |
| CN111381406A (en) * | 2018-12-29 | 2020-07-07 | 咸阳彩虹光电科技有限公司 | Pixel unit, pixel array and liquid crystal panel thereof |
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