CN100354739C - Picture element structure and active component array substrate - Google Patents
Picture element structure and active component array substrate Download PDFInfo
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- CN100354739C CN100354739C CNB2005100747985A CN200510074798A CN100354739C CN 100354739 C CN100354739 C CN 100354739C CN B2005100747985 A CNB2005100747985 A CN B2005100747985A CN 200510074798 A CN200510074798 A CN 200510074798A CN 100354739 C CN100354739 C CN 100354739C
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Abstract
The present invention relates to a pixel structure which is electrically connected with a scan wire and a data wire. The pixel structure comprises an active block, a first pixel electrode, a second pixel electrode, a capacitance coupling electrode and a charge releasing assembly, wherein the active block is electrically connected with the scan wire and the data wire; the first pixel electrode is electrically connected with the data wire through the active block; the second pixel electrode and the first pixel electrode are electrically insulated; the capacitance coupling electrode is arranged below the second pixel electrode and is electrically connected with the data wire through the active block; the charge releasing assembly is electrically connected with the second pixel electrode. The pixel structure can effectively solve the problem of image retention. The present invention also provides an active block array substrate which can avoid image retention.
Description
Technical field
The present invention relates to a kind of dot structure and active component array substrate, and be particularly related to a kind of dot structure and the active component array substrate that can avoid image retention (image sticking).
Background technology
(Thin Film Transistor LiquidCrystal Display, performance requirement TFT-LCD) are towards characteristics such as height contrast (high contrastratio), the counter-rotating of no GTG (no gray scale inversion), colour cast little (little colorshift), brightness height (high luminance), high color richness, high color saturation, rapid reaction and wide viewing angles to existing market for the membrane transistor LCD.Can reach the technology of wide viewing angle requirement at present, for example stable twisted nematic liquid crystal (TN) adds view film (wide viewing film), copline suitching type (In-Plane Switching, IPS) LCD, limit suitching type (fringe field switching) LCD and multidomain vertical alignment type membrane transistor LCD modes such as (MVA TFT-LCD).
Fig. 1 illustrates a kind of diagrammatic cross-section of existing multi-field vertical assigned LCD panel.Please refer to Fig. 1, existing multi-field vertical assigned LCD panel 100 comprises electric crystal array film substrate 110, colored optical filtering substrates 120 and the liquid crystal layer 130 between electric crystal array film substrate 110 and colored optical filtering substrates 120.Wherein, electric crystal array film substrate 110 has a plurality of pixel electrodes 112, and pixel electrode 112 has slit (slit) 112a, and has one on the colored optical filtering substrates 120 and share electrode 122 and be disposed at orientation protrusion (alignment protrusion) 124 on the shared electrode 122.Because pixel electrode 112 has slit 112a, and the orientation protrusion 124 that is disposed on the shared electrode 122 can make liquid crystal molecule 130 be multi-direction arrangement, obtaining several different field A, B, so multi-field vertical assigned LCD panel 100 can be reached the requirement of wide viewing angle.It should be noted that in same dot structure the liquid crystal capacitance value in field A and the field B all maintains Clc.Yet, when the user when different visual angles is watched vertical alignment type liquid crystal display panel 100, its penetrance just changes to some extent to the curve (transmittance-level curve) of GTG.Change speech, when the user when different visual angles is watched, the shown brightness that goes out of existing multiple domain vertical orientation type liquid crystal display 100 just can change, and then causes color saturation deficiency phenomenons such as (color washout).
Fig. 2 A and Fig. 2 B illustrate the diagrammatic cross-section of another kind of existing multi-field vertical assigned LCD panel.Please be simultaneously with reference to Fig. 2 A and Fig. 2 B, phenomenon for fear of color saturation deficiency (color washout), prior art has developed and another kind of multi-field vertical assigned LCD panel 200, and it comprises electric crystal array film substrate 210, colored optical filtering substrates 220 and the liquid crystal layer 230 between electric crystal array film substrate 210 and colored optical filtering substrates 220.Wherein, electric crystal array film substrate 210 has a plurality of pixel electrodes 212,214, and pixel electrode 212,214 all has slit (not illustrating), and has one on the colored optical filtering substrates 220 and share electrode 222 and be disposed at orientation protrusion 224 on the shared electrode 222.
It should be noted that, pixel electrode 212 is to be electrically insulated each other with pixel electrode 214, and when multi-field vertical assigned LCD panel 200 drives, pixel electrode 212 is coupled to voltage level Vdata, the pixel electrode of electrically floating 214 then is to maintain voltage level Vcc by capacity coupled effect (C.C.), and voltage level Vdata＞voltage level Vcc.In view of the above, multi-field vertical assigned LCD panel 200 can be divided into field A, field B, field A ' and field B '; Anticipate promptly, pixel electrode 212 can maintain different voltage levels with pixel electrode 214, to reach the effect of color saturation compensation.More particularly, the liquid crystal capacitance value of pixel electrode 212 tops is to maintain Clc1 (field A and field B), and the liquid crystal capacitance value of pixel electrode 214 tops is to maintain Clc2 (field A ' and field B '), and Clc1＞Clc2.
Shown in Fig. 2 B, because pixel electrode 214 is to be in the state of electrically floating, therefore multi-field vertical assigned LCD panel 200 is easy to because of positive and negative charge unbalance the phenomenon of electric charge sunken by hindering (trapped) in alignment film PI take place in the process that drives, and then cause the voltage level drift (shift) of pixel electrode 214 so the finally very serious image retention problem of this wide viewing angle technological side.
Summary of the invention
The purpose of this invention is to provide a kind of dot structure, it can effectively avoid the problem of image retention.
Another object of the present invention provides a kind of active component array substrate, and it can effectively avoid the problem of image retention.
The invention provides a kind of dot structure, is to be electrically connected at an one scan line and a data line, and this dot structure comprises an active block, one first pixel electrode, one second pixel electrode, a capacitive coupling electrode and an electric charge releasing unit.Wherein, active block is to be electrically connected at sweep trace and data line.First pixel electrode is to be electrically connected at data line by active block.Second pixel electrode is to be electrically insulated with first pixel electrode.Capacitive coupling electrode is to be configured in second pixel electrode below, and capacitive coupling electrode is to be electrically connected at data line by active block.The electric charge releasing unit then is to be electrically connected at second pixel electrode.
The invention provides a kind of active component array substrate, it comprises a substrate, multi-strip scanning line, many data lines and a plurality of aforesaid dot structure.Wherein, sweep trace, data line and dot structure all are configured on the substrate, and dot structure is to be electrically connected at sweep trace and data line accordingly.
In an embodiment of the present invention, the electric charge releasing unit for example is a capacitor.For example, capacitor comprises that the top electrode and of one and second pixel electrode electric connection is positioned at the bottom electrode of top electrode below.Wherein, the voltage level of bottom electrode is identical with the voltage level of sweep trace.In a preferred embodiment, capacitor is that the subregion by the subregion of sweep trace and second pixel electrode is constituted.More specifically, second pixel electrode has an outshot, and outshot is the subregion top that is positioned at sweep trace, and capacitor is that subregion and teat branch by sweep trace constitutes.
In an embodiment of the present invention, the electric charge releasing unit (capacitor) of each dot structure for example is to be positioned at the sweep trace top that drives dot structure itself, or is positioned at next bar sweep trace top, also or simultaneously is positioned on aforesaid two kinds of positions.
In an embodiment of the present invention, active block for example is a first film electric crystal.For example, the first film electric crystal has a first grid, one first channel layer, one first source electrode and first drain electrode, and wherein, first grid is to be electrically connected at sweep trace, and first source electrode is to be electrically connected at data line, and first drain electrode is to be electrically connected at first pixel electrode.
In an embodiment of the present invention, the electric charge releasing unit for example is one second membrane transistor, and the W/L value of second membrane transistor is the W/L value less than the first film electric crystal.In addition, second membrane transistor has a second grid, one second channel layer, one second source electrode and second drain electrode, and wherein, second grid is to be electrically connected at sweep trace, and second source electrode is to be electrically connected at data line, and second drain electrode is to be electrically connected at second pixel electrode.
In an embodiment of the present invention, first pixel electrode and second pixel electrode for example all have jagged slit (jagged slits).
The present invention is because of employing electric charge releasing unit (capacitor or membrane transistor), so the present invention can discharge the electric charge in the dot structure effectively when each data write.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 is a kind of diagrammatic cross-section of existing multi-field vertical assigned LCD panel.
Fig. 2 A and Fig. 2 B are the diagrammatic cross-section of another kind of existing multi-field vertical assigned LCD panel.
Fig. 3 is the vertical view according to the first embodiment of the invention dot structure.
Fig. 3 ' is the vertical view according to another kind of dot structure in the first embodiment of the invention.
Fig. 4 is the circuit diagram according to the first embodiment of the invention dot structure.
Fig. 5 A to Fig. 5 C is the partial enlarged drawing of electric charge releasing unit among Fig. 3.
Fig. 6 is the vertical view according to the second embodiment of the invention dot structure.
Fig. 6 ' is the vertical view according to another kind of dot structure in the second embodiment of the invention.
Fig. 7 is the circuit diagram according to the second embodiment of the invention dot structure.
The reference numeral explanation
100,200: multi-field vertical assigned LCD panel
110,210: electric crystal array film substrate
112,212,214: pixel electrode
112a: slit
120,220: colored optical filtering substrates
122,222: shared electrode
124,224: the orientation protrusion
130,230: liquid crystal layer
A, B, A ', B ': field
PI: alignment film
300,300 ': dot structure
310: active block
310a: the first film electric crystal
310b: second membrane transistor
320: the first pixel electrodes
320a, 320b: slit
330: the second pixel electrodes
332: outshot
340: capacitive coupling electrode
342,346: top electrode
344,345,348: contact hole
350: the electric charge releasing unit
400: sweep trace
400a: opening
410: shared electrode
500: data line
G, G1, G2: grid
C, C1, C1: channel layer
S, S1, S2: source electrode
D, D1, D2: drain electrode
Embodiment
Because the image retention problem that prior art faced, the present invention proposes some and has the dot structure of electric charge releasing unit and the embodiment of active component array substrate, with details are as follows.Dot structure of the present invention and active component array substrate can be avoided the accumulation of electric charge by the electric charge releasing unit, and then avoid the problem of image retention.
First embodiment
Fig. 3 illustrates and is the vertical view according to the first embodiment of the invention dot structure.Please refer to Fig. 3, the dot structure 300 of present embodiment is to be electrically connected at an one scan line 400 and a data line 500.As shown in Figure 3, dot structure 300 comprises an active block 310, one first pixel electrode 320, one second pixel electrode 330, a capacitive coupling electrode 340 and an electric charge releasing unit 350.Wherein, active block 310 is to be electrically connected at sweep trace 400 and data line 500.First pixel electrode 320 is to be electrically connected at data line 500 by active block 310.Second pixel electrode 330 is to be electrically insulated with first pixel electrode 320.Capacitive coupling electrode 340 is to be disposed at second pixel electrode, 330 belows, and capacitive coupling electrode 340 is to be electrically connected at data line 500 by active block 310.350 of electric charge releasing units are to be electrically connected at second pixel electrode 330.
In the present embodiment, first pixel electrode 320 for example has jagged slit 320a, and second pixel electrode 330 for example has jagged slit 330a.Above-mentioned zigzag slit 320a, 330a can carry out orientation to liquid crystal molecule, to reach the purpose of wide viewing angle.
Fig. 4 illustrates and is the circuit diagram according to the first embodiment of the invention dot structure.Please be simultaneously with reference to Fig. 3 and Fig. 4, in order to keep good display quality, the dot structure of present embodiment can further comprise a holding capacitor Cst1, and this holding capacitor Cst1 is made of shared electrode 410, top electrode 342 and the dielectric layer between the two (for example being gate insulation layer).Wherein, top electrode 342 is except being connected with capacitive coupling electrode 340, and top electrode 342 also can electrically connect by the contact hole 344 in the protective seam (not illustrating) and first pixel electrode 320.Except holding capacitor Cst1, the dot structure of present embodiment can further comprise a holding capacitor Cst2, this holding capacitor Cst2 for example be by shared electrode 410, top electrode 346 and be positioned at the two between dielectric layer (for example being gate insulation layer) constituted.Wherein, top electrode 346 is to be electrically connected at second pixel electrode 330 by the contact hole 348 in the protective seam (not illustrating).
Please be simultaneously with reference to Fig. 3 and Fig. 4, the active block 310 of present embodiment for example is a membrane transistor, and this membrane transistor has a grid G, a channel layer C, one source pole S and drain D.Wherein, grid G is to be electrically connected at or directly to be integrated in the sweep trace 400, and source electrode D is electrically connected at or directly is integrated in the data line 500.In addition, drain D is to be electrically connected at first pixel electrode 320; More specifically, the drain D of present embodiment for example is that top electrode 342 and contact hole 344 by capacitive coupling electrode 340, holding capacitor Cst1 is electrically connected at first pixel electrode 320.
As shown in Figure 3 and Figure 4; if a view data will be write in the dot structure 3 00; present embodiment can provide a high voltage Vgh to sweep trace 400 to open active block 310 (grid G of membrane transistor); afterwards again by data line 500 with view data (Vdata) via the active block 310 (source S of membrane transistor; channel layer C and drain D) capacitive coupling electrode 340; the top electrode 342 of holding capacitor Cst1 and the contact hole 344 that is arranged in protective seam (not illustrating) write to first pixel electrode 320, so that first pixel electrode 320 maintains voltage level Vdata.Yet when view data being write first pixel electrode 320, second pixel electrode 330 can be coupled to voltage level Vcc because of the coupling effect (C.C.) of capacitive coupling electrode 340, and voltage level Vda ta＞voltage level Vcc.In view of the above, corresponding to identical view data (Vdata), first pixel electrode 320 can maintain different voltage levels respectively with second pixel electrode 330.In addition, shared electrode (Vcom) on first pixel electrode 320, liquid crystal layer and the subtend substrate (as colored filter substrate) is to constitute a liquid crystal capacitance Clc1, and the shared electrode (Vcom) on second pixel electrode 330, liquid crystal layer and the subtend substrate is to constitute a liquid crystal capacitance Clc2.
It should be noted that, the electric charge releasing unit 350 of present embodiment is played the part of crucial role in dot structure 300, particularly, electric charge releasing unit 350 can effectively avoid electric charge to be sunk into phenomenon in the alignment film by resistance, and its detailed mechanism will be arranged in pairs or groups after Fig. 3 to Fig. 5 is specified in.
Please be simultaneously with reference to Fig. 3 to Fig. 4; the electric charge releasing unit 350 of present embodiment for example is a capacitor, the bottom electrode and that it top electrode, one that comprises that one and second pixel electrode 330 electrically connects is positioned at the top electrode below be positioned at the two between dielectric layer (for example being protective seam).Wherein, the voltage level of bottom electrode for example is identical with the voltage level of sweep trace 400, and except active block 310 be unlocked during, the voltage level of the two all maintains Vg1 (for example being about-6 volts).Because the voltage level of bottom electrode all is to maintain Vg1 in most of the time, and voltage level Vg1＜voltage level Vdata, therefore electric charge releasing unit 350 can suppress the phenomenon of positive and negative charge unbalance by capacitance coupling effect, and then avoids the problem of image retention.
As shown in Figure 3, the capacitor of present embodiment is made of the subregion of sweep trace 400 and the subregion of second pixel electrode 330.More specifically, second pixel electrode 330 has an outshot 332, and outshot 332 is the tops, subregion that are positioned at sweep trace 400; Anticipate promptly, capacitor is made of the subregion of sweep trace 400 and outshot 332.The design of this capacitor can be made under the prerequisite of changing processing step not significantly, can not cause the burden on the cost.
Hold above-mentioned, in the dot structure 300 that Fig. 3 illustrated, electric charge releasing unit 350 (capacitor) is to be positioned at sweep trace 400 tops that drive dot structure 300 itself, yet, any personage who has the knack of this technology is behind reference foregoing of the present invention, when doing suitable change at the position of electric charge releasing unit 350.
For example, when aforesaid dot structure 300 constitutes an active component array substrate with the array way arrangement, the present invention can be made in electric charge releasing unit 350 (capacitor) next bar sweep trace top, or is made in aforesaid two sweep traces top simultaneously.It should be noted that if electric charge releasing unit 350 (capacitor) is that the capacitance of capacitor will not be vulnerable to the influence of technology mis-alignment (mis-alignment) when being made in aforesaid two sweep traces top simultaneously.Change speech, the electric charge releasability of each electric charge releasing unit 350 (capacitor) on the active component array substrate will be very approaching.
Fig. 5 A to Fig. 5 C illustrates the partial enlarged drawing into electric charge releasing unit among Fig. 3.Please refer to Fig. 5 A to Fig. 5 C, present embodiment optionally forms opening 400a on sweep trace 400, and the position of this opening 400a for example is the end corresponding to outshot 332.In design, the end of outshot 332 is a principle not exceed opening 400a, when first pixel electrode 320 (being illustrated in Fig. 3) and second pixel electrode 330 when making mis-alignment take place and during along level or vertical offset, outshot 332 can be kept necessarily with the overlapping area (oblique line part) of sweep trace 400, and then make the electric charge releasability of electric charge releasing unit 350 (capacitor) with identical.In addition, in the present embodiment, outshot 332 changes (shown in Fig. 5 A to Fig. 5 C) with the visual product design demand of overlapping area (oblique line part) of sweep trace 400.
Fig. 3 ' illustrates and is the vertical view according to another kind of dot structure in the first embodiment of the invention.Please be simultaneously with reference to Fig. 3 and Fig. 3 ', the holding capacitor in the dot structure 300 of present embodiment can adopt the design of various different kenels.In the dot structure 300 that Fig. 3 illustrated, the holding capacitor that holding capacitor that is made of top electrode 342 and shared electrode 410 and top electrode 346 and shared electrode 410 are constituted all belongs to the capacitor (MIM-typecapacitor) of a kind of metal level-insulation course-metal level kenel.In addition, in the dot structure 300 that Fig. 3 ' illustrated, the holding capacitor that is made of top electrode 342 and shared electrode 410 belongs to the capacitor (MIM-type capacitor) of a kind of metal level-insulation course-metal level kenel, and is belonged to the capacitor (MII-typecapacitor) of a kind of metal level-insulation course-indium tin oxide kenel by the holding capacitor that second pixel electrode 330 and shared electrode 410 are constituted.Particularly, the design of having omitted top electrode 346 in the dot structure 300 of Fig. 3 '.Hold above-mentionedly, the personage who has the knack of this technology is after the disclosed content of reference present embodiment, when making further change at kenel, the arrangement position of holding capacitor.
Second embodiment
Fig. 6 illustrates and is the vertical view according to the second embodiment of the invention dot structure.The dot structure 300 of the dot structure 300 ' of present embodiment and first embodiment is similar, only the main difference of the two is: be to control by a first film electric crystal 310a and one second membrane transistor 310b in the dot structure 300 ' of present embodiment, wherein, the first film electric crystal 310a is electrically connected at first pixel electrode 320, and the second membrane transistor 310b is electrically connected at second pixel electrode 330, and the W/L value (breadth length ratio) of the second membrane transistor 310b is the W/L value less than the first film electric crystal 310a.
For example, the first film electric crystal 310a has a first grid G1, one first channel layer C1, one first source S 1 and first drain D 1, wherein, first grid G1 is electrically connected at or is integrated in the sweep trace 400, and first source S 1 is to be electrically connected at or to be integrated in the data line 500, and first drain D 1 is to be electrically connected at first pixel electrode 320.In addition, the second membrane transistor 310b of present embodiment is for can be considered a kind of electric charge releasing unit.The second membrane transistor 310b has a second grid G2, one second channel layer C2, one second source S 2 and second drain D 2, wherein, second grid G2 is electrically connected at sweep trace 400, and second source S 2 is to be electrically connected at data line 500, and second drain D 2 is to be electrically connected at second pixel electrode 330.
Fig. 7 illustrates and is the circuit diagram according to the second embodiment of the invention dot structure.Please be simultaneously with reference to Fig. 6 and Fig. 7; if a view data will be write in the dot structure 300 '; present embodiment can provide a high voltage Vgh to sweep trace 400 with the first grid G1 that opens the first film electric crystal 310a and the second grid G2 of the second membrane transistor 310b; after again by data line 500 with first source S 1 of view data (Vdata) via the first film electric crystal 310a; the first channel layer C1; first drain D 1; capacitive coupling electrode 340; the top electrode 342 of holding capacitor Cst1 and the contact hole 344 that is arranged in protective seam (not illustrating) write to first pixel electrode 320, so that first pixel electrode 320 maintains voltage level Vda ta.Yet; when view data being write first pixel electrode 320; view data (Vda ta) can write to second pixel electrode 330 via second source S 2, the second channel layer C1, second drain D 2, the capacitive coupling electrode 340 of the second membrane transistor 310b and the contact hole 345 that is arranged in protective seam (not illustrating); so that second pixel electrode 330 maintains voltage level Vcc, and voltage level Vdata＞voltage level Vcc.In view of the above, corresponding to identical view data (Vda ta), first pixel electrode 320 can maintain different voltage levels respectively with second pixel electrode 330.In addition, shared electrode (Vcom) on first pixel electrode 320, liquid crystal layer and the subtend substrate (as colored filter substrate) constitutes a liquid crystal capacitance Clc1, and the shared electrode (Vcom) on second pixel electrode 330, liquid crystal layer and the subtend substrate (as colored filter substrate) constitutes a liquid crystal capacitance Clc2.
Fig. 6 ' illustrates and is the vertical view according to another kind of dot structure in the second embodiment of the invention.Please be simultaneously with reference to Fig. 6 and Fig. 6 ', the holding capacitor in the dot structure 300 ' of present embodiment can adopt the design of various different kenels equally.In the dot structure 300 ' that Fig. 6 illustrated, the holding capacitor that holding capacitor that is made of top electrode 342 and shared electrode 410 and top electrode 346 and shared electrode 410 are constituted all belongs to the capacitor (MIM-typecapacitor) of a kind of metal level-insulation course-metal level kenel.In addition, in the dot structure 300 ' that Fig. 6 ' illustrated, the holding capacitor that is made of top electrode 342 and shared electrode 410 belongs to the capacitor (MIM-type capacitor) of a kind of metal level-insulation course-metal level kenel, and is belonged to the capacitor (MII-typecapacitor) of a kind of metal level-insulation course-indium tin oxide kenel by the holding capacitor that second pixel electrode 330 and shared electrode 410 are constituted.Particularly, omitted the design of top electrode 346 in the dot structure 300 ' of Fig. 6 '.Hold above-mentionedly, the personage who has the knack of this technology is after the disclosed content of reference present embodiment, when making further change at kenel, the arrangement position of holding capacitor.
In sum, have following advantage at least at dot structure of the present invention and active component array substrate:
1. dot structure of the present invention and active component array substrate can effectively be avoided the problem of image retention.
2. dot structure of the present invention and active component array substrate on making with existing process compatible, need not significantly change technology.
3. the electric charge releasing unit in dot structure of the present invention and the active component array substrate is a framework in the sweep trace top, does not influence the aperture opening ratio of panel.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; anyly be familiar with those of ordinary skill in the art; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so the scope of the present invention is with being as the criterion that claims were defined.
Claims (20)
1. a dot structure is to be electrically connected at an one scan line and a data line, and this dot structure comprises:
One active block is electrically connected at this sweep trace and this data line;
One first pixel electrode, it is electrically connected at this data line by this active block;
One second pixel electrode is electrically insulated with this first pixel electrode;
One capacitive coupling electrode be disposed at this second pixel electrode below, and this capacitive coupling electrode is to be electrically connected at this data line by this active block; And
One electric charge releasing unit is electrically connected at this second pixel electrode.
2. dot structure as claimed in claim 1, wherein, this electric charge releasing unit is a capacitor.
3. dot structure as claimed in claim 2, wherein, this capacitor comprises:
One top electrode electrically connects with this second pixel electrode; And
One bottom electrode is positioned at this top electrode below, and wherein, the voltage level of this bottom electrode is identical with the voltage level of this sweep trace.
4. dot structure as claimed in claim 2, wherein, this capacitor is that the subregion by the subregion of this sweep trace and this second pixel electrode is constituted.
5. dot structure as claimed in claim 2, wherein, this second pixel electrode has an outshot, and this outshot is the subregion top that is positioned at this sweep trace, and this capacitor is that subregion and this teat branch by this sweep trace constitutes.
6. dot structure as claimed in claim 1, wherein, this active block is a first film electric crystal.
7. dot structure as claimed in claim 6, wherein, this the first film electric crystal has a first grid, one first channel layer, one first source electrode and first drain electrode, this first grid is to be electrically connected at this sweep trace, and this first source electrode is to be electrically connected at this data line, and this first drain electrode is to be electrically connected at this first pixel electrode.
8. dot structure as claimed in claim 6, wherein, this electric charge releasing unit is one second membrane transistor, and this second membrane transistor breadth length ratio value is less than the breadth length ratio value of this first film electric crystal.
9. dot structure as claimed in claim 8, wherein, this second membrane transistor has a second grid, one second channel layer, one second source electrode and second drain electrode, this second grid is to be electrically connected at this sweep trace, and this second source electrode is to be electrically connected at this data line, and this second drain electrode is to be electrically connected at this second pixel electrode.
10. dot structure as claimed in claim 1, wherein, this first pixel electrode and this second pixel electrode all have jagged slit.
11. an active component array substrate comprises:
One substrate;
The multi-strip scanning line is disposed on this substrate;
Many data lines are disposed on this substrate;
A plurality of dot structures, and these dot structures are to be electrically connected at this sweep trace and this data line accordingly, and each dot structure comprises:
One active block is electrically connected at this sweep trace and this data line;
One first pixel electrode is electrically connected at this data line by this active block;
One second pixel electrode is electrically insulated with this first pixel electrode;
One capacitive coupling electrode is disposed at this second pixel electrode below, and wherein, this capacitive coupling electrode is electrically connected at this data line by this active block; And
One electric charge releasing unit is electrically connected at this second pixel electrode.
12. active component array substrate as claimed in claim 11, wherein, this electric charge releasing unit is a capacitor.
13. active component array substrate as claimed in claim 12, wherein, this capacitor comprises:
One top electrode is electrically connected at this second pixel electrode; And
One bottom electrode is positioned at this top electrode below, and wherein, the voltage level of this bottom electrode is identical with the voltage level of this sweep trace.
14. active component array substrate as claimed in claim 12, wherein, this capacitor is that the subregion by the subregion of at least one sweep trace and this second pixel electrode is constituted.
15. active component array substrate as claimed in claim 12, wherein, this second pixel electrode has an outshot, and this outshot is the subregion top that is positioned at this sweep trace, and this capacitor is that subregion and this teat branch by at least one sweep trace constitutes.
16. active component array substrate as claimed in claim 11, wherein, this active block is a first film electric crystal.
17. active component array substrate as claimed in claim 16, wherein, this the first film electric crystal has a first grid, one first channel layer, one first source electrode and first drain electrode, this first grid is to be electrically connected at this sweep trace, and this first source electrode is to be electrically connected at this data line, and this first drain electrode is to be electrically connected at this first pixel electrode.
18. active component array substrate as claimed in claim 16, wherein, this electric charge releasing unit is one second membrane transistor, and the breadth length ratio value of this second membrane transistor is less than the breadth length ratio value of this first film electric crystal.
19. active component array substrate as claimed in claim 18, wherein, this second membrane transistor has a second grid, one second channel layer, one second source electrode and second drain electrode, this second grid is to be electrically connected at this sweep trace, and this second source electrode is to be electrically connected at this data line, and this second drain electrode is to be electrically connected at this second pixel electrode.
20. active component array substrate as claimed in claim 11, wherein, this first pixel electrode and this second pixel electrode all have jagged slit.
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| TWI326493B (en) | 2006-12-15 | 2010-06-21 | Au Optronics Corp | Thin film transistor array substrate and pixel structure |
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| US20020113238A1 (en) * | 2001-02-19 | 2002-08-22 | Au Optronics Corp. | Thin-film transistor array structure |
| CN1573486A (en) * | 2003-06-10 | 2005-02-02 | 三星电子株式会社 | Liquid crystal display with multiple area and panel for the display |
| CN1622149A (en) * | 2003-11-25 | 2005-06-01 | 三洋电机株式会社 | Display |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020113238A1 (en) * | 2001-02-19 | 2002-08-22 | Au Optronics Corp. | Thin-film transistor array structure |
| CN1573486A (en) * | 2003-06-10 | 2005-02-02 | 三星电子株式会社 | Liquid crystal display with multiple area and panel for the display |
| CN1622149A (en) * | 2003-11-25 | 2005-06-01 | 三洋电机株式会社 | Display |
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