CN101387803A - Pixel array of LCD - Google Patents
Pixel array of LCD Download PDFInfo
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- CN101387803A CN101387803A CNA2008101711575A CN200810171157A CN101387803A CN 101387803 A CN101387803 A CN 101387803A CN A2008101711575 A CNA2008101711575 A CN A2008101711575A CN 200810171157 A CN200810171157 A CN 200810171157A CN 101387803 A CN101387803 A CN 101387803A
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Abstract
The invention discloses a pixel array of liquid crystal display devices, comprising M data lines, N scan lines and a plurality of pixel structures electrically connected with the data lines and the scan lines and arranged in an array, wherein each pixel structure comprises a switch component, at least one main pixel electrode, at least one pixel electrode, a first capacity coupling electrode pattern and a second coupling electrode pattern, the switch component is electrically connected with the first scan line and the first data line, at least one main pixel electrode and at least one pixel electrode are electrically connected with the switch component, the first and the second capacitor coupling electrode patterns are electrically connected with at least one main pixel electrode and are coupled with at least one pixel electrode in a capacitor type, the first capacitor coupling electrode pattern is adjacent to the first data line and the second capacitor coupling electrode pattern is adjacent to the second data line.
Description
Technical field
The invention relates to a kind of pel array of LCD, and particularly relevant for a kind of pel array that reduces the LCD of crosstalk effect.
Background technology
Along with showing being showing improvement or progress day by day of science and technology, people borrow the auxiliary of display device can make life convenient more, for asking light, the thin characteristic of display, so flat-panel screens (Flat Panel Display FPD) becomes present main flow.In many flat-panel screens, (Liquid Crystal Display LCD) has advantageous characteristic such as high spatial utilization ratio, low consumpting power, radiationless and low electromagnetic interference (EMI) to LCD, and therefore, LCD is very popular.
LCD is made of image element array substrates, colored optical filtering substrates and liquid crystal layer, and wherein pixel electrode on the image element array substrates and the voltage difference between the shared electrode on the colored optical filtering substrates can determine the arrangement mode of liquid crystal molecule of liquid crystal layer to carry out the demonstration of picture.In general, sweep trace on the image element array substrates and data line can mark off a plurality of dot structures that are arrayed, and pixel electrode then is configured in each dot structure.In addition, each dot structure also needs the deploy switch assembly, to drive the pixel electrode in this dot structure.
In theory, it is big to be healed in the area design ground of the pixel electrode in the dot structure, more can promote the aperture opening ratio (aperture ratio) of LCD.Yet, when pixel electrode and data line too near the time, (capacitance between pixel and data line Cpd) can become big to the stray capacitance between pixel electrode and the data line.Thus, in the switch module down periods, the voltage of pixel electrode can be subjected to the influence of the signal that data line transmits and so-called crosstalk effect (crosstalk) takes place, and then influences the display quality of LCD.
Summary of the invention
The invention provides a kind of pel array of LCD, the pel array of this LCD has the capacitive coupling electrode pattern to reduce the stray capacitance between pixel electrode and the data line.
The present invention provides a kind of pel array of LCD again, and it helps to reduce crosstalk effect.
For specifically describing content of the present invention, at this a kind of pel array of LCD is proposed, it comprises M bar data line, N bar sweep trace and electrically connects with data line and sweep trace and a plurality of dot structures of arrayed that wherein the relative both sides of each dot structure are respectively adjacent to one first data line and one second data line.Each dot structure comprises a switch module, at least one main pixel electrode, at least pixel electrode, one first capacitive coupling electrode pattern and one second a capacitive coupling electrode pattern.The switch module and first sweep trace and first data line electrically connect.At least one main pixel electrode and at least pixel electrode electrically connect with switch module respectively.The first/the second capacitive coupling electrode pattern and at least one main pixel electrode electrically connect and produce capacitive coupling with at least pixel electrode, the wherein contiguous first data line setting of the first capacitive coupling electrode pattern, and the contiguous second data line setting of the second capacitive coupling electrode pattern.
In one embodiment of this invention, the pel array of LCD more comprises one first common lines and one second common lines.The first/the second common lines is arranged at the below of at least one main pixel electrode and at least pixel electrode, and wherein first common lines and second common lines be arranged in parallel.In one embodiment, the pel array of LCD more comprises at least one first top electrode pattern and at least one second top electrode pattern.At least one first top electrode pattern setting between first common lines and at least one main pixel electrode and at least pixel electrode, and with at least one main pixel electrode and at least one of them electric connection of pixel electrode.At least one second top electrode pattern setting between second common lines and at least one main pixel electrode and at least pixel electrode, and with one of them electric connection of at least one main pixel electrode and at least pixel electrode.In one embodiment, the second top electrode pattern is connected with the first capacitive coupling electrode pattern.
In one embodiment of this invention, switch module comprises the thin film transistor (TFT) of drain electrode more than.
In one embodiment of this invention, main pixel electrode and inferior pixel electrode have jagged edge.
In one embodiment of this invention, main pixel electrode comprises one first pixel electrode and one second pixel electrode, and inferior pixel electrode is between first pixel electrode and second pixel electrode.
For specifically describing content of the present invention, at this a kind of pel array of LCD is proposed again, it comprises M bar data line, N bar sweep trace and electrically connects with data line and sweep trace and many groups dot structure of arrayed, and the relative both sides of each dot structure are respectively adjacent to one first data line and one second data line, and wherein each group dot structure comprises first dot structure and second dot structure.First dot structure comprises one first switch module, at least one first main pixel electrode, at least one first time pixel electrode, one first capacitive coupling electrode pattern and one second capacitive coupling electrode pattern.Second dot structure comprises a second switch assembly, at least one second main pixel electrode, at least one second time pixel electrode, one the 3rd capacitive coupling electrode pattern and one the 4th capacitive coupling electrode pattern.First switch module and first sweep trace and first data line electrically connect.At least one first main pixel electrode and at least one first time pixel electrode and first switch module electrically connect.The first/the second capacitive coupling electrode pattern and at least one first main pixel electrode electrically connect and with at least one first time pixel electrode produce capacitive coupling, the wherein contiguous first data line setting of the first capacitive coupling electrode pattern, and the contiguous second data line setting of the second capacitive coupling electrode pattern.Second switch assembly and second sweep trace electrically connect, and with one of them electric connection of first data line and second data line.At least one second main pixel electrode and at least one second time pixel electrode and the second switch assembly electrically connect.The the 3rd/the 4th capacitive coupling electrode pattern and at least one second main pixel electrode electrically connect and with at least one second time pixel electrode produce capacitive coupling, the wherein contiguous first data line setting of the 3rd capacitive coupling electrode pattern, and the contiguous second data line setting of the 4th capacitive coupling electrode pattern.
In one embodiment of this invention, the position at the position at the first switch module place and second switch assembly place is in alignment with each other.In one embodiment, first switch module and second switch assembly lay respectively at the corner regions of place dot structure.
In one embodiment of this invention, in the corner regions of place dot structure, first switch module and second switch assembly all electrically connect with first data line.
In one embodiment of this invention, in the corner regions of place dot structure, first switch module and first data line electrically connect, and the second switch assembly and second data line electrically connect.In one embodiment, the pel array of LCD more comprises a compensating line, and this compensating line and first switch module are electrically insulated, and extends to second data line and electrically connect with second data line from first switch module.
In one embodiment of this invention, the position at the position at the first switch module place and second switch assembly place is in alignment with each other.In one embodiment, first switch module lays respectively at the zone line that the place dot structure is close to a side of corresponding sweep trace with the second switch assembly.
In one embodiment of this invention, the pel array of LCD more comprises one first compensating line and one second compensating line.First compensating line and first switch module are electrically insulated, and extend to second data line and electrically connect with second data line from first switch module.Second compensating line and second switch assembly are electrically insulated, and extend to first data line and electrically connect with first data line from the second switch assembly.
In one embodiment of this invention, the position at the position at the first switch module place and second switch assembly place is interlaced with each other.
In one embodiment of this invention, the pel array of LCD more comprises one first common lines, one second common lines, one the 3rd common lines and one the 4th common lines.The first/the second common lines is arranged at the below of at least one first master/time pixel electrode, and wherein first common lines and second common lines be arranged in parallel.The the 3rd/the 4th common lines is arranged at the below of at least one second master/time pixel electrode, and wherein the 3rd common lines and the 4th common lines be arranged in parallel.
In one embodiment of this invention, the pel array of LCD more comprises at least one first top electrode pattern, at least one second top electrode pattern, at least one the 3rd top electrode pattern and at least one the 4th top electrode pattern.The first top electrode pattern setting between first common lines and at least one first main pixel electrode and at least one first time pixel electrode, and with at least one first one of them electric connection of master/time pixel electrode.The second top electrode pattern setting between second common lines and at least one first main pixel electrode and at least one first time pixel electrode, and with at least one first main pixel electrode and at least one first time pixel electrode one of them electric connection.The 3rd top electrode pattern setting between the 3rd common lines and at least one second main pixel electrode and at least one second time pixel electrode, and with at least one second one of them electric connection of master/time pixel electrode.The 4th top electrode pattern setting between the 4th common lines and at least one second main pixel electrode and at least one second time pixel electrode, and with at least one second main pixel electrode and at least one second time pixel electrode one of them electric connection.In one embodiment, the second top electrode pattern is connected with the first capacitive coupling electrode pattern, and the 4th top electrode pattern is connected with the 3rd capacitive coupling electrode pattern.
In one embodiment of this invention, first switch module and second switch assembly are respectively many drain electrode thin film transistor (TFT)s.
In one embodiment of this invention, at least one first main pixel electrode, at least one first time pixel electrode, at least one second main pixel electrode and at least one second time pixel electrode all have jagged edge.
In one embodiment of this invention, at least one first main pixel electrode comprises one first pixel electrode and one second pixel electrode, and at least one first time pixel electrode between first pixel electrode and second pixel electrode.
In one embodiment of this invention, at least one second main pixel electrode comprises one the 3rd pixel electrode and one the 4th pixel electrode, and at least one second time pixel electrode between the 3rd pixel electrode and the 4th pixel electrode.
The pel array of LCD of the present invention has the capacitive coupling electrode pattern, to reduce the stray capacitance between pixel electrode and the data line.The pel array of LCD of the present invention is applied in the display, and then the cross-talk phenomenon of this display can be improved.
For above-mentioned feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail as follows.
Description of drawings
Fig. 1 is the partial top view of pel array of the LCD of embodiments of the invention;
Fig. 2 is the local schematic top plan view of pel array of the LCD of embodiments of the invention;
Fig. 3 is the local schematic top plan view of pel array of the LCD of embodiments of the invention;
Fig. 4 is the local schematic top plan view of pel array of the LCD of embodiments of the invention;
Fig. 5 is the local schematic top plan view of pel array of the LCD of embodiments of the invention.
Wherein, Reference numeral:
100,200,300,400,500: the pel array of LCD
130,230,330,430,530: dot structure
132: switch module 134M: main pixel electrode
134M
1, 234M
1: main pixel electrode (first pixel electrode)
134M
2, 234M
2: main pixel electrode (second pixel electrode)
134S: 136: the first capacitive coupling electrode patterns of inferior pixel electrode
142: the first common lines of 138: the second capacitive coupling electrode patterns
152,152a, 152b: 144: the second common lines of the first top electrode pattern
154: the second top electrode pattern 230a: first dot structure
230b: the second dot structure 232a: first switch module
232b: second switch assembly 234M
a: the first main pixel electrode
234M
b: the second main pixel electrode 234M
3: the 3rd pixel electrode
234M
4: the 4th pixel electrode 234S
a: pixel electrode for the first time
234S
b: 236: the three capacitive coupling electrode patterns of the pixel electrode second time
238: the four capacitive coupling electrode pattern CL: compensating line
CL1: the first compensating line CL2: second compensating line
D1, D2: drain D L1: first data line
DL2: the second data line DL1 ': first extension
DL2 ': the second extension DL ': extension
G: grid H1, H2, H3, H4, H5: contact hole
S: source S L1: first sweep trace
SL2: second sweep trace
Embodiment
Fig. 1 is the partial top view of pel array of the LCD of embodiments of the invention, and wherein Fig. 1 only illustrates a dot structure 130.Please refer to Fig. 1, the pel array 100 of the LCD of present embodiment comprises M bar data line (as DL1, DL2), N bar sweep trace (as SL1) and electrically connects with data line and sweep trace and a plurality of dot structures 130 of arrayed that wherein M and N for example are the integers more than or equal to 1.In addition, each dot structure 130 comprises a switch module 132, at least one main pixel electrode 134M, at least pixel electrode 134S, one first capacitive coupling electrode pattern 136 and one second a capacitive coupling electrode pattern 138.On the practice, the pel array 100 of LCD can be applicable in various types of LCD.For the effect of the LCD performance wide viewing angle that makes the pel array 100 with LCD, the main pixel electrode 134M of present embodiment and the edge of time pixel electrode 134S optionally further have little slit (fine slit) structure of zigzag (tooth-like).
Need to prove that at this in the present invention, main pixel electrode 134M can be one or more with the quantity of time pixel electrode 134S.In following embodiment, mainly be to be that example describes with time pixel electrode 134S with main pixel electrode 134M, wherein main pixel electrode 134M comprises main pixel electrode 134M
1With main pixel electrode 134M
2Two parts (it can be described as first pixel electrode and second pixel electrode again), so it is not in order to limit the present invention.
As shown in Figure 1, the switch module 132 and the first sweep trace SL1 and the first data line DL1 electrically connect, and main pixel electrode 134M
1And inferior pixel electrode 134S and switch module 132 electric connections, another main pixel electrode 134M
2By contact hole H3, H4 and capacitive coupling electrode pattern 138 (will be specified in the back) with main pixel electrode 134M
1Electrically connect.More specifically, the sharp switch module 132 of this enforcement for example is the thin film transistor (TFT) of drain electrode more than, and wherein switch module 132 has grid G, source S and drain D 1, D2.In detail, in the present embodiment, the first sweep trace SL1 electrically connects in order to the transmission sweep signal and by grid G and switch module 132, and the first data line DL1 electrically connects in order to data signal and by source S and switch module 132.Main pixel electrode 134M
1Be electrically connected to the drain D 1 and the drain D 2 of switch module 132 and main pixel electrode 134M respectively with inferior pixel electrode 134S
1, 134M
2Be electrically insulated with inferior pixel electrode 134S.From the above, single dot structure 130 can pass through main pixel electrode 134M
1, 134M
2With the configuration of inferior pixel electrode 134S and be divided into different voltage regime, this measure helps to improve colour cast.
For the LCD that makes the pel array 100 with LCD is kept superior display quality, the pel array 100 of the LCD of present embodiment can further comprise one first common lines 142, one second common lines 144, at least one first top electrode pattern 152 and at least one second top electrode pattern 154.In the present embodiment, the first top electrode pattern 152 comprises the first top electrode pattern 152a, 152b.Wherein, the first top electrode pattern 152a, 152b respectively with main pixel electrode 134M
1And time pixel electrode 134S electrically connects.And the second top electrode pattern 154 can reach one of them electric connection of at least pixel electrode with at least one main pixel electrode, and in the present embodiment, the second top electrode pattern 154 is and main pixel electrode 134M
2Electrically connect.
Hold above-mentioned, in the present embodiment, the first top electrode pattern 152 can form a plurality of reservior capacitors with 144 couplings of second common lines with 142 couplings of first common lines and the second top electrode pattern 154, to keep the voltage of main pixel electrode 134M and time pixel electrode 134S.Need to prove at this, in the present embodiment, the first top electrode pattern 152 can with the 142 corresponding configurations of first common lines and to press from both sides the reservior capacitor that establish the dielectric layer of an insulativity and constitute be metal-insulator-metal (Metal-Insulator-Metal, framework MIM).Yet the reservior capacitor in the pel array 100 of LCD of the present invention also can adopt metal-insulator-indium tin oxide, and (Metal-Insulator-ITO, framework MII) for example save the first top electrode pattern 152, and utilize main pixel electrode 134M
1Form storage capacitors with inferior pixel electrode 134S with first common lines 142.In other words, the disclosed first top electrode pattern 152 of present embodiment is selectivity member (optional element).In like manner can know by inference, the second top electrode pattern 154 also is the selectivity member.Next, present embodiment can further specify first, second top electrode pattern 154,154 and first, second common lines 142,144 again.
In the present embodiment, first common lines 142 and second common lines 144 are arranged at the below of main pixel electrode 134M and inferior pixel electrode 134S, and wherein first common lines 142 and second common lines 144 are parallel to the sweep trace setting in fact.
In detail, in the present embodiment, first common lines 142 and second common lines 144 for example are two common lines independent of each other, therefore, and each pixel electrode (main pixel electrode 134M
1, main pixel electrode 134M
2With inferior pixel electrode 134S) and different common lines (first common lines 142 and second common lines 144) between capacitance coupling effect also can be different thereupon.So, different pixels electrode (the main pixel electrode 134M in the same dot structure 130
1, main pixel electrode 134M
2And the phenomenon that unusual short circuit takes place inferior pixel electrode 134S) just can be detected in the array test stage.
In the present embodiment, the first top electrode pattern 152 is arranged at first common lines 142 and main pixel electrode 134M
1Reach between time pixel electrode 134S, wherein the first top electrode pattern 152a and main pixel electrode 134M
1Electrically connect, and the first top electrode pattern 152b electrically connects with time pixel electrode 134S.On the other hand, the second top electrode pattern 154 is arranged at second common lines 144 and main pixel electrode 134M
2And between time pixel electrode 134S, and with main pixel electrode 134M
2Electrically connect.Say that further the first top electrode pattern 152a for example is by contact hole H1 and main pixel electrode 134M
1Electrically connect, and another first top electrode pattern 152b electrically connects by contact hole H2 and time pixel electrode 134S.In addition, the second top electrode pattern 154 for example is by contact hole H3 and main pixel electrode 134M
2Electrically connect.
In other embodiments, be arranged at second common lines 144 and main pixel electrode 134M
2And the second top electrode pattern 154 between time pixel electrode 134S also can electrically connect with inferior pixel electrode 134S.But in the present embodiment, the second top electrode pattern 154 is and main pixel electrode 134M
2Electrically connect.
In the present embodiment, the first capacitive coupling electrode pattern 136 and the second capacitive coupling electrode pattern 138 electrically connect with main pixel electrode 134M, and produce capacitive coupling with inferior pixel electrode 134S.The first capacitive coupling electrode pattern 136 and the second capacitive coupling electrode pattern 138 that it should be noted that present embodiment are played the part of crucial role in dot structure 130.Particularly, the first capacitive coupling electrode pattern 136 and the second capacitive coupling electrode pattern 138 can effectively reduce the stray capacitance between time pixel electrode 134S and the data line (as DL1, DL2), after its detailed mechanism is specified in.
In the present embodiment, data line DL1, DL2, first, second capacitive coupling electrode pattern 136,138 and first, second top electrode pattern 152,154 for example are to belong to same rete to define and form, and wherein the second top electrode pattern 154 can be connected with the first capacitive coupling electrode pattern 136.As shown in Figure 1, the first capacitive coupling electrode pattern 136 that is close to the first data line DL1 for example is respectively by contact hole H4, contact hole H3 and main pixel electrode 134M
1, main pixel electrode 134M
2Electrically connect, and the second capacitive coupling electrode pattern 138 of the contiguous second data line DL2 for example is by contact hole H5 and main pixel electrode 134M
2Electrically connect.
Hold above-mentionedly, the first capacitive coupling electrode pattern 136 and the second capacitive coupling electrode pattern 138 are electrically insulated with time pixel electrode 134S.Yet, part first capacitive coupling electrode pattern 136 and the part second capacitive coupling electrode pattern 138 overlap with time pixel electrode 134S, and make the first capacitive coupling electrode pattern 136 and the second capacitive coupling electrode pattern 138 can influence the voltage of time pixel electrode 134S by capacitance coupling effect.Therefore, can reduce coupling capacitance between time pixel electrode 134S and the first data line DL1 by the first capacitive coupling electrode pattern 136, and the second capacitive coupling electrode pattern 138 can reduce the coupling capacitance between time pixel electrode 134S and the second data line DL2, can help balance time pixel electrode 134S with first contiguous data line DL1 and the stray capacitance between the second data line DL2.And the relative both sides that the first capacitive coupling electrode pattern 136 and second capacitive coupling electrode 138 are separately positioned on the contiguous first data line DL1 of time pixel electrode 134S and the second data line DL2 can obtain better capacitance balancing effect.
By the foregoing description as can be known, the function of each member in each dot structure and the configuration relation between each member.And following examples are that two dot structures are considered as one group of dot structure, with the configuration relation of each member in each group dot structure of further discussion.In other words, in following examples, composition member in each dot structure and the embodiment of Fig. 1 are roughly the same, and following examples are to be that the assembly layout that can do under one group the structure situation changes with two dot structures.
Fig. 2 is the local schematic top plan view of pel array of the LCD of embodiments of the invention, and wherein Fig. 2 only illustrates one group of dot structure 230.Please refer to Fig. 2, the pel array 200 of the LCD of present embodiment comprises M bar data line (as DL1, DL2), N bar sweep trace (as SL1, SL2) and electrically connects with data line and sweep trace and many groups dot structure 230 of arrayed that wherein M and N for example are the integers more than or equal to 1.
In the present embodiment, one group of dot structure 230 comprises one first dot structure 230a and one second dot structure 230b.The first dot structure 230a comprises one first switch module 232a, at least one first main pixel electrode 234M
a, at least one first time pixel electrode 234S
a, one first capacitive coupling electrode pattern 136 and one second capacitive coupling electrode pattern 138, the wherein first main pixel electrode 234M
aComprise main pixel electrode 234M
1With main pixel electrode 234M
2Two parts (main pixel electrode 234M
1With main pixel electrode 234M
2Can be described as the first pixel electrode 234M again
1With the second pixel electrode 234M
2).The second dot structure 230b comprises a second switch assembly 232b, at least one second main pixel electrode 234M
b, at least one second time pixel electrode 234S
b, one the 3rd capacitive coupling electrode pattern 236 and one the 4th capacitive coupling electrode pattern 238, the wherein second main pixel electrode 234M
bComprise main pixel electrode 234M
3With a main pixel electrode 234M
4Two parts (main pixel electrode 234M
3With main pixel electrode 234M
4Can be described as the 3rd pixel electrode 234M again
3With the 4th pixel electrode 234M
4).
What deserves to be mentioned is, in the present embodiment, the first switch module 232a and second switch assembly 232b are electrically connected to same data line, wherein the position at the position at the first switch module 232a place and second switch assembly 232b place is in alignment with each other, and the first switch module 232a and second switch assembly 232b are positioned at the corner regions of place dot structure.Specifically, in the present embodiment, the first switch module 232a and the first sweep trace SL1 and the first data line DL1 electrically connect, and the second switch assembly 232b and the second sweep trace SL2 and the first data line DL1 electrically connect, and the first switch module 232a and second switch assembly 232b are configured in the corner regions of the first dot structure 230a and the second dot structure 230b respectively in the mode of being close to the first data line DL1.
On the practice, the pel array 200 of the LCD of present embodiment can be applicable in various types of LCD.For the effect of the LCD performance wide viewing angle that makes pel array 200, the main pixel electrode 234M of first, second of present embodiment with LCD
a, 234M
bWith first, second time pixel electrode 234S
a, 234S
bCan further have jagged edge.In addition, make the LCD of the pel array 200 with LCD keep superior display quality, the pel array 200 of the LCD of present embodiment can further comprise one first common lines 142, one second common lines 144, one the 3rd common lines 242, one the 4th common lines 244.In addition, above first common lines 142, one second common lines 144, one the 3rd common lines 242, one the 4th common lines 244, more can further comprise respectively and dispose at least one first top electrode pattern, at least one second top electrode pattern, at least one the 3rd top electrode pattern and at least one the 4th top electrode pattern (not shown among Fig. 2, as to please refer to the setting of top electrode pattern shown in Figure 1 152,154).
Except the set-up mode of the described dot structure group of above-mentioned Fig. 2, the setting of other dot structure group can also be arranged, as shown in Figure 3.In Fig. 3, the pel array 300 of LCD is similar with the pel array 200 of the LCD of Fig. 2, but the two main difference part is: the first switch module 232a of the first dot structure 330a in the dot structure group 330 of present embodiment is electrically connected to different data lines respectively with the second switch assembly 232b of the second dot structure 330b.Further say, the position at the position at the first switch module 232a place and second switch assembly 232b place is in alignment with each other, and the first switch module 232a and second switch assembly 232b lay respectively at the corner regions of the first dot structure 330a and the second dot structure 330b.In addition, in this corner regions, the first switch module 232a and the first data line DL1 electrically connect, and the second switch assembly 232b and the second data line DL2 electrically connect.
As shown in Figure 3, in the second dot structure 330b, the second data line DL2 has an extension DL ' who is parallel to sweep trace.Therefore, second switch assembly 232b can electrically connect with the second data line DL2 by extension DL '.Yet, extension DL ' and the pixel electrode 234S second time
bBetween also capacitance coupling effect can take place.In order to reduce the otherness of the capacitance coupling effect between the first dot structure 330a and the second dot structure 330b, the pel array 300 of LCD is configuration one compensating line CL in the first dot structure 330a further.Wherein, compensating line CL can be electrically insulated with the first switch module 232a, and extends to the second data line DL2 with identical bearing of trend with sweep trace and electrically connect with the second data line DL2 from the first switch module 232a.
From the above, present embodiment not only possesses the advantage of first, second embodiment, and first, second dot structure 330a, 330b in each group dot structure 330 also can reduce the difference of capacitance coupling effect to each other by the configuration of compensating line CL.
In addition, according to another embodiment of the present invention, the design of dot structure group can also be as shown in Figure 4.In Fig. 4, the pel array 400 of LCD is similar with the pel array 300 of the LCD of Fig. 3, but the two main difference part is: the first switch module 232a in the dot structure group 430 and second switch assembly 232b lay respectively at the zone line that the first dot structure 430a and the second dot structure 430b are close to a side of corresponding sweep trace.
As shown in Figure 4, the first data line DL1 and the second data line DL2 have the first extension DL1 ' and the second extension DL2 ' that is parallel to sweep trace respectively.Therefore, the first switch module 232a can utilize the first extension DL1 ' and electrically connect with the first data line DL1, and second switch assembly 232b can utilize the second extension DL2 ' and electrically connect with the second data line DL2.Yet the first extension DL1 ' can the while and the first primary and secondary pixel electrode 234M
a, 234S
aProduce capacitive coupling, and the second extension DL2 ' only can with the pixel electrode 234S second time
bProduce capacitive coupling.In order to reduce the otherness of the capacitance coupling effect between the first dot structure 430a and the second dot structure 430b, the pel array 400 of LCD is configuration one first compensating line CL1 in the first dot structure 430a further, and disposes one second compensating line CL2 in the second dot structure 430b.Wherein, the first compensating line CL1 and the first switch module 232a are electrically insulated, and extend to the second data line DL2 with identical bearing of trend with sweep trace and electrically connect with the second data line DL2 from the first switch module 232a; The second compensating line CL2 and second switch assembly 232b are electrically insulated, and extend to the first data line DL1 with identical bearing of trend with sweep trace and electrically connect with the first data line DL1 from second switch assembly 232b.
According to further embodiment of this invention, the design of dot structure group can also be as shown in Figure 5.In Fig. 5, the pel array 500 of LCD is similar with the pel array 400 of the LCD of Fig. 4, but the two main difference part is: the position at the second switch assembly 232b place of the position at the first switch module 232a place of the first dot structure 530a in the dot structure group 530 and the second dot structure 530b is interlaced with each other.In more detail, the first switch module 232a and the first data line DL1 electrically connect, and second switch assembly 232b and the second data line DL2 electrically connect, and wherein the first switch module 232a corner regions that is positioned at the first dot structure 530a can present arrangement mode interlaced with each other with the corner regions that second switch assembly 232b is positioned at the second dot structure 530b.
In the present embodiment, because the first switch module 232a is adjacent to the first data line DL1 and second switch assembly 232b is adjacent to the second data line DL2, therefore, the capacitive coupling of the first dot structure 530a and the second dot structure 530b does not have too big-difference.Yet the deviser also demand of visual product is provided with compensating line in the first dot structure 530a and the second dot structure 530b, but not as limit.
In other embodiments, when the position at the first switch module 232a place is can be with the position at second switch assembly 232b place interlaced with each other, the first switch module 232a and second switch assembly 232b can be electrically connected to same data line, for example the first data line DL1.Certainly, also optionally compensating line is set in position, to compensate the capacity coupled difference of the first dot structure 530a and the second dot structure 530b.
In sum, in the pel array of LCD of the present invention every group or each dot structure are divided into different voltage regime by main pixel electrode with time pixel electrode, the first capacitive coupling pattern electrode pattern that wherein is positioned at time pixel electrode both sides proximity data line and the second capacitive coupling pattern electrode pattern help the stray capacitance between inferior pixel electrode of balance and proximity data line, and better capacitance balancing effect is arranged.Dot structure of the present invention is applied in the LCD, and then the cross-talk phenomenon of this LCD can be improved.
Though the present invention with preferred embodiment openly as above; but it is not in order to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when can doing a little change and modification, so protection scope of the present invention is as the criterion when looking the accompanying Claim book person of defining.
Claims (23)
1. the pel array of a LCD, it is characterized in that, it comprises M bar data line, N bar sweep trace and electrically connects with those data lines and those sweep traces and a plurality of dot structures of arrayed, wherein the relative both sides of each dot structure are respectively adjacent to one first data line and one second data line, and each dot structure comprises:
One switch module electrically connects with one first sweep trace and this first data line;
At least one main pixel electrode and at least pixel electrode electrically connect with this switch module respectively;
One first capacitive coupling electrode pattern, it electrically connects with this at least one main pixel electrode and produces capacitive coupling with this at least pixel electrode, wherein contiguous this first data line setting of this first capacitive coupling electrode pattern; And
One second capacitive coupling electrode pattern, it electrically connects with this at least one main pixel electrode and produces capacitive coupling with this at least pixel electrode, the wherein contiguous second data line setting of this second capacitive coupling electrode pattern.
2. the pel array of LCD as claimed in claim 1 is characterized in that, also comprises:
One first common lines is arranged at the below of this at least one main pixel electrode and this at least pixel electrode; And
One second common lines is arranged at the below of this at least one main pixel electrode and this at least pixel electrode, and wherein this first common lines and this second common lines be arranged in parallel.
3. the pel array of LCD as claimed in claim 2 is characterized in that, also comprises:
At least one first top electrode pattern is arranged between this first common lines and this at least one main pixel electrode and this pixel electrode at least, and with this at least one main pixel electrode and this one of them electric connection of at least pixel electrode; And
At least one second top electrode pattern is arranged between this second common lines and this at least one main pixel electrode and this pixel electrode at least, and with one of them electric connection of this at least one main pixel electrode and this at least pixel electrode.
4. the pel array of LCD as claimed in claim 3 is characterized in that, this second top electrode pattern is connected with this first capacitive coupling electrode pattern.
5. the pel array of LCD as claimed in claim 1 is characterized in that, this switch module comprises the thin film transistor (TFT) of drain electrode more than.
6. the pel array of LCD as claimed in claim 1 is characterized in that, this at least one main pixel electrode and this at least pixel electrode have jagged edge.
7. the pel array of LCD as claimed in claim 1, it is characterized in that, this at least one main pixel electrode comprises one first pixel electrode and one second pixel electrode, and this at least pixel electrode is between this first pixel electrode and this second pixel electrode.
8. the pel array of a LCD, it is characterized in that, comprise M bar data line, N bar sweep trace and electrically connect with those data lines and those sweep traces and many groups dot structure of arrayed, wherein each relative both sides of group dot structure is respectively adjacent to one first data line and one second data line, and each group dot structure comprises:
One first dot structure, it comprises:
One first switch module, itself and one first sweep trace electrically connect, and electrically connect with this first data line;
At least one first main pixel electrode and at least one first time pixel electrode, itself and this first switch module electrically connects;
One first capacitive coupling electrode pattern, its electrically connect with should at least one first main pixel electrode and with this at least one first time pixel electrode produce capacitive coupling, wherein this first capacitive coupling electrode pattern is close to this first data line setting; And
One second capacitive coupling electrode pattern, its electrically connect with should at least one first main pixel electrode and with this at least one first time pixel electrode produce capacitive coupling, wherein this second capacitive coupling electrode pattern is close to this second data line setting;
One second dot structure, it comprises:
One second switch assembly, itself and one second sweep trace electrically connect, and with one of them electric connection of this first data line and this second data line;
At least one second main pixel electrode and at least one second time pixel electrode, itself and this second switch assembly electrically connects;
One the 3rd capacitive coupling electrode pattern, its electrically connect with should at least one second main pixel electrode and with this at least one second time pixel electrode produce capacitive coupling, wherein the 3rd capacitive coupling electrode pattern is close to this first data line setting; And
One the 4th capacitive coupling electrode pattern, its electrically connect with should at least one second main pixel electrode and with this at least one second time pixel electrode produce capacitive coupling, wherein the 4th capacitive coupling electrode pattern is close to this second data line setting.
9. the pel array of LCD as claimed in claim 8 is characterized in that, the position at the position at this first switch module place and this second switch assembly place is in alignment with each other.
10. the pel array of LCD as claimed in claim 9 is characterized in that, this first switch module and this second switch assembly lay respectively at the corner regions of place dot structure.
11. the pel array of LCD as claimed in claim 10 is characterized in that, this first switch module of corner regions and this second switch assembly that are positioned at the place dot structure all electrically connect with this first data line.
12. the pel array of LCD as claimed in claim 10 is characterized in that, this first switch module of corner regions and this first data line that are positioned at the place dot structure electrically connect, and this second switch assembly and the electric connection of this second data line.
13. the pel array of LCD as claimed in claim 12 is characterized in that, also comprises a compensating line, itself and this first switch module is electrically insulated, and this first switch module extends to this second data line and electrically connects with this second data line certainly.
14. the pel array of LCD as claimed in claim 9 is characterized in that, this first switch module lays respectively at the zone line that the place dot structure is close to a side of corresponding sweep trace with this second switch assembly.
15. the pel array of LCD as claimed in claim 14 is characterized in that, also comprises:
One first compensating line, itself and this first switch module is electrically insulated, and this first switch module extends to this second data line and electrically connects with this second data line certainly;
One second compensating line, itself and this second switch assembly is electrically insulated, and this second switch assembly extends to this first data line and electrically connects with this first data line certainly.
16. the pel array of LCD as claimed in claim 8 is characterized in that, the position at the position at this first switch module place and this second switch assembly place is interlaced with each other.
17. the pel array of LCD as claimed in claim 8 is characterized in that, also comprises:
One first common lines is arranged at the below of this at least one first main pixel electrode and this at least one first time of pixel electrode;
One second common lines is arranged at the below of this at least one first main pixel electrode and this at least one first time of pixel electrode, and wherein this first common lines and this second common lines be arranged in parallel;
One the 3rd common lines is arranged at the below of this at least one second main pixel electrode and this at least one second time of pixel electrode; And
One the 4th common lines is arranged at the below of this at least one second main pixel electrode and this at least one second time of pixel electrode, and wherein the 3rd common lines and the 4th common lines be arranged in parallel.
18. the pel array of LCD as claimed in claim 17 is characterized in that, also comprises:
At least one first top electrode pattern, be arranged at this first common lines and this at least one first main pixel electrode and should be at least one between the first time pixel electrode, and reach this at least one one of them electric connection of pixel electrode first time with this at least one first main pixel electrode;
At least one second top electrode pattern, be arranged between this second common lines and this at least one first main pixel electrode and this at least one first time of pixel electrode, and with one of them electric connection of this at least one first main pixel electrode and this at least one first time of pixel electrode;
At least one the 3rd top electrode pattern, be arranged at the 3rd common lines and this at least one second main pixel electrode and should be at least one between the second time pixel electrode, and reach this at least one one of them electric connection of pixel electrode second time with this at least one second main pixel electrode; And
At least one the 4th top electrode pattern, be arranged between the 4th common lines and this at least one second main pixel electrode and this at least one second time of pixel electrode, and with one of them electric connection of this at least one second main pixel electrode and this at least one second time of pixel electrode.
19. the pel array of LCD as claimed in claim 18 is characterized in that, this second top electrode pattern is connected with this first capacitive coupling electrode pattern, and the 4th top electrode pattern is connected with the 3rd capacitive coupling electrode pattern.
20. the pel array of LCD as claimed in claim 8 is characterized in that, this first switch module and this second switch assembly are respectively many drain electrode thin film transistor (TFT)s.
21. the pel array of LCD as claimed in claim 8, it is characterized in that this at least one first main pixel electrode, this pixel electrode, this at least one second main pixel electrode, this, pixel electrode all had jagged edge at least one first time at least one second time.
22. the pel array of LCD as claimed in claim 8, it is characterized in that, this at least one first main pixel electrode comprises one first pixel electrode and one second pixel electrode, and this at least one first time pixel electrode between this first pixel electrode and this second pixel electrode.
23. the pel array of LCD as claimed in claim 8, it is characterized in that, this at least one second main pixel electrode comprises one the 3rd pixel electrode and one the 4th pixel electrode, and this at least one second time pixel electrode between the 3rd pixel electrode and the 4th pixel electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2008101711575A CN100573293C (en) | 2008-10-22 | 2008-10-22 | The pel array of LCD |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2008101711575A CN100573293C (en) | 2008-10-22 | 2008-10-22 | The pel array of LCD |
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| Publication Number | Publication Date |
|---|---|
| CN101387803A true CN101387803A (en) | 2009-03-18 |
| CN100573293C CN100573293C (en) | 2009-12-23 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2008101711575A Active CN100573293C (en) | 2008-10-22 | 2008-10-22 | The pel array of LCD |
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| CN (1) | CN100573293C (en) |
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| CN102231025A (en) * | 2011-08-04 | 2011-11-02 | 南京中电熊猫液晶显示科技有限公司 | Multi-domain vertically-aligned liquid crystal display panel and pixel structure thereof |
| US8139191B2 (en) | 2008-10-16 | 2012-03-20 | Chunghwa Picture Tubes, Ltd. | Pixel array structure |
| CN101713893B (en) * | 2009-10-26 | 2012-07-04 | 华映光电股份有限公司 | Pixel array |
| CN102566177A (en) * | 2011-11-18 | 2012-07-11 | 友达光电股份有限公司 | Display panel, pixel structure in display panel and driving method in display panel |
| CN101923259B (en) * | 2009-06-11 | 2012-11-28 | 华映视讯（吴江）有限公司 | Pixel array structure |
| WO2013053144A1 (en) * | 2011-10-12 | 2013-04-18 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and pixel electrode thereof |
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| US8139191B2 (en) | 2008-10-16 | 2012-03-20 | Chunghwa Picture Tubes, Ltd. | Pixel array structure |
| CN101923259B (en) * | 2009-06-11 | 2012-11-28 | 华映视讯（吴江）有限公司 | Pixel array structure |
| CN101713893B (en) * | 2009-10-26 | 2012-07-04 | 华映光电股份有限公司 | Pixel array |
| CN105137686A (en) * | 2011-04-13 | 2015-12-09 | 友达光电股份有限公司 | Pixel array, pixel structure and driving method of pixel structure |
| CN105137686B (en) * | 2011-04-13 | 2017-11-10 | 友达光电股份有限公司 | Pixel array, pixel structure and driving method of pixel structure |
| CN102231025A (en) * | 2011-08-04 | 2011-11-02 | 南京中电熊猫液晶显示科技有限公司 | Multi-domain vertically-aligned liquid crystal display panel and pixel structure thereof |
| WO2013053144A1 (en) * | 2011-10-12 | 2013-04-18 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and pixel electrode thereof |
| US8854584B2 (en) | 2011-10-12 | 2014-10-07 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Liquid crystal display panel and pixel electrode thereof |
| CN102566177B (en) * | 2011-11-18 | 2014-08-06 | 友达光电股份有限公司 | Display panel, pixel unit in display panel and driving method in display panel |
| CN102566177A (en) * | 2011-11-18 | 2012-07-11 | 友达光电股份有限公司 | Display panel, pixel structure in display panel and driving method in display panel |
| CN107015403A (en) * | 2017-04-05 | 2017-08-04 | 深圳市华星光电技术有限公司 | Array base palte |
| WO2018184257A1 (en) * | 2017-04-05 | 2018-10-11 | 深圳市华星光电半导体显示技术有限公司 | Array substrate |
| CN107015403B (en) * | 2017-04-05 | 2019-05-31 | 深圳市华星光电半导体显示技术有限公司 | Array substrate |
| WO2021128612A1 (en) * | 2019-12-26 | 2021-07-01 | Tcl华星光电技术有限公司 | Pixel electrode and display panel |
| US11454850B2 (en) | 2019-12-26 | 2022-09-27 | Tcl China Star Optoelectronics Technology Co., Ltd. | Pixel electrode and display panel |
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