CN111381406A - Pixel unit, pixel array and liquid crystal panel thereof - Google Patents
Pixel unit, pixel array and liquid crystal panel thereof Download PDFInfo
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- CN111381406A CN111381406A CN201811639002.XA CN201811639002A CN111381406A CN 111381406 A CN111381406 A CN 111381406A CN 201811639002 A CN201811639002 A CN 201811639002A CN 111381406 A CN111381406 A CN 111381406A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136213—Storage capacitors associated with the pixel electrode
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
Abstract
The invention relates to a pixel unit, a pixel array and a liquid crystal panel thereof, wherein the pixel unit comprises a first switch, a second switch and a third switch, the first switch and the second switch are electrically connected with the same data line and the same scanning line, the third switch is connected with the second switch in parallel, and the third switch is electrically connected with the same scanning line; the main pixel electrode is electrically connected with the first switch; the sub-pixel electrode is electrically connected with the second switch and the third switch; the coupling electrode is electrically connected with the second switch and the third switch; the third switch is also electrically connected with the common line. According to the invention, the third switch is added, and the third switch and the second switch are connected in parallel, so that the charging and discharging speed of the second storage capacitor is improved, the charge release capacity of the second storage capacitor is enhanced, and the afterimage can be improved.
Description
Technical Field
The invention relates to the field of liquid crystal display screens, in particular to a pixel unit, a pixel array and a liquid crystal panel thereof.
Background
Liquid Crystal Displays (LCDs) have many advantages such as thin body, power saving, no radiation, and are widely used, for example: liquid crystal televisions, mobile phones, Personal Digital Assistants (PDAs), digital cameras, computer screens, notebook computer screens, or the like, are dominant in the field of flat panel displays.
Currently, a mainstream liquid crystal display panel is formed by bonding a Thin Film transistor Array (TFT Array Substrate) and a Color Filter (CF) Substrate, and liquid crystal is injected between the TFT Substrate and the CF Substrate. The liquid crystal molecules are controlled to change direction by electrifying or not, and the light rays of the backlight module are refracted out to generate a picture.
The CF substrate comprises a CF substrate and a plurality of pixel units, wherein one side of the CF substrate is provided with the pixel units which are arranged in an array mode, each pixel unit comprises a red sub-pixel, a green sub-pixel and a blue sub-pixel, and a Black Matrix (BM) is distributed on the periphery of each sub-pixel and used for shading light. The area size of the light blocking area corresponding to the three colors of red, green and blue on the CF substrate and the light blocking area corresponding to the black matrix directly affects the aperture ratio and contrast of the liquid crystal display, thereby affecting the overall display quality of the liquid crystal display. The aperture ratio is an important parameter of the liquid crystal display panel, and refers to the ratio of the effective light-transmitting area to the total area of the liquid crystal display panel. When light is emitted from the backlight module, not all light can pass through the liquid crystal display panel: for the TFT substrate, signal traces for the source driver chip and the gate driver chip of the liquid crystal display panel, and a storage capacitor for storing voltage are not completely transparent, and light passing through these places is not controlled by voltage, so that it is necessary to shield the TFT substrate by using a black matrix; for the CF substrate, the light-transmitting area is mainly the light-blocking area corresponding to the red, green and blue sub-pixels, and the black matrix is the light-blocking area, mainly used to prevent the color mixing of the red, green and blue light-blocking of each sub-pixel, so as to increase the contrast value of the panel.
In the liquid crystal display panel, a gate electrode of each TFT switch is connected to a scanning line in a horizontal direction, a source electrode is connected to a data line in a vertical direction, and a drain electrode is connected to a liquid crystal pixel electrode and a storage capacitor. The display screen activates only one gate scan line at a time to turn on the TFT switches of the corresponding row. The data lines in the vertical direction send corresponding video signals to charge the liquid crystal storage capacitor to proper voltage for displaying images of corresponding lines.
Due to the fact that anisotropy exists in the refractive indexes of liquid crystal molecules under different view angles, brightness difference of RGB pixels is caused, and color cast is formed finally. CC Type (capacitive Coupling technology) is a common 8-domain display design. As shown in fig. 1-2, a metal pixel electrode connected to an a-TFT switch is connected to an ITO floating electrode through a contact hole to form a Main pixel, a metal pixel electrode connected to a b-TFT switch is connected to the ITO floating electrode through a contact hole to form a Sub-pixel with a lower potential, a Main pixel forms a st-Main through a metal electrode, a Sub-pixel forms a st-Sub through a metal electrode, the voltage of the ITO floating electrode is related to the ratio of upper and lower capacitances, and the potential of the Sub-pixel is controlled by the b-TFT. In the design structure, the pixel array is provided with two metal electrodes, so that the aperture opening ratio of the pixels is reduced. Furthermore, the sub-pixels are influenced by the potential of the ITO suspension electrode, so that the charge release capacity is low, and afterimages are easy to appear.
Therefore, there is a need to provide a new and more effective solution to the color shift problem.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a pixel unit, a pixel array and a liquid crystal panel thereof. The technical problem to be solved by the invention is realized by the following technical scheme:
an embodiment of the present invention provides a pixel unit, including:
the first switch, the second switch and the same data line and the same scanning line are electrically connected, the third switch is connected with the second switch in parallel, and the third switch is electrically connected with the same scanning line;
the main pixel electrode is electrically connected with the first switch;
the sub-pixel electrode is electrically connected with the second switch and the third switch;
the coupling electrode is electrically connected with the second switch and the third switch;
the third switch is also electrically connected with the common line.
In a specific embodiment, the pixel unit further includes:
a first capacitor electrode constituting a first storage capacitor together with the main pixel electrode;
and the second capacitor electrode and the sub-pixel electrode form a second storage capacitor together.
In a specific embodiment, the pixel unit further includes:
one end of the main pixel coupling capacitor is electrically connected with the main pixel electrode, and the other end of the main pixel coupling capacitor is electrically connected with one of the common lines;
and one end of the sub-pixel coupling capacitor is electrically connected with the sub-pixel electrode, and the other end of the sub-pixel coupling capacitor is electrically connected with one of the common lines.
Another embodiment of the present invention further provides a pixel array, comprising
A plurality of scan lines;
the data lines are staggered with the scanning lines, and the scanning lines and the data lines define a plurality of pixel regions;
a plurality of pixel units as described in any one of the above, respectively disposed in the corresponding pixel regions, wherein any one of the pixel units is electrically connected to one of the scan lines and one of the data lines;
a plurality of common lines, wherein one common line is electrically connected with the third switch;
and one of the coupling lines and the coupling electrode form a coupling capacitor.
In a specific embodiment, the first switch is a first thin film transistor, a gate of the first thin film transistor is electrically connected to one of the scan lines, a source of the first thin film transistor is electrically connected to one of the data lines, and a drain of the first thin film transistor is electrically connected to the main pixel electrode.
In a specific embodiment, the second switch is a second thin film transistor, a gate of the second thin film transistor is electrically connected to one of the scan lines, a source of the second thin film transistor is electrically connected to one of the data lines, and a drain of the second thin film transistor is electrically connected to the third switch and the sub-pixel electrode.
In a specific embodiment, the third switch is a third thin film transistor, a gate of the third thin film transistor is electrically connected to one of the scan lines, a source of the third thin film transistor is electrically connected to one of the common lines, and a drain of the third thin film transistor is electrically connected to a drain of the second thin film transistor and the sub-pixel electrode.
In a specific embodiment, the coupling line is connected to a coupling driver, and the coupling driver is configured to control a driving timing of the coupling capacitor.
Another embodiment of the present invention further provides a liquid crystal panel including the pixel array according to any one of the above embodiments.
Compared with the prior art, the invention has the beneficial effects that:
1. the invention provides a pixel unit, which is characterized in that a first switch, a second switch and a third switch are arranged, and the third switch and the second switch are connected in parallel, so that the charging and discharging speed of a second storage capacitor is increased, the charge release capacity of the second storage capacitor is enhanced, and the afterimage can be improved.
2. The drive of the coupling electrode is controlled by the coupling line, the voltage of the coupling line is from an external free control end, namely the coupling electrode can be adjusted according to the design requirement, and the design space is increased.
3. The third switch and the second switch are connected in parallel to divide voltage, and the coupling capacitor connected with the connection node of the third switch and the second switch jointly controls the charging voltage of the second storage capacitor, so that the voltage adjustment of the sub-pixels is more flexible.
Drawings
FIG. 1 is a schematic diagram of a pixel array in the prior art;
FIG. 2 is a diagram of a driving circuit in the prior art;
fig. 3 is a schematic structural diagram of a pixel array according to an embodiment of the invention;
FIG. 4 is a schematic diagram of a driving circuit according to an embodiment of the present invention;
FIG. 5 is a V-T plot provided by an embodiment of the present invention.
Detailed Description
In the following description, numerous technical details are set forth in order to provide a better understanding of the present application. However, it will be understood by those skilled in the art that the technical solutions claimed in the present application may be implemented without these technical details and with various changes and modifications based on the following embodiments.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
As shown in fig. 3-4, fig. 3 is a schematic structural diagram of a pixel array according to an embodiment of the invention; FIG. 4 is a schematic diagram of a driving circuit according to an embodiment of the present invention; the pixel array of the embodiment includes a plurality of scanning lines 10(i) and a plurality of data lines 20(j) which are crossed and insulated, a pixel area is defined at the crossed position of the scanning lines 10(i) and the data lines 20(j), and a plurality of pixel units 30 are configured in the pixel area; the pixel array further includes a plurality of common lines 40(i) and a plurality of coupling lines 50(i), the pixel unit 30 is electrically connected to one of the scan lines 10(i), one of the data lines 20(j), one of the common lines 40(i) and one of the coupling lines 50(i), wherein i and j are natural numbers, and the plurality of common lines 40(i) can be connected to each other; the plurality of pixel units 30 are arranged in a plurality of rows, and the pixel units arranged in the same row are electrically connected to the same scanning line and the same coupling line, that is, the scanning line 10(i), the common line 40(i) and the coupling line 50(i) are respectively electrically connected to the pixel units 30 arranged in the ith row; further, the data line 20(j) is electrically connected to the pixel units 30 arranged in j rows, and the scan line 10(i), the common line 40(i) and the coupling line 50(i) are electrically insulated from each other.
In the present embodiment, the extension directions of the scan line 10(i), the common line 40(i) and the coupling line 50(i) are substantially parallel, and the extension direction of the data line 20(j) is perpendicular to the extension direction of the scan line 10 (i).
Further, as shown in fig. 3, the pixel unit includes a first switch a-TFT, a second switch b-TFT, a third switch c-TFT, a main pixel electrode, a sub-pixel electrode, and a coupling electrode, wherein the first switch a-TFT and the second switch b-TFT are electrically connected to the same data line and the same scan line; the first switch a-TFT is electrically connected with the main pixel electrode, the second switch b-TFT is electrically connected with the sub-pixel electrode, the third switch c-TFT and the second switch b-TFT are electrically connected with the sub-pixel electrode after being connected in parallel, a connecting node of the third switch c-TFT and the second switch b-TFT is also connected with a coupling electrode, the third switch c-TFT is also electrically connected with one common line TFT-Vcom, and the common line TFT-Vcom provides voltage for the third switch c-TFT.
Further, the first capacitor electrode and the main pixel electrode form a first storage capacitor, and the first switch a-TFT is used for charging the first storage capacitor; the second capacitor electrode and the sub-pixel electrode constitute a second storage capacitor, the sub-pixel electrode is connected to a connection node of the second switch b-TFT and the third switch c-TFT, and thus the second switch b-TFT and the third switch c-TFT are used together to charge the second storage capacitor; the coupling electrode and the coupling line form a coupling capacitor, the coupling electrode is electrically connected with a connection node of the second switch b-TFT and the third switch c-TFT, and therefore the second switch b-TFT and the third switch c-TFT are also used for charging the coupling capacitor.
In practical application, after the data lines are conducted, the scanning lines and the common line TFT-Vcom are conducted simultaneously; the driving process of the pixel unit at the intersection of the data line and the scan line at this time is as follows:
the first switch a-TFT is conducted to charge the first storage capacitor; the main pixel voltage is controlled by a data line and a scanning line;
the third switch c-TFT and the second switch b-TFT are conducted to charge the second storage capacitor and the coupling capacitor, the coupling capacitor is connected with the coupling line, the voltage of the coupling line is an external loading voltage and has no correlation with the voltage of the scanning line, so that the charging duration of the second storage capacitor and the coupling capacitor is influenced by the coupling line, namely the Sub-pixel voltage needs to be jointly determined by the data line data, the scanning line gate, the common line TFT-Vcom and the coupling line st-Sub; the design mode can meet the requirement of liquid crystal driving of the sub-pixel on one hand, and can avoid the charge and discharge speed of the sub-pixel liquid crystal from being reduced on the other hand.
Specifically, in the embodiment of the present invention, the principle of voltage division by the second switch b-TFT and the third switch c-TFT in parallel is as shown in formula 1 and fig. 5,
wherein, VSubIs the sub-pixel voltage, TgateIs the point in time at which the gate is closed, IdataIs a data current, CtotalIs the total capacitance of the pixel, IVcomIs a common line current, Δ Vst-SubIs the voltage difference of the coupled line, Cx is the coupling capacitance formed by st _ sub and CF-Vcom, Cst-SubIs a coupling capacitor formed by the coupling line and the sub-pixel, Clc-subLiquid crystal capacitor being a sub-pixel
As shown in fig. 5, the data line, the scan line and the common line provide a potential signal, at the nth frame time, the scan line provides a potential signal, the sub-pixel electrode starts to charge, as shown by the dotted line, the potential of the sub-pixel electrode drops from the point a to the point b due to the parallel action of the b-TFT and the c-TFT, when the scan line is closed, the potential of the sub-pixel electrode drops to the point c due to the effect of the feed-through voltage, and the potential state is maintained until the coupling capacitor is opened, and when the coupling capacitor is opened, the potential of the sub-pixel electrode rises to the point d and is maintained to the N +1 th frame due to the effect of the coupling capacitor.
And in the (N + 1) th frame, the data line provides a potential signal with the polarity opposite to that of the previous frame, due to the parallel action of the b-TFT and the c-TFT, when the Gate is opened, the pixel voltage is changed from the dotted line to the solid line, the voltage is reduced to the point e, when the scanning line is closed, the potential of the sub-pixel electrode is reduced to the point f under the influence of the feed-through voltage, the potential state is kept until the coupling capacitor is opened, and when the coupling capacitor is opened, the potential of the sub-pixel electrode is influenced by the coupling capacitor, the potential is increased to the point g and is kept to the next frame.
The b-TFT and the c-TFT are commonly used for charging the second storage capacitor, so that the charging speed is improved, and correspondingly, the discharging speed of the second storage capacitor is also improved when the charges are released.
The coupling capacitor is connected with the coupling line, the driving time sequence of the coupling capacitor can be freely designed according to needs, specifically, the electric potential loaded on the coupling line is controlled by the coupling driver, and the coupling driver is used for controlling the driving time sequence and the electric potential of the coupling capacitor. For example: when the electric potential loaded on the coupling line is higher than the electric potential of the scanning line, the coupling capacitor plays a role in pulling up the electric potential, the charging process of the second storage capacitor is prolonged, and when the electric potential loaded on the coupling line is lower than the electric potential provided by the scanning line, the coupling capacitor plays a role in pulling down the electric potential, and the charging process of the second storage capacitor is shortened;
correspondingly, when the electric charge is released, the electric potential loaded on the coupling line is higher than the electric potential of the scanning line, so that the discharging process is prolonged, and when the electric potential loaded on the coupling line is lower than the scanning line or the electric potential loaded on the coupling line is in an extremely low state, the electric charge releasing speed of the second storage capacitor can be increased, so that the reaction speed of the sub-pixel is increased, and the color cast problem is improved.
It should be noted that, the driving timing sequence of the coupling capacitor can be freely designed according to the requirement, and further includes that no voltage is loaded on the coupling line, that is, the coupling capacitor can be in a state of not adjusting the sub-pixel potential, further, the adjusting time of the coupling capacitor can be freely designed, and when the coupling capacitor works, and when the coupling capacitor does not work, the coupling driver controls the coupling capacitor; furthermore, the magnitude of the voltage difference of the coupling capacitor can be adjusted according to actual requirements, and the influence of the coupling capacitor on the sub-pixels can be positive or negative, namely, the charging and discharging speed of the second storage capacitor can be increased or decreased during working, and the design space of the coupling line is increased.
Furthermore, compared with the prior art, the embodiment of the invention only designs the coupling electrode on the sub-pixel, and the coupling electrode of the main pixel in the prior art is reduced, so that the aperture opening ratio of the pixel is improved.
Furthermore, the pixel unit also comprises a main pixel coupling capacitor and a sub-pixel coupling capacitor, wherein one end of the main pixel coupling capacitor is electrically connected with the first switch a-TFT, and the other end of the main pixel coupling capacitor is electrically connected with the common line; one end of the sub-pixel coupling capacitor is electrically connected with the second switch b-TFT and the third switch c-TFT, and the other end of the sub-pixel coupling capacitor is electrically connected with the common line. The main pixel coupling capacitor and the sub-pixel coupling capacitor are the inevitable result of the first storage capacitor and the second storage capacitor in the charging process, but the main pixel coupling capacitor and the sub-pixel coupling capacitor are connected with the common line, and the common line provides a stable voltage, so that the voltage drift of the main pixel coupling capacitor and the sub-pixel coupling capacitor is small, and the voltage stabilizing effect can be achieved. In a preferred embodiment, the first switch a-TFT is a first thin film transistor having a gate electrode connected to the scan line, a source electrode connected to the data line, and a drain electrode connected to the main pixel electrode; the second switch b-TFT is a second thin film transistor and is provided with a grid electrode connected with the scanning line, a source electrode connected with the data line and a drain electrode connected with the third switch c-TFT, the coupling electrode and the sub-pixel electrode; the third switch c-TFT is a third thin film transistor having a gate electrode connected to the scan line, a source electrode connected to the common line, and a drain electrode connected to the drain electrode of the second thin film transistor and the subpixel electrode.
It should be noted that, in this embodiment, the pixel unit includes a main pixel region and a sub-pixel region, the main pixel electrode and the plurality of groups of first slits define a first display region, the sub-pixel electrode and the plurality of groups of second slits define a second display region, and the plurality of first display regions and the plurality of second display regions enable the pixel unit to have a wide viewing angle characteristic. As shown in fig. 3, the main pixel region has four first display regions, and the sub-pixel region has four second display regions, so that one pixel unit has 8 display regions, which can improve the color shift problem.
The embodiment of the invention also provides a liquid crystal panel which comprises the pixel array provided by the embodiment, and the liquid crystal panel using the pixel array can better improve the problems of color cast and image retention and has better visual experience.
It is noted that, in this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the use of the verb "comprise a" to define an element does not exclude the presence of another, same element in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that a certain action is executed according to a certain element, it means that the action is executed according to at least the element, and two cases are included: performing the action based only on the element, and performing the action based on the element and other elements.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (9)
1. A pixel cell, comprising:
the first switch, the second switch and the same data line and the same scanning line are electrically connected, the third switch is connected with the second switch in parallel, and the third switch is electrically connected with the same scanning line;
the main pixel electrode is electrically connected with the first switch;
the sub-pixel electrode is electrically connected with the second switch and the third switch;
the coupling electrode is electrically connected with the second switch and the third switch;
the third switch is also electrically connected with the common line.
2. The pixel cell of claim 1, further comprising:
a first capacitor electrode constituting a first storage capacitor together with the main pixel electrode;
and the second capacitor electrode and the sub-pixel electrode form a second storage capacitor together.
3. The pixel cell of claim 2, further comprising:
one end of the main pixel coupling capacitor is electrically connected with the main pixel electrode, and the other end of the main pixel coupling capacitor is electrically connected with one of the common lines;
and one end of the sub-pixel coupling capacitor is electrically connected with the sub-pixel electrode, and the other end of the sub-pixel coupling capacitor is electrically connected with one of the common lines.
4. A pixel array, comprising
A plurality of scan lines;
the data lines are staggered with the scanning lines, and the scanning lines and the data lines define a plurality of pixel regions;
a plurality of pixel units according to any one of claims 1-3, respectively disposed in the corresponding pixel regions, wherein any one of the pixel units is electrically connected to one of the scan lines and one of the data lines;
a plurality of common lines, wherein one common line is electrically connected with the third switch;
and one of the coupling lines and the coupling electrode form a coupling capacitor.
5. The pixel array of claim 4, wherein the first switch is a first thin film transistor, a gate of the first thin film transistor is electrically connected to one of the scan lines, a source of the first thin film transistor is electrically connected to one of the data lines, and a drain of the first thin film transistor is electrically connected to the main pixel electrode.
6. The pixel array of claim 5, wherein the second switch is a second thin film transistor, a gate of the second thin film transistor is electrically connected to one of the scan lines, a source of the second thin film transistor is electrically connected to one of the data lines, and a drain of the second thin film transistor is electrically connected to the third switch and the sub-pixel electrode.
7. The pixel array of claim 6, wherein the third switch is a third thin film transistor, a gate of the third thin film transistor is electrically connected to one of the scan lines, a source of the third thin film transistor is electrically connected to one of the common lines, and a drain of the third thin film transistor is electrically connected to a drain of the second thin film transistor and the sub-pixel electrode.
8. The pixel array according to claim 4, wherein the coupling line is connected to a coupling driver for controlling a driving timing of the coupling capacitor.
9. A liquid crystal panel comprising the pixel array according to any one of claims 4 to 8.
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| CN111381406B (en) | 2023-02-03 |
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