CN101888209A - Gaussian White Noise Generator Based on FPGA - Google Patents
Gaussian White Noise Generator Based on FPGA Download PDFInfo
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Abstract
一种信号处理技术领域的基于FPGA的高斯白噪声发生器，包括：伪随机序列发生装置、运算装置、存储装置和控制模块，其中：控制模块与运算装置相连传输运算命令信号，控制模块与存储装置相连传输数据地址信号和数据有效信号，控制模块与伪随机序列发生装置相连传输序列生成命令信号，运算装置与存储装置相连传输运算数据和运算结果，伪随机序列发生装置与存储装置相连传输伪随机序列信号。所述的运算装置包括：加法器、乘法器、第二移位寄存器和二元电路选择器。本发明大大减小了装置的复杂度，且提高了高斯白噪声的输出速率，得到的高斯白噪声方差近似为1，从而适合于复杂的系统。
An FPGA-based Gaussian white noise generator in the technical field of signal processing, comprising: a pseudo-random sequence generating device, a computing device, a storage device and a control module, wherein: the control module is connected with the computing device to transmit a computing command signal, and the control module and the storage device The device is connected to transmit data address signal and data effective signal, the control module is connected to the pseudo-random sequence generating device to transmit the sequence generating command signal, the computing device is connected to the storage device to transmit computing data and computing results, and the pseudo-random sequence generating device is connected to the storage device to transmit pseudo-random sequence generating device. random sequence signal. The computing device includes: an adder, a multiplier, a second shift register and a binary circuit selector. The invention greatly reduces the complexity of the device, and increases the output rate of the Gaussian white noise, and the variance of the obtained Gaussian white noise is approximately 1, thus being suitable for complex systems.
Description
Technical field
What the present invention relates to is the device in a kind of signal processing technology field, specifically is a kind of Gaussian white noise generator based on FPGA (field programmable gate array, Field Programmable Gate Array).
Background technology
In communication and control system, white Gaussian noise is a common noise signal very, therefore need utilize the white Gaussian noise signal source to test and the interference free performance of checking system.Simultaneously, in radio communication channel, usually need the white Gaussian noise signal source.So design realizes the white Gaussian noise signal source of simple in structure a, dependable performance, system is detected very necessary meaning.
Existing Gassian noise generator has physical noise generator and digital composite noise generator two classes usually.Though physical noise generator ratio of precision is higher, realize that circuit is comparatively complicated, so in engineering, more select the Digital Noise generator for use.At present, realize in systems such as microprocessor and DSP in a lot of white Gaussian noise sources, because they can calculate sine and exponential function easily by using function library.But utilize hardware emulator can increase substantially simulation velocity.
Through existing literature search is found, Chinese patent application number is: 88200391.7, name is called: digital voice grade Gaussian white noise generator, this technology comprises: noise source, amplifier, attenuator, but noise source is made of with erasable read only memory EPROM 28 rank m sequencers, and digital noise is output as general simulating the white noise through digital to analog converter.The pseudo random sequence that the digital white Gaussian noise that this technology realizes by hardware circuit, this technology directly produce sequencer is carried out the tap processing and is exported to digital to analog converter as digital white noise.But the digital white Gaussian noise output speed that this technology produced is low, and weak effect is not suitable for the application of complication system.
Summary of the invention
The objective of the invention is to overcome the above-mentioned deficiency of prior art, a kind of Gaussian white noise generator based on FPGA is provided.The present invention has realized the effective processing to pseudo random number by to function fitting and utilization, the output speed height, and noise effects is good, and is fit to be applied to complicated system.
The present invention is achieved by the following technical solutions:
The present invention includes: pseudo-random sequence generating device, arithmetic unit, storage device and control module, wherein: control module links to each other with arithmetic unit and transmits the computing command signal, control module links to each other with storage device and transmits data address signal and data useful signal, the control module transfer sequence that links to each other with pseudo-random sequence generating device generates command signal, arithmetic unit links to each other with storage device and transmits operational data and operation result, and pseudo-random sequence generating device links to each other with storage device and transmits the pseudo random sequence signal.
Described pseudo-random sequence generating device is first shift register.
Described arithmetic unit comprises: adder, multiplier, second shift register and two-dimensional circuit selector, wherein: second shift register links to each other with storage device and transmits the fitting function data, multiplier links to each other with second shift register and transmits the fitting function data, adder links to each other with multiplier and transmits multiplication result information, adder links to each other with storage device and transmits summed result information, the two-dimensional circuit selector links to each other with storage device and transmits final operation result, adder, multiplier, second shift register links to each other with control module respectively with the two-dimensional circuit selector and transmits the s operation control command information.
Described control module comprises: data address control submodule, data are effectively controlled submodule, pseudo random sequence is effectively controlled submodule and s operation control submodule, wherein: data address control submodule links to each other with storage device and transmits data address signal, data are effectively controlled the submodule transmission data effective control signal that links to each other with storage device, pseudo random sequence is effectively controlled the submodule transmission pseudo random sequence that links to each other with pseudo-random sequence generating device and is started and stop signal, s operation control submodule link to each other with arithmetic unit transfer function s operation control signal and two-dimensional circuit selector control signal.
Described storage device comprises: data storage cell and data address memory cell, wherein: data storage cell links to each other with control module and transmits store instruction information, data storage cell links to each other with pseudo-random sequence generating device and transmits effective pseudo random sequence information, data storage cell links to each other with arithmetic unit and transmits operational data information, and the data address memory cell links to each other with control module and transmits address data memory information.
Described control module links to each other with counter.
Compared with prior art, the invention has the beneficial effects as follows: reduced the complexity of device greatly, and improved the output speed of white Gaussian noise, the white Gaussian noise variance that obtains is approximately 1, thereby is suitable for complicated system.
Description of drawings
Fig. 1 is the white Gaussian noise simulation schematic diagram that embodiment obtains.
Embodiment
Below in conjunction with accompanying drawing device of the present invention is further described: present embodiment is being to implement under the prerequisite with the technical solution of the present invention, provided detailed execution mode and concrete operating process, but protection scope of the present invention is not limited to following embodiment.
Embodiment
Present embodiment comprises: pseudo-random sequence generating device, arithmetic unit, storage device, counter and control module, wherein: control module links to each other with arithmetic unit and transmits the computing command signal, control module links to each other with storage device and transmits data address signal and data useful signal, the control module transfer sequence that links to each other with pseudo-random sequence generating device generates command signal, arithmetic unit links to each other with storage device and transmits operational data and operation result, pseudo-random sequence generating device links to each other with storage device and transmits the pseudo random sequence signal, and counter links to each other with control module and transmits count information.
Described pseudo-random sequence generating device is first shift register.
First shift register in the present embodiment is that maximum length is 50 a linear feedback shift register.
Described arithmetic unit comprises: adder, multiplier, second shift register and two-dimensional circuit selector, wherein: second shift register links to each other with storage device and transmits the fitting function data, multiplier links to each other with second shift register and transmits the fitting function data, adder links to each other with multiplier and transmits multiplication result information, adder links to each other with storage device and transmits summed result information, the two-dimensional circuit selector links to each other with storage device and transmits final operation result, adder, multiplier, second shift register links to each other with control module respectively with the two-dimensional circuit selector and transmits the s operation control command information.
Described control module comprises: data address control submodule, data are effectively controlled submodule, pseudo random sequence is effectively controlled submodule and s operation control submodule, wherein: data address control submodule links to each other with storage device and transmits data address signal, data are effectively controlled the submodule transmission data effective control signal that links to each other with storage device, pseudo random sequence is effectively controlled the submodule transmission pseudo random sequence that links to each other with pseudo-random sequence generating device and is started and stop signal, s operation control submodule link to each other with arithmetic unit transfer function s operation control signal and two-dimensional circuit selector control signal.
Described storage device comprises: data storage cell and data address memory cell, wherein: data storage cell links to each other by the internal data interface with control module and transmits store instruction information, data storage cell links to each other by the internal data interface with pseudo-random sequence generating device and transmits effective pseudo random sequence information, data storage cell links to each other by the internal data interface with arithmetic unit and transmits operational data information, data address memory cell and control module be by the internal data interface transmission address data memory information that links to each other, and data storage cell and data address memory cell are respectively by external data interface link to each other with external equipment transmitting data information and data address information.
The present embodiment device adopts Xilinx Spartan-3A DSP 1800A development board to realize, wherein: control module be wherein logical block and the Digital Logical Circuits of microprocessor IP kernel MicroBlaze realize; Pseudo-random sequence generating device and arithmetic unit be wherein logical block and the DPS arithmetic element of microprocessor IP kernel MicroBlaze in shift register realize; Storage device is that wherein logical block and the Block-RAM of microprocessor IP kernel MicroBlaze thereof realizes.
The enforcement running of present embodiment is:
Step 1: control module sends useful signal to pseudo-random sequence generating device.
Step 2: pseudo-random sequence generating device receives behind the effective order signal under the clock of 1.024KHz drives, and produces 50 random sequence, u
1And u
2Can get preceding 32 and back 18 of random sequence respectively, and respectively with u
1And u
2Pass to storage device.
Step 3: control module sends the data useful signal to storage device, and sends run signal to arithmetic unit.
Step 4: the data in the arithmetic unit read storage device, following column operations, and with operation result information x
1And x
2Pass to storage device, send computing simultaneously and finish signal to control module:
x
1＝f(u
1)g
1(u
2)，
x
2＝f(u
1)g
2(u
2)，
Step 5: the s operation control submodule in the control module constantly sends 0/1 instruction to the two-dimensional circuit selector, control result output, the two-dimensional circuit selector reads the corresponding data in the memory module and exports to the bus data interface by internal data bus according to signal.
Step 6: device whenever sends two groups of data, and control module just sends useful signal to pseudo-random sequence generating device once more, returns step 1, stops up to reaching the default number of times of counter.
The probability distribution schematic diagram of the white Gaussian noise that present embodiment obtains as shown in Figure 1, its ordinate is the probability in percent value, abscissa be signal to noise ratio (unit :/dB).
Adopt the method for prior art directly to adopt the variance of the white Gaussian noise that the data of pseudo random sequence produce to surpass 2, and the average of the white Gaussian noise of the device that adopts present embodiment after 10000 data that produce are handled is 0.010700336319647, variance is 0.999869024280097, the variance of the white Gaussian noise that obtains is approximately 1, thereby applied widely.
Claims (5)
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106230386A (en) * | 2016-08-02 | 2016-12-14 | 中国电子科技集团公司第二十九研究所 | A kind of white Gaussian noise produces circuit and method |
| CN108833043A (en) * | 2018-05-31 | 2018-11-16 | 西安电子科技大学 | Improved AWGN channel implementation method and device based on Polar method |
| CN110855246A (en) * | 2019-11-08 | 2020-02-28 | 成都天奥测控技术有限公司 | Method for generating Gaussian white noise with arbitrary variance |
| RU2723271C1 (en) * | 2019-10-01 | 2020-06-09 | Акционерное общество "Концерн "Созвездие" | Method for generation of digital white gaussian noise using the wallace method |
| RU2723272C1 (en) * | 2019-10-01 | 2020-06-09 | Акционерное общество "Концерн "Созвездие" | Digital white gaussian noise generator by wallace method |
| CN114553146A (en) * | 2022-02-28 | 2022-05-27 | 湖南迈克森伟电子科技有限公司 | Noise generation method and circuit |
-
2010
- 2010-07-23 CN CN201010234321XA patent/CN101888209A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106230386A (en) * | 2016-08-02 | 2016-12-14 | 中国电子科技集团公司第二十九研究所 | A kind of white Gaussian noise produces circuit and method |
| CN108833043A (en) * | 2018-05-31 | 2018-11-16 | 西安电子科技大学 | Improved AWGN channel implementation method and device based on Polar method |
| CN108833043B (en) * | 2018-05-31 | 2020-10-30 | 西安电子科技大学 | AWGN channel realization method and device based on Polar method improvement |
| RU2723271C1 (en) * | 2019-10-01 | 2020-06-09 | Акционерное общество "Концерн "Созвездие" | Method for generation of digital white gaussian noise using the wallace method |
| RU2723272C1 (en) * | 2019-10-01 | 2020-06-09 | Акционерное общество "Концерн "Созвездие" | Digital white gaussian noise generator by wallace method |
| CN110855246A (en) * | 2019-11-08 | 2020-02-28 | 成都天奥测控技术有限公司 | Method for generating Gaussian white noise with arbitrary variance |
| CN110855246B (en) * | 2019-11-08 | 2023-04-11 | 成都天奥测控技术有限公司 | Method for generating Gaussian white noise with arbitrary variance |
| CN114553146A (en) * | 2022-02-28 | 2022-05-27 | 湖南迈克森伟电子科技有限公司 | Noise generation method and circuit |
| CN114553146B (en) * | 2022-02-28 | 2023-07-28 | 湖南迈克森伟电子科技有限公司 | Noise generation method and circuit |
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Open date: 20101117 |