RU2723271C1 - Method for generation of digital white gaussian noise using the wallace method - Google Patents

Abstract

FIELD: electrical engineering.SUBSTANCE: invention relates to electrical engineering and can be used to simulate a communication channel for checking a noise-immune encoding module. In the method it is proposed to generate pseudo-random addresses as follows: p=(start – stride)⊕mask; q=start⊕mask; s=(start + stride)⊕mask; r=(start + stride<<1)⊕mask. Subtraction operation is equivalent to adding operation when using binary-additional code and collectively also takes one cycle. Thus, all four addresses can be obtained in one cycle and transmitted to a memory unit. These addresses are obtained in exact accordance with the Wallace algorithm. It should be noted that subtraction is performed modulo N=1024, i.e. number -1 is equivalent to number 1023. At the same time correlation of output readings is reduced at use of only one matrix Adue to use of one of remaining bits from 32-digit reference of generator of uniform random numbers for change of sign of readings p', q', r', s'.EFFECT: faster operation of a digital white Gaussian noise generator.1 cl, 2 dwg

Description

The proposed method relates to the field of electrical engineering, in particular to a method for modeling a communication channel for testing a noise-resistant coding module.

The natural way to implement the error-correcting coding algorithm is as follows.

1) Modeling the algorithm in a high-level language (C - C ++, Matlab, Octave, SystemC, OpenCL), and in integers.

2) Implementation of the algorithm on the FPGA (programmable logic integrated circuit) [Steshenko VB FPGA company Altera: Design of signal processing devices, Moscow 2000]. FPGA is a set of logic elements on the board and registers consisting of binary numbers of a given bit capacity, with the ability to commute them programmatically. The first difference from the implementation of the algorithm on a computer is that the capacity of each register can be arbitrarily selected, and it is not caused by the capacity of the central processor, which is not there. The second difference is that all actions are performed simultaneously and in parallel, but at a lower clock frequency than in the system by the central processor. The description of the algorithm in this case consists of a static description of the switching of elements and a dynamic description of their interaction (VHDL, Verilog). Here, in addition to the correct implementation of the algorithm, questions of energy consumption and physical performance arise. A synchronization pulse is supplied to each structural block, ensuring its dynamic interaction with the others, the element itself having a capacitance and / or inductance, the switching line also has an active and reactive resistance that grows with the dimensions of the circuit, which forces the supply voltage to increase in order to prevent “erosion” fronts of synchronizing pulses. All of the above factors limit the FPGA clock frequency of 200 MHz. Currently, there are attempts to use a high-level language for programming FPGAs, this is complicated by the fact that high-level languages do not have the means to describe static links. However, there are library extensions (SystemC) over the C / C ++ language that allow you to model the system behavior of the model by describing the interfaces, queues, signals in a static and dynamic form, but such a simulation does not take into account the real physical processes in the chip.

Verification of the developed algorithms is achieved through the consistent use of test vectors developed in the previous stages. A test vector can be a digitized mixture of signal and noise, a binary configuration of errors with specified properties, any set of test values that, when applied to the input of a device being developed or an element of this device, will cause a predicted (at the previous stage) reaction. I would like to note that error-correcting coding algorithms correct all errors, including those of the developer and programmer, so some tests that are not related to Monte Carlo simulations in white Gaussian noise can be successfully completed even if there are errors in the implementation. Complete verification is provided by statistically reliable FPGA simulation using the Monte Carlo method in a channel where the additive interference is white Gaussian noise (BSS). Therefore, the urgent task is to develop the components of such a model, in particular, a white Gaussian noise generator in integers for its implementation on the FPGA.

Well-known algorithms are Box-Muller [G. E. P. Box and M. E. Muller, “A note on the generation of randomnormal deviates,” Ann. Math. Stat., Vol. 29, pp. 610–61, 1958.] and polar [Marsaglia, G .; Bray, T. A. (1964). "A Convenient Method for Generating Normal Variables." SIAM Review. 6 (3): 260–264. doi: 10.1137 / 1006063. JSTOR 2027592., D. E. Knuth, The Art of Computer Programming, Volume 2: Seminumerical Algorithms (second edition). Addison-Wesley, Menlo Park, 1981.] require the calculation of the functions log, sin, cos, which is a difficult task to implement in integer arithmetic. Wallace proposed his method [C. S. Wallace "Fast Pseudorandom Generators for Normal and Exponential Variates", ACM Transactions on Mathematical Software, Vol. 22, No. 1, March 1996, Pages 119-127] that did not require floating-point calculations, at least at every measure.

Wallace's method is as follows:

элементов гауссовскими случайными величинами с нулевым матожиданием и единичной дисперсией;• pre-populate an array of

elements with Gaussian random variables with zero expectation and unit dispersion;

адресов для доступа к массиву, первый из которых равномерно распределенное случайное число от

до

, а остальные

;• form

addresses to access the array, the first of which is a uniformly distributed random number from

before

and the rest

;

случайных величин выполняют ортогональное линейное преобразование путем умножения на ортогональную матрицу, получая

новых отсчетов;• for

random variables perform an orthogonal linear transformation by multiplying by an orthogonal matrix, obtaining

new readings;

• раз повторяют шаги 2 и 3, формируют новый массив из

, перемежают его, записывая по строкам и читая по столбцам в перемежителе

, перемеженным массивом заменяют первоначально инициализированный массив;

• once repeat steps 2 and 3, form a new array of

, interleave it, writing row by row and reading column by column in the interleaver

interleaved array replace the initially initialized array;

элементов массива, которые являются выходом алгоритма.• calculate the correction factor using the last element from the new array, multiply by the correction normalization factor by

array elements that are the output of the algorithm.

In the future, the algorithm for improving statistical properties, in particular, to reduce the correlation between samples, underwent a number of changes.

An analogue is the Chinese application Gaussian white noise generator based FPGA CN201810037910.5A, CN108390648A priority 2018/01/16 published on 2018/08/10, where a white Gaussian noise generator implemented by the Wallace algorithm is given [C. S. Wallace, Fast Pseudo-Random Generators for Normal and Exponential Variates, ACM Trans. on Mathematical Software 22 (1996), 119–127].

The method implemented in this device differs from the method from [Dong-U Lee, Wayne Luk, John D. Villasenor, Guanglie Zhang, Philip HW Leong "A Hardware Gaussian Noise Generator Using the Wallace Method" IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION ( VLSI) SYSTEMS, VOL. 13, NO. 8, AUGUST 2005] in that:

• another generator of uniform random variables (simpler) was taken;

• addresses are calculated by the formulas:

суммирование с единицей есть просто присоединение дополнительного бита. Однако в [Dong-U Lee, Wayne Luk, John D. Villasenor, Guanglie Zhang, Philip H. W. Leong "A Hardware Gaussian Noise Generator Using the Wallace Method" IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 13, NO. 8, AUGUST 2005] указывается, что изменение алгоритма генерации адресов весьма критично влияет на статистические свойства результирующей последовательности, поэтому точное выполнение алгоритма Уоллеса в плане генерации псевдослучайных адресов имеет важное значение. В заявке CN108390648A добились сбалансированного вычисления адресов, т. е. каждый адрес вычисляют за одинаковое количество тактов, только за счет изменения оригинального алгоритма. Calculation of each of the addresses will take no more than a beat, since in the case of

summing with a unit is simply adding an extra bit. However, in [Dong-U Lee, Wayne Luk, John D. Villasenor, Guanglie Zhang, Philip HW Leong "A Hardware Gaussian Noise Generator Using the Wallace Method" IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 13, NO. 8, AUGUST 2005], it is pointed out that changing the address generation algorithm has a very critical effect on the statistical properties of the resulting sequence; therefore, the exact execution of the Wallace algorithm in terms of pseudo-random address generation is important. In the application CN108390648A, a balanced calculation of addresses was achieved, that is, each address is calculated for the same number of clock cycles, only by changing the original algorithm.

Closest to the claimed is the method described in [Dong-U Lee, Wayne Luk, John D. Villasenor, Guanglie Zhang, Philip HW Leong "A Hardware Gaussian Noise Generator Using the Wallace Method" IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 13, NO. 8, AUGUST 2005] adopted as a prototype.

The prototype method is as follows:

элементов гауссовскими случайными величинами с нулевым матожиданием и единичной дисперсией;• pre-populate an array of

elements with Gaussian random variables with zero expectation and unit dispersion;

и одно 9-разрядное число

путем последовательного взятия бит, с первого по десятый, с одиннадцатого по двадцатый, с двадцать первого по двадцать девяты1;• each cycle, using a 32-bit sample of the generator of uniform random numbers, forms two 10-bit numbers:

and one 9-bit number

by sequentially taking bits from the first to the tenth, from the eleventh to the twentieth, from the twenty-first to twenty-ninth1;

• 4 addresses are formed in each clock cycle:

, формируют 4-х мерный вектор

, выполняют ортогональное линейное преобразование

, • read counts at the generated addresses

form a 4-dimensional vector

perform orthogonal linear transformation

,

,

• where

,

и

используют попеременно и меняют через каждые

отсчета;matrices

and

use alternately and change every

countdown;

записывают в массив по новым адресам

, полученным за то время, пока выполнялось ортогональное преобразование;• received readings

write to the array at new addresses

obtained while the orthogonal transformation was performed;

поступают на вход блока коррекции, где каждый отсчет умножают на корректирующий множитель

, получая отсчеты

, которые являются выходом алгоритма;• also readings

arrive at the input of the correction block, where each sample is multiplied by a correction factor

getting samples

which are the output of the algorithm;

отсчетов производят корректировку корректирующего множителя по формуле

, где

текущий отсчет

предвычисленные константы.• every

samples correct the correction factor according to the formula

where

current countdown

precomputed constants.

отсчетов была бы константой, что неприемлемо для моделирования. В качестве генератора 32-битных равномерных случайных чисел используют генератор Таусворта [ P. L’Ecuyer, “Maximally equidistributed combined Tausworthe generators,” Math. Comput., vol. 65, no. 213, pp. 203–213, 1996] с порождающим полиномом

. Периодичность такого генератора

бит.The need for a correction factor is due to the fact that if it is absent, the sum of the squares of each

samples would be a constant, which is unacceptable for modeling. As a 32-bit uniform random number generator, the Tausworth generator [P. L'Ecuyer, “Maximally equidistributed combined Tausworthe generators,” Math. Comput., Vol. 65, no. 213, pp. 203–213, 1996] with a generating polynomial

. The frequency of such a generator

bit.

могут быть получены посредством следующих операций: Consider the operation of the orthogonal linear transformation unit. Easy to see counts

can be obtained through the following operations:

для матрицы

,

for matrix

,

для матрицы

.

for matrix

.

. Эти вычисления займут три такта и могут быть выполнены в конвейерном режиме. Матрицы используют поочередно, каждые

отсчетов меняя между собой.It is easy to see that

. These calculations will take three clock cycles and can be performed in pipelined mode. Matrices are used alternately every

counts changing among themselves.

. Таким образом, вычисление

займет два такта, а остальных адресов – один такт, что является недостатком блока формирования адресов, так как ограничивает его быстродействие.Consider the work of the address generation unit. The sum operation, followed by the addition of the result modulo 2, is a quick operation that can be performed in one clock cycle. Also fast is the operation of multiplying by 2, which, in essence, is a bit shift or rearrangement of bits and does not require time-consuming. However, the operation of multiplying by 3 takes a whole cycle and can be performed as a sum

. Thus, the calculation

it will take two clock cycles, and the remaining addresses - one clock cycle, which is a drawback of the address generation block, as it limits its speed.

The task of simplifying and improving the speed of the method, in particular, balancing the calculations in the address generation unit, is solved by the analogue method [Chen Yong Gaussian white noise generator based FPGA CN201810037910.5A, CN108390648A], however, the addresses are formed in a different way than in the prototype method, which may cause deterioration of the statistical properties of the resulting sequence of samples of white Gaussian noise.

The most used at present is dual-port memory, which allows you to access to write or read simultaneously to two addresses. However, developments are known [Kevin R. Townsend, Osama G. Attia, Phillip H. Jones, and Joseph Zambreno "A Scalable Unsegmented Multiport Memory for FPGA-Based Systems", International Journal of Reconfigurable Computing Volume 2015, Article ID 826283, 12 pages] allowing to organize effective multiport memory access. Thus, it is seen that the efficiency and speed of the digital white noise generator can be significantly improved due to the balancing of calculations and the use of multiport memory.

The problem to which the claimed technical solution is directed is to increase the efficiency of testing electronic equipment, in particular, a system for modeling noise-resistant codes.

элементов гауссовскими случайными величинами с нулевым матожиданием и единичной дисперсией; в каждый такт, используя 32-разрядный отсчет генератора равномерных случайных чисел, формируют 2 10-разрядных числа:

и одно 9-разрядное двоичное число

путем последовательного взятия бит с первого по десятый, с одиннадцатого по двадцатый, с двадцать первого по двадцать девятый; в каждый такт формируют четыре адреса, считывают по сформированным адресам

отсчеты

, формируют 4-х мерный вектор

, выполняют ортогональное линейное преобразование

, где

To solve the problem in the method of generating samples of digital white Gaussian noise, which consists in filling an array of

elements with Gaussian random variables with zero expectation and unit dispersion; in each cycle, using a 32-bit sample of the generator of uniform random numbers, form 2 10-bit numbers:

and one 9-bit binary number

by sequentially taking bits from the first to the tenth, from the eleventh to the twentieth, from the twenty-first to the twenty-ninth; four addresses are formed in each clock cycle, read at the generated addresses

counts

form a 4-dimensional vector

perform orthogonal linear transformation

where

by performing the following operations:

,

,

,

,

записывают в массив по новым адресам

, полученным за то время, пока выполнялось ортогональное преобразование; также отсчеты

поступают на вход блока коррекции, где каждый отсчет умножают на корректирующий множитель

, получая отсчеты

, которые являются результатом алгоритма; каждые

отсчетов производят корректировку корректирующего множителя по формуле

, где

текущий отсчет

предвычисленные константы, которые определяются по следующим формулам:

,received readings

write to the array at new addresses

obtained while the orthogonal transformation was performed; also readings

arrive at the input of the correction block, where each sample is multiplied by a correction factor

getting samples

that are the result of an algorithm; every

samples correct the correction factor according to the formula

where

current countdown

precomputed constants, which are determined by the following formulas:

,

из тридцатого бита генератора равномерных случайных чисел; адреса формируют по формулам:according to the invention, form a single-bit signal

from the thirtieth bit of the generator of uniform random numbers; addresses are formed by the formulas:

, то изменяют знак отсчетов

на противоположный.while if

then change the sign

to the opposite.

The inventive method solves the technical problem of improving performance by balancing the calculations in the address generation unit, without changing the original algorithm without degrading the statistical properties of the resulting sequence of white Gaussian noise samples.

Graphic materials used in the description:

FIG. 1 is a diagram of a device that implements the inventive method;

FIG. 2 is a diagram of an address generating unit.

The inventive method is as follows.

элементов гауссовскими случайными величинами с нулевым матожиданием и единичной дисперсией;Fill an array of

elements with Gaussian random variables with zero expectation and unit dispersion;

и одно 9-разрядное

путем последовательного взятия бит, с первого по десятый, с одиннадцатого по двадцатый, с двадцать первого по двадцать девятый, а также формируют однобитный сигнал

из тридцатого бита;each cycle, using a 32-bit sample of the uniform random number generator, forms two 10-bit numbers:

and one 9-bit

by sequentially taking bits from the first to the tenth, from the eleventh to the twentieth, from the twenty-first to the twenty-ninth, and also form a single-bit signal

from the thirtieth bit;

Each cycle is formed by 4 addresses:

, формируют 4-х мерный вектор

, выполняют ортогональное линейное преобразование

, где

read samples from the generated addresses

form a 4-dimensional vector

perform orthogonal linear transformation

where

by performing the following operations:

,

,

,

,

то изменяют знак отсчетов

на противоположный;if

then change the sign

to the opposite;

записывают в массив по новым адресам

, полученным за то время, пока выполнялось ортогональное преобразование;received readings

write to the array at new addresses

obtained while the orthogonal transformation was performed;

также поступают на вход блока коррекции, где каждый отсчет умножают на корректирующий множитель

, получая отсчеты

, которые являются выходом алгоритма;counts

also enter the input of the correction block, where each sample is multiplied by a correction factor

getting samples

which are the output of the algorithm;

отсчетов производят корректировку корректирующего множителя по формуле

, где

текущий отсчет

предвычисленные константы, которые определяются по следующим формулам:

.every

samples correct the correction factor according to the formula

where

current countdown

precomputed constants, which are determined by the following formulas:

.

New distinctive features of the method are:

из тридцатого бита;- formation of a one-bit signal

from the thirtieth bit;

то изменяют знак отсчетов

на противоположный;-if

then change the sign

to the opposite;

-formation of four addresses according to the formulas:

A device implementing the inventive method is shown in FIG. 1, where indicated:

1 - generator of uniform random numbers (HRGS);

2 - multiplexer;

3 - block formation of addresses (BFA);

4 - memory block;

5 - initialization block;

6 - block orthogonal transformation;

7 - block correction.

. Выходы блока формирования адресов 3 соединены с соответствующими входами блока памяти 4, четыре выхода которого соединены с соответствующими входами блока ортогонального преобразования 6, выходы которого соединены с соответствующими входами блока памяти 4 и блока коррекции 7, выходы которого являются выходами устройства. Выход блока инициализации 5 соединен с соответствующим входом блока памяти 4. Четвертый выход мультиплексора 2, соответствующий сигналу

, подключен к пятому входу блока ортогонального преобразования 6.The device contains a series-connected generator of uniform random numbers 1 and a multiplexer 2, the three outputs of which are connected to the corresponding inputs of the address generation unit 3 and correspond to signals

. The outputs of the address generation unit 3 are connected to the corresponding inputs of the memory unit 4, the four outputs of which are connected to the corresponding inputs of the orthogonal transformation unit 6, the outputs of which are connected to the corresponding inputs of the memory unit 4 and the correction unit 7, the outputs of which are the outputs of the device. The output of the initialization unit 5 is connected to the corresponding input of the memory unit 4. The fourth output of the multiplexer 2, corresponding to the signal

connected to the fifth input of the orthogonal transform unit 6.

In FIG. 2 is a diagram of the address generation unit, where it is indicated:

3.1 - shift node;

3.2 - subtractor;

3.3, 3.4 - the first and second adders;

3.5, 3.6, 3.7, 3.8 - the first, second, third and fourth nodes are exclusive or.

Выход узла сдвига 1 через второй сумматор 3.4 соединен с первым входом четвертого узла "исключающее или" 3.8. Выход вычитателя 3.2 соединен с первым входом первого узла "исключающее или" 3.5. Выход первого сумматора 3.3 соединен с первым входом третьего узла "исключающее или" 3.7. Первый вход второго узла "исключающее или" 3.6 соединен со вторыми входами вычитателя 3.2, первого 3.3 и второго 3.4 сумматоров и является первым входом блока формирования адресов 3 и соответствует сигналу

. Кроме того, вторые входы первого 3.5, второго 3.6, третьего 3.7 и четвертого 3.8 узлов "исключающее или" объединены и являются входом блока формирования адресов 3, соответствующий сигналу

. Выходы узлов "исключающее или" являются выходами блока формирования адресов 3, соответствующие сигналам

.The address generating unit 3 comprises a shift unit 1, a subtractor 3.2, a first 3.3 and a second 3.4 adders, as well as a first 3.5, a second 3.6, a third 3.7, and a fourth 3.8 “exclusive or” nodes. The input of the shift node 1, the first inputs of the subtractor 3.2 and the first adder 3.3 are combined and are the second input of the address generation unit 3 and correspond to the signal

The output of the shift unit 1 through the second adder 3.4 is connected to the first input of the fourth node "exclusive or" 3.8. The subtractor 3.2 output is connected to the first input of the first exclusive or 3.5 node. The output of the first adder 3.3 is connected to the first input of the third node exclusive or 3.7. The first input of the second exclusive or 3.6 node is connected to the second inputs of the subtractor 3.2, the first 3.3 and the second 3.4 adders and is the first input of the address generation unit 3 and corresponds to the signal

. In addition, the second inputs of the first 3.5, second 3.6, third 3.7 and fourth 3.8 nodes "exclusive or" are combined and are the input of the address generation unit 3 corresponding to the signal

. The outputs of the nodes "exclusive or" are the outputs of the address generation unit 3 corresponding to the signals

.

и

и один 9-разрядный сигнал stride для блока формирования адресов 3, а также однобитный сигнал

для блока ортогонального преобразования 6. В блоке формирования адресов 3 параллельно формируют четыре адреса по формуле: A device that implements the proposed method works as follows. A 32-bit uniform random number is formed in the uniform random number generator (GPRS) 1 from which two 10-bit signals are generated in the multiplexer 2:

and

and one 9-bit stride signal for address block 3, as well as a single-bit signal

for the orthogonal transform unit 6. In the address generation unit 3, four addresses are formed in parallel using the formula:

для блока ортогонального преобразования 6, а также запись текущих отсчетов

с выхода блока ортогонального преобразования 6, в блоке ортогонального преобразования проводят преобразования входных сигналов

по формулам:on which readout of samples

for block orthogonal transform 6, as well as recording current samples

from the output of the orthogonal transform unit 6, in the orthogonal transform unit, transform the input signals

according to the formulas:

,

,

,

,

на противоположный, если

, отсчеты

поступают на вход блока коррекции 7 где получают выходные отсчеты алгоритма в видеand also change the sign

to the opposite if

counts

arrive at the input of correction block 7 where they receive the output samples of the algorithm in the form

отсчетов производят обновление по формуле

, где

текущий отсчет белого гауссовского шума

предвычисленные константы, которые определяются по следующим формулам:

.where after every

samples update according to the formula

where

current sample of white gaussian noise

precomputed constants, which are determined by the following formulas:

.

The technical result consists in increasing the speed of the method and is achieved by balancing the calculations in the address generation unit 6, for which it is proposed to generate pseudo-random addresses as follows:

, т. е. число -1 эквивалентно числу 1023. Таким образом, заявляемый способ позволяет достичь двукратного повышения производительности блока формирования адресов. Производительность генератора цифрового белого гауссовского шума по методу Уоллеса при условии применения четырех портового блока алгоритма доступа к блоку памяти также повысится в два раза при этом генератор равномерных случайных величин используют такой же как и в способе прототипе. Таким образом, выигрыш в производительности достигнут без ухудшения статистических свойств получаемых отсчетов белого шума.The subtraction operation is equivalent to the addition operation when using a binary-additional code, and in aggregate it also takes one clock cycle. Thus, all 4 random addresses can be obtained in one clock cycle and transferred to the memory block. It should be noted that the subtraction is performed modulo

, that is, the number -1 is equivalent to the number 1023. Thus, the claimed method allows to achieve a twofold increase in the performance of the address generation unit. The performance of the digital white Gaussian noise generator according to the Wallace method, provided that the four port block of the algorithm for accessing the block of memory is applied, will also double, while the generator of uniform random variables is used the same as in the prototype method. Thus, a gain in performance is achieved without compromising the statistical properties of the resulting white noise samples.

Claims (9)

1. The method of generating samples of digital white Gaussian noise, which consists in filling an array of

elements with Gaussian random variables with zero expectation and unit dispersion; in each cycle, using a 32-bit sample of the generator of uniform random numbers, form two 10-bit numbers

and one 9-bit binary number

by sequentially taking bits from the first to the tenth, from the eleventh to the twentieth, from the twenty-first to the twenty-ninth; four addresses are formed in each clock cycle, read at the generated addresses

counts

form a 4-dimensional vector

perform orthogonal linear transformation

where

, by performing the following operations:

,

, received readings

write to the array at new addresses

obtained while the orthogonal transformation was performed; also readings

arrive at the input of the correction block, where each sample is multiplied by a correction factor

getting samples

that are the result of an algorithm; every

samples correct the correction factor according to the formula

where

- current countdown

- precomputed constants, which are determined by the following formulas:

, characterized in that they form a one-bit signal

from the thirtieth bit of the generator of uniform random numbers; addresses are formed by the formulas:

while if

then change the sign

to the opposite. 2. The method according to claim 1, characterized in that apply the method of generating Tausworth with a generating polynomial

which results in 32-bit samples.

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