CN106774624A - A kind of Parallel Implementation method of real-time white Gaussian noise hardware generator - Google Patents

Abstract

The invention discloses a parallel realization method of a real-time Gaussian white noise hardware generator. The invention can realize the high-quality Gaussian white noise generation of the Gaussian white noise hardware generator in real time, at high speed and in parallel. The present invention firstly realizes the FPGA high-speed parallel realization of uniform white noise based on the cellular automata theory, and provides the calculation method of the N-way initial vectors required for parallel realization and the recursive function relationship of the parallel generation algorithm of the cellular automata; then, provides The Box_Muller algorithm is a low-complexity approximation method, which simplifies the Box_Muller algorithm into simple multiplication and addition and CORDIC operations. FPGA implementation only consumes a small amount of multipliers and logic resources, so that real-time , High-speed generation of Gaussian white noise with long period, wide bandwidth and good quality.

Description

A Parallel Realization Method of Real-time Gaussian White Noise Hardware Generator

technical field

The invention relates to the technical field of wireless channel simulation and noise modeling, in particular to a parallel implementation method of a real-time Gaussian white noise hardware generator.

Background technique

Because wireless channel simulation technology can reproduce an ideal, degraded, or even near-real radio wave propagation environment on the ground, and simulate the impact of various time and space changes in the channel on signal propagation, it has long become an indispensable verification in the technical fields of communication, measurement and control, etc. means of testing. Compared with wired channels, wireless channels are a harsh medium for radio wave propagation, with complex characteristics such as randomness and unpredictability. In the process of channel transmission, radio waves will inevitably be affected by random non-ideal characteristics such as noise interference, channel fading, ionospheric scintillation, and dynamic rain attenuation. In order to study the impact of these non-ideal characteristics on radio wave propagation, domestic and foreign scholars usually use Gaussian white noise modeling as the basis, and then use various linear or nonlinear complex transformations to model and analyze other non-ideal characteristics of the channel. It can be seen that Gaussian white noise is the most important thing in the study of random non-ideal characteristics of wireless channels. The study of Gaussian white noise theory and implementation methods is of great significance to the modeling, simulation and simulation of wireless channel characteristics.

Research data show that Gaussian white noise is mostly generated by Gaussian processing of uniformly distributed white noise through some algorithms. At present, the generation methods of uniform white noise mainly include linear congruence algorithm, delayed Fibonacci method, linear shift register method and cellular automata theory. Compared with the delayed Fibonacci method, the linear congruence method is less effective in performance tests such as the uniformity of random number distribution and subsequence dependencies, but the latter requires more multiplier resources. FPGA (Field Programmable Gate Array) consumes a lot of hardware resources. The linear shift register method is currently the most widely used method, which has outstanding advantages such as simple algorithm, fast speed, strong repeatability and easy FPGA hardware implementation. However, due to the linear feedback structure of this method, the generated pseudo-random numbers will have a strong correlation, and the quality of uniform white noise generation is relatively poor. In contrast, the cellular automata theory has only been used in the generation of uniform white noise in recent years. Because the noise it generates has outstanding advantages such as long period, fast speed, good statistical characteristics, and less hardware resources occupied, it has been widely used since it came out. It has received extensive attention from scholars at home and abroad.

In terms of Gaussian white noise generation algorithms, it mainly includes cumulative distribution function inverse transformation method, rejection-acceptance method and uniform white noise transformation method. The basic idea of the cumulative distribution function inverse transformation method is to inversely change the cumulative distribution function of any given random variable, so as to obtain the random variable corresponding to the cumulative distribution function. This method is intuitive and easy to understand, but it needs to store the mapping relationship between nonlinear Gaussian cumulative distribution function and Gaussian white noise during hardware implementation, which will inevitably occupy a large amount of storage resources. The basic idea of the rejection-acceptance method is to determine whether the generated random variable belongs to Gaussian white noise according to some given criteria, and then decide whether to choose or not. However, since this method needs to use the loop condition to discriminate the input variables and discard the data that cannot produce Gaussian white noise after conversion, its efficiency is not high and it is not suitable for hardware implementation. In contrast, the uniform white noise transformation method does not need to solve the inverse transformation of the cumulative distribution function, and generates Gaussian white noise by directly transforming uniformly distributed white noise. At present, this kind of method is the most widely used, mainly including Box-Muller algorithm, central limit theorem accumulation method, Monty Python algorithm and segmental approximation method based on triangular distribution, etc.

In terms of Gaussian white noise generators, most of the early Gaussian white noise generators were implemented based on computer software. It was not until the 1980s and 1990s that different types of Gaussian white noise hardware generators appeared one after another. For example, Gaussian white noise hardware generator based on Ziggurat algorithm, Gaussian white noise hardware generator based on Box-Muller algorithm, Gaussian white noise hardware generator based on delayed Fibonacci algorithm and central limit theorem, etc. However, the research focus of the above-mentioned hardware generator is mainly on how to generate high-quality Gaussian white noise with low FPGA resource consumption, but the generation speed of Gaussian white noise is ignored. In particular, with the advent of broadband and ultra-wideband systems, how to generate high-quality white Gaussian noise in real time and at high speed with low hardware resource consumption is very important. Therefore, it is of great significance to study the high-speed, parallel generation algorithm and hardware implementation method of Gaussian white noise.

Contents of the invention

In view of this, the present invention provides a parallel implementation method of a real-time Gaussian white noise hardware generator, based on cellular automata theory and Box_Muller algorithm, realizes the real-time, high-speed, parallel generation of high-quality Gaussian white noise hardware generator Gaussian white noise.

The parallel implementation method of the real-time Gaussian white noise hardware generator of the present invention comprises the following steps:

Step 1, select the cellular automata rule as the zero-boundary 90/150 cellular automata rule, under this rule, calculate the order M of the cellular automata and two reciprocal rules according to the period length of the Gaussian white noise to be generated Vectors d ₁ and d ₂ , where d ₁ ={d ₁ (m),m=1,2,...,M} and d ₂ ={d ₂ (m),m=1,2,... .,M}, elements d ₁ (m) and d ₂ (m) in the regular vector are 0 or 1;

Step 2, set the initial vector s ₀ of the cellular automaton as s ₀ ={s ₀ (m),m=1,2,3...,M}, and the initial vector is a non-zero vector; where, the element s ₀ (m) is 0 or 1;

Step 3, generate two groups of parallel implementations of uniform white noise inside the FPGA, specifically including the following sub-steps:

Step 3.1, according to the sampling frequency f _s of the actual application system and the working clock f _clk of the FPGA, calculate the number of parallel channels in Indicates rounding up;

Step 3.2, according to the regular vector d ₁ and the initial vector s ₀ , obtain the initial vector s _p ={s _p (m),m=1,2,...,M} of the parallel paths under the regular vector d ₁ , p=1,2,...,N;

Among them, any element s ₁ (m) in the first initial vector s ₁ is:

Among them, the symbol Express XOR operation, m=1,2,3,...,M; s ₀ (0)≡0, s ₀ (M+1)≡0;

The element s _p (m) in the initial vector s _p of any parallel path p is:

And s _p (0)≡0 and s _p (M+1)≡0

Step 3.3, same as step _3.2 , according to the rule vector d ₂ and the initial vector s ₀ , obtain the initial vector r _p ={r _p (m),m=1,2,... ,M}, p=1,2,...,N;

Step 3.4, according to the zero-boundary 90/150 cellular automaton rule, deduce the recursive function f of each parallel path under the rule vector d ₁ ; where, p=1,2,…,N; among them, is the state vector of the p-th road and the n-th moment, is the state vector of the pth road and the n-1th moment,

Similarly, the recursive function g of each parallel path under the regular vector d ₂ is obtained; where, p=1,2,…,N; among them, is the state vector of the p-th road and the n-th moment, is the state vector of the pth road and the n-1th moment,

In step 3.5, the N initial vectors s _p generated in step 3.2 and the N initial vectors r _p generated in step 3.3 are respectively regarded as two sets of Mbit binary numbers, and according to the recursive function relationship f and g derived in step 3.4, in the FPGA Generate 2 sets of N-channel uniform white noise in parallel with p=1,2,...,N;

Step 4: Generate parallel N-way Gaussian white noise, specifically including the following steps:

Step 4.1, for the first group of uniform white noise generated in step 3 Using non-equal interval piecewise polynomial fitting method for Box_Muller algorithm Fitting is performed to obtain the fitting coefficients of each non-equal interval segment; the fitting coefficients are quantized and stored in the internal memory of the FPGA; inside the FPGA, the first group of Mbits generated in parallel in step 3 are evenly distributed according to the stored fitting coefficients White Noise Perform parallel polynomial calculations and intercept high Mbit as intermediate results

Step 4.2, for the second group of uniform white noise generated in step 3 According to the formula y ₂ =cosx ₂ in the Box_Muller algorithm, use the CORDIC IP core parallel calculation inside the FPGA to generate M bit intermediate results

Step 4.3: Generate p-th Gaussian white noise g _p (n) in parallel in the FPGA, p=1, 2,..., N: in the p-th path, two Mbit and Multiply, and intercept the high M ₀ bit of the product result as the Gaussian white noise g _p (n) that is finally generated; where M ₀ is the effective number of digits of the digital-to-analog converter;

Step 5: After parallel-to-serial conversion processing is performed on the N-channel Gaussian white noise generated in step 4, the final Gaussian white noise is generated through digital-to-analog conversion.

Further, in the step 1, the rule vector is obtained by Euclidean algorithm or table lookup.

Beneficial effect:

Compared with the prior art, the present invention has the following advantages:

Firstly, a parallel generation algorithm of uniform white noise based on cellular automata theory and an FPGA-based implementation method are proposed. On the basis of cellular automata theory, the present invention provides the selection method of cellular automata rule, order and number of parallel paths according to the period length of uniform white noise to be produced, the high-speed sampling frequency of the actual system and the low-speed working clock of FPGA. The calculation method of N-way initial vectors required for parallel implementation and the recursive function relationship of the parallel generation algorithm of cellular automata are deduced, and finally a high-speed parallel implementation method of FPGA based on uniform white noise of cellular automata is given. Therefore, the method proposed in the present invention takes into account many advantages of cellular automata theory to generate uniform white noise, such as long cycle, fast speed, good statistical characteristics, and less hardware resource occupation, etc., and greatly improves the real-time performance of uniform white noise and generation speed.

Then, a low-complexity approximation method of Box_Muller algorithm is given. In this method, polynomials with non-equal intervals are used to approximate the logarithm and square root operations in the original Box_Muller algorithm, and the CORDIC algorithm is used to perform the cos operation in the Box_Muller algorithm. Through the above approximation, the Box_Muller algorithm can be simplified to simple multiplication and addition and CORDIC operations, and only a small amount of multipliers and logic resources are required for FPGA implementation. It is especially suitable for high-speed, parallel Gaussian white noise generation.

In summary, compared with the existing Gaussian white noise hardware generator, the method proposed in the present invention can generate Gaussian white noise with long period, large bandwidth and good quality in real time and at high speed with lower FPGA resource consumption .

Description of drawings

Fig. 1 is the realization structure of calculation of the intermediate result 1 of any parallel path p.

Fig. 2 is a structural block diagram of the Gaussian white noise hardware generator of the present invention.

detailed description

The present invention will be described in detail below with reference to the accompanying drawings and examples.

The invention provides a parallel implementation method of a real-time Gaussian white noise hardware generator. Based on cellular automata theory and Box_Muller algorithm, high-quality Gaussian white noise can be generated in parallel, in real time and at high speed on FPGA. The present invention first determines the order, rules and parallel paths of the cellular automata according to the length of the noise cycle, the high-speed sampling frequency of the actual system, and the low-speed working clock of the FPGA; Two reciprocal regular vectors are obtained by the algorithm or table lookup; at the same time, according to the theory of cellular automata, the N-way initial vectors and function recursion relations required for parallel implementation are deduced from the arbitrarily set non-zero initial vectors, and in FPGA internally generates two sets of uniform white noise; finally, adopts non-equal interval polynomial fitting and CORDIC algorithm to approximate the Box_Muller algorithm, performs Gaussian processing on the two sets of uniform white noise generated in parallel, and then performs parallel-serial conversion and D/A external Play to produce the final white Gaussian noise.

Specific steps are as follows:

Step 1: Determine the rules and orders of the cellular automaton according to the period length of Gaussian white noise that needs to be generated.

Assuming that the length of the cycle that needs to generate Gaussian white noise is L, in order to generate uniform white noise with a longer cycle with a lower cellular automaton order, the present invention chooses the zero-boundary 90/150 cellular automaton rule. Under this cellular automaton rule, the order M is calculated as follows:

in, Indicates a round up operation.

Step 2: According to the zero-boundary 90/150 cellular automaton rule and order M determined in step 1, two reciprocal rule vectors of M-order cellular automata can be obtained by Euclid algorithm or table lookup, which are denoted as : d ₁ ={d ₁ (m),m=1,2,...,M} and d ₂ ={d ₂ (m),m=1,2,...,M}, where the regular vector There are only two possible elements, 0 and 1, namely d ₁ (m)∈{0,1} and d ₂ (m)∈{0,1}.

Step 3: Set any non-zero vector of M elements as the initial vector of the cellular automaton, where each element has only two values of 0 or 1, denoted as s ₀ ={s ₀ (m),m=1, 2,3...,M}, where m represents the position of the element in the vector, and there exists s ₀ (m)∈{0,1}.

Step 4: According to the rules of cellular automata, order M, rule vectors d ₁ and d ₂ , and initial vector s ₀ , deduce the parallel realization algorithm of cellular automata, and generate two sets of parallel realization uniform white noise inside FPGA.

details as follows:

Step 4.1: Calculate the number of parallel channels according to the sampling frequency f _s of the actual application system and the working clock f _clk to be adopted by the FPGA hardware in Indicates a round up operation.

Step 4.2: According to the regular vector d ₁ and the initial vector s ₀ , recursively generate the first group of N initial vectors required for parallel implementation according to the cellular automata theory, denoted as s _p ={s _p (m),m=1 ,2,...,M; p=1,2,...,N}, where m∈[1,M] represents the position of the element in the vector, and p∈[1,N] represents the number of parallel paths.

The specific principles of the sub-steps are as follows:

According to the theory of cellular automata, any element s ₁ (m) in the initial vector s ₁ of the parallel path p=1 can be calculated from the regular vector d ₁ and the elements in the initial vector s ₀ according to the following formula:

Among them, the symbol Indicates XOR operation, vector element position m=1,2,3,...,M. According to the zero-boundary 90/150 cellular automata rule, there exist s ₀ (0)≡0 and s ₀ (M+1)≡0.

Similarly, the elements in the initial vector s _p of any parallel path p can be calculated from the elements in the initial vector s _p - ₁ of the p-1th path and the regular vector d ₁ according to the following formula:

Wherein, _p =2, 3, . . . , N, sp (0) _≡0 and sp (M+1)≡0 exist.

Therefore, according to the regular vector d ₁ and the initial vector s ₀ , the N initial vectors s _p ={s _p (m),m=1, 2,...,M,p=1,2,...,N}.

Step 4.3: Similarly, according to the regular vector d ₂ and the initial vector s ₀ , recursively generate the second group of N initial vectors required for parallel implementation according to the cellular automata theory, denoted as r _p ={r _p (m), m=1,2,...,M; p=1,2,...,N}, where m∈[1,M] represents the position of the element in the vector, p∈[1,N] represents the parallel path number.

It is worth noting that the principle of step 4.3 is the same as that of step 4.2, the only difference is that the rule vectors used are different. That is to say, any element in the p=1th initial vector r ₁ can be calculated as follows:

The elements in the initial vector r _p of any p-th road are

Wherein, p=2, 3, . . . , N, r _p (0)≡0 and r _p (M+1)≡0 exist.

Step 4.4: According to the zero-boundary 90/150 cellular automata rule, deduce the function recurrence relation c _p (n)=f(c _p ( _n - ₁ )).

The sub-step principle is as follows:

Take the first group of data corresponding to the regular vector d ₁ as an example:

According to the theory of cellular automata, any element s ( m,n) can be calculated according to the following formula under the zero boundary 90/150 rule:

Among them, d(m) is an element in any regular vector d.

Considering that any regular vector d is a known quantity and only has two values of 0 or 1, it can be recursed once according to formula (6), and it can be obtained

That is to say, the state vector s(n+1) at the n+1th moment has nothing to do with the regular vector, and can be expressed by the fixed functional relationship f ₁ by the state vector s(n) at the nth moment, denoted as s(n+1) = f ₁ (s(n)).

In the same way, according to (6) (7) and recursion, the functional relationship f ₂ determined by s(n+2) and s(n) can be obtained, which is recorded as s(n+2)=f ₂ (s (n)).

And so on, after recursing N times, we can get

s(n+N)=f(s(n)) (8)

That is to say, according to the determined functional relationship f, the state vector s(n+N) at the n+Nth time can be directly calculated from the state vector s(n) at the nth time.

Considering that if the cellular automaton is realized by N paths in parallel, the state vector c _p (n)={c _p (m,n),m=1, ...,M; n=0,1,...} should correspond to the state vector at the N×(n-1)+p moment generated by the original serial cellular automaton (6). That is, the following relationship exists:

According to equations (8) and (9), the state vector on the right side of the equal sign satisfies:

s(N×(n-1)+p)=f(s(N×(n-2)+p))

The state vectors c _p (n) and c _p (n-1) realized in parallel in this way also exist:

c _p (n) = f(c _p (n-1)) (10)

That is to say, the state vector c _p (n) of any p-th road and the n-th moment can be calculated from the state vector c _p (n-1) of the previous moment according to the unified functional relationship f, c _p (0)=s _p .

Similarly, the recursive function g of each parallel path under the regular vector d ₂ can be obtained; where, p=1,2,…,N; among them, is the state vector of the p-th road and the n-th moment, is the state vector of the pth road and the n-1th moment,

Step 4.5: Treat the first group of N initial vectors s _p containing M 0, 1 elements generated in step 4.2 as Mbit binary numbers, and generate the first group in FPGA in parallel according to the recursive function relationship f derived in step 4.4 N-way uniform white noise.

The sub-step principle is as follows:

If set is the first group of state vectors generated by any p-th road and n-th moment, then It can be recursively obtained as follows:

Among them, the superscript "1" indicates the first group, n=1,...,∞, p=1,...,N.

When the specific FPGA is implemented, the state vector is first The M elements of 0 and 1 are regarded as Mbit binary numbers, and then deduced according to the functional relationship f determined by (11), so that the Mbit uniform white noise value generated in parallel by the first group can be obtained, which is rewritten as p=1,2,...,N; n=1,2,....

Step 4.6: While step 4.5 is in progress, regard the initial vector r _p containing M 0, 1 elements generated in step 4.3 as an Mbit binary number, and according to the recursive function relationship g derived in step 4.4, generate the first 2 sets of N-channel uniform white noise.

The sub-step principle is as follows:

If set is the second group of uniform white noise generated by any p-th channel and n-th moment, then It can be recursively obtained as follows:

Among them, the superscript "2" indicates the second group, p=1,...,N.

If the state vector M elements of 0 and 1 in Mbit are regarded as Mbit binary numbers, and thus the uniform white noise value generated at the nth moment of the second group can be obtained, which can be rewritten as p=1,2,...,N; n=1,2,....

Step 5: Approximate the Box_Muller algorithm by using non-equal interval segmental polynomial fitting method and CORDIC (Coordinate Rotational Digital Computer, coordinate rotation digital calculation) algorithm, and perform Gaussian processing on the two groups of uniform white noise generated in parallel in step 4 inside the FPGA, Generate N channels of parallel Gaussian white noise, denoted as g _p (n), p=1,2,...,N; n=1,2,....

The Box_Muller algorithm formula is as follows:

Among them, x ₁ and x ₂ are uniformly distributed white noise on (0,1), and there are x ₁ ∈ (0,1) and x ₂ ∈ (0,1), and y is Gaussian white noise.

Step 5.1: The first group of uniform white noise generated according to step 4 Using the non-equal interval piecewise polynomial fitting method to calculate the intermediate results represented by M bits in parallel within the FPGA, which is recorded as:

The specific principles of the sub-steps are as follows:

According to the Box_Muller algorithm, the calculation of the intermediate result y ₁ involves natural logarithm and square root operation. Obviously, if the traditional direct table lookup is adopted, a large amount of storage resources inside the FPGA will inevitably be consumed. For this reason, the present invention adopts non-equal interval piecewise polynomial fitting method to calculate natural logarithm and square root operation.

According to the accuracy requirement of piecewise polynomial fitting, the x ₁ ∈ (0,1) interval is divided into non-equal intervals, and it is divided into K segments in total, denoted as x ₁ ∈ (q _k ,q _k+1 ), where k= 0,1,...,K−1, and there exist q ₀ =0 and q _K =1. For any k-th segment, the cubic polynomial pair function relationship shown in (14) is adopted make an approximation, that is,

According to the functional relationship In the interval of x ₁ ∈ (q _k ,q _k+1 ), sample x ₁ and y ₁ at four points at equal intervals, and establish the following linear equations by formula (14):

X _k A _k = Y _k (15)

Among them, column vector A _k ＝[a _k b _k c _k d _k ] ^T , Y _k ＝[y _k1 y _k2 y _k3 y _k4 ] ^T , and there exists

Solve the above linear equations to obtain the polynomial fitting coefficient A _k of any k-th segment, so that the function value in any x ₁ ∈ (q _k ,q _k+1 ) segment It can be calculated from the polynomial fitting coefficients A _k and x ₁ in the current segment according to formula (14).

Considering that quantization processing is required for the actual implementation of FPGA, the fitting coefficients {A _k ,k=0,1,...,K-1} of K non-equally spaced segments can be calculated according to formula (17) Quantized and stored in FPGA internal memory, namely

in, is the polynomial fitting coefficient after quantization, k∈[0,K-1], N ₁ is the number of digits of expansion, int[ ] means rounding operation, The final quantization is M ₁ bit signed number (the number of decimal places is N ₁ bit).

In this way, according to the first group of Mbit uniform white noise generated in parallel in step 4 and the stored fit coefficients The intermediate results can be calculated in parallel within the FPGA

Taking the calculation of the intermediate result of any p-th path as an example, the FPGA implementation structure is shown in Figure 1.

First, the fitting coefficient lookup table module is based on the uniform white noise A look-up table selects the polynomial coefficients used. For any k ₀ ∈[0,K-1], if the uniform white noise Satisfy:

Then the fitting coefficient lookup table module selects and outputs the kth=k ₀ segment The fitting coefficient of

Subsequently, the third-order polynomial calculation module is based on the uniform white noise and fit coefficient The intermediate result required for this sub-step can be obtained by calculating according to the formula which is

in, Table rounding down operation. The intermediate process of the calculation of the above formula does not perform truncation processing, the calculation result cuts off the low M ₂ bits, and retains the high M bits as the final intermediate result of the Box_Muller algorithm output.

Step 5.2: The second group of Mbit uniform white noise generated in parallel according to step 4 The CORDIC-Coordinate Rotational Digital Computer (CORDIC-Coordinate Rotational Digital Computer) IP core is used to calculate the cos function in parallel in the FPGA, and the Mbit intermediate result is automatically calculated according to the following formula which is

Among them, the superscript "2" indicates the intermediate result of the second group, int[·] indicates the rounding operation, and p∈[1,N],n∈[1,∞).

It is worth noting that when the FPGA is internally implemented, the uniform white noise is quantized into an M bit unsigned number as the phase input of the CORDICIP core, and the output of the IP core Directly quantized to M bit signed number.

Step 5.3: M bit intermediate results generated according to steps 5.1 and 5.2 with In the FPGA, the following formula is used to generate N-channel parallel Gaussian white noise, namely

Among them, p ∈ [1, N], n ∈ [1, ∞). When calculating, two Mbit signed numbers and Multiply, cut off the low M ₃ bits and keep the high M ₀ bits as the final Gaussian white noise g _p (n). Wherein, M ₀ is the effective number of digits of D/A, and M ₃ =M+MM ₀ exists.

It can be seen that after steps 5.1 to 5.3, the present invention uses the non-equal interval segmental polynomial fitting method and the CORDUC algorithm to approximate the Box_Muller algorithm, and the two groups of M bit uniform white noise generated in parallel in step 4 with Gaussian processing is carried out, and Gaussian white noise of N channels M ₀ bits is generated in parallel in the FPGA.

Step 6: Perform parallel-to-serial conversion processing on the N-channel Gaussian white noise generated in step 5 in sequence, and then output the final Gaussian white noise through D/A.

To sum up, the above are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (2)

1. a parallel implementation method of real-time Gaussian white noise hardware generator, is characterized in that, comprises the steps: Step 1, select the cellular automata rule as the zero-boundary 90/150 cellular automata rule, under this rule, calculate the order M of the cellular automata and two reciprocal rules according to the period length of the Gaussian white noise to be generated Vectors d ₁ and d ₂ , where d ₁ ={d ₁ (m),m=1,2,...,M} and d ₂ ={d ₂ (m),m=1,2,... .,M}, elements d ₁ (m) and d ₂ (m) in the regular vector are 0 or 1; Step 2, set the initial vector s ₀ of the cellular automaton as s ₀ ={s ₀ (m),m=1,2,3...,M}, and the initial vector is a non-zero vector; where, the element s ₀ (m) is 0 or 1; Step 3, generate two groups of parallel implementations of uniform white noise inside the FPGA, specifically including the following sub-steps: Step 3.1, according to the sampling frequency f _s of the actual application system and the working clock f _clk of the FPGA, calculate the number of parallel channels in Indicates rounding up; Step 3.2, according to the regular vector d ₁ and the initial vector s ₀ , obtain the initial vector s _p ={s _p (m),m=1,2,...,M} of the parallel paths under the regular vector d ₁ , p=1,2,...,N; Among them, any element s ₁ (m) in the first initial vector s ₁ is: ${\mathrm{<span\; class="notranslate">\; the\; s</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; m</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; the\; s</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; m</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&CirclePlus;</span><span\; class="notranslate">\; \&lsqb;</span>{\mathrm{<span\; class="notranslate">\; d</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; m</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&times;</span>{\mathrm{<span\; class="notranslate">\; the\; s</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; m</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&rsqb;</span><span\; class="notranslate">\; \&CirclePlus;</span>{\mathrm{<span\; class="notranslate">\; the\; s</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; m</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$ Among them, the symbol Express XOR operation, m=1,2,3,...,M; s ₀ (0)≡0, s ₀ (M+1)≡0; The element s _p (m) in the initial vector s _p of any parallel path p is: ${\mathrm{<span\; class="notranslate">\; the\; s</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; m</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; the\; s</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; m</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&CirclePlus;</span><span\; class="notranslate">\; \&lsqb;</span>{\mathrm{<span\; class="notranslate">\; d</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; m</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&times;</span>{\mathrm{<span\; class="notranslate">\; the\; s</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; m</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&rsqb;</span><span\; class="notranslate">\; \&CirclePlus;</span>{\mathrm{<span\; class="notranslate">\; the\; s</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; m</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; p</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; ,</span><span\; class="notranslate">\; ...</span><span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; N</span>}$ And s _p (0)≡0 and s _p (M+1)≡0 Step 3.3, same as step _3.2 , according to the rule vector d ₂ and the initial vector s ₀ , obtain the initial vector r _p ={r _p (m),m=1,2,... ,M}, p=1,2,...,N; Step 3.4, according to the zero-boundary 90/150 cellular automaton rule, deduce the recursive function f of each parallel path under the rule vector d ₁ ; where, p=1,2,…,N; among them, is the state vector of the p-th road and the n-th moment, is the state vector of the pth road and the n-1th moment, Similarly, the recursive function g of each parallel path under the regular vector d ₂ is obtained; where, p=1,2,…,N; among them, is the state vector of the p-th road and the n-th moment, is the state vector of the pth road and the n-1th moment, In step 3.5, the N initial vectors s _p generated in step 3.2 and the N initial vectors r _p generated in step 3.3 are respectively regarded as two sets of Mbit binary numbers, and according to the recursive function relationship f and g derived in step 3.4, in the FPGA Generate 2 groups of N-channel uniform white noise in parallel with p=1,2,...,N; Step 4: Generate parallel N-way Gaussian white noise, specifically including the following steps: Step 4.1, for the first group of uniform white noise generated in step 3 Using non-equal interval piecewise polynomial fitting method for Box_Muller algorithm Perform fitting to obtain the fitting coefficients of each non-equal interval segment; quantize the fitting coefficients and store them in the internal memory of the FPGA; inside the FPGA, the first group of M bits generated in parallel in step 3 according to the stored fitting coefficients uniform white noise Perform parallel polynomial calculations and intercept high M bits as intermediate results Step 4.2, for the second group of uniform white noise generated in step 3 According to the formula y ₂ =cosx ₂ in the Box_Muller algorithm, use the CORDIC IP core parallel calculation inside the FPGA to generate M bit intermediate results Step 4.3: Generate p-th Gaussian white noise g _p (n) in parallel in the FPGA, p=1, 2,..., N: in the p-th path, two Mbit and Multiply, and intercept the high M ₀ bit of the product result as the Gaussian white noise g _p (n) that is finally generated; where M ₀ is the effective number of digits of the digital-to-analog converter; Step 5: After parallel-to-serial conversion processing is performed on the N-channel Gaussian white noise generated in step 4, the final Gaussian white noise is generated through digital-to-analog conversion. 2. the parallel realization method of real-time Gaussian white noise hardware generator as claimed in claim 1, is characterized in that, in described step 1, regular vector obtains by Euclidean algorithm or look-up table.