CN106774624A - A kind of Parallel Implementation method of real-time white Gaussian noise hardware generator - Google Patents

Abstract

The invention discloses a kind of Parallel Implementation method of real-time white Gaussian noise hardware generator.Using the present invention can realize white Gaussian noise hardware generator in real time, at high speed, the high-quality white Gaussian noise of parallel generation.The present invention is primarily based on the FPGA high-speed parallels realization of the uniform white noise of cellular automaton theory, gives the recurrence function relation of the computational methods of N roads initial vector and cellular automaton parallel generation algorithm needed for Parallel Implementation；Then, give Box_Muller algorithms a kind of approach method of low complex degree, Box_Muller algorithms are reduced to simple multiply-add and CORDIC computings, only need to expend a small amount of multiplier and logical resource when FPGA is realized, so as to can under relatively low FPGA resource consumption, in real time, at high speed the generation cycle it is long, with the measured white Gaussian noise of roomy, matter.

Description

A kind of Parallel Implementation method of real-time white Gaussian noise hardware generator

Technical field

The present invention relates to wireless channel simulation, noise modeling technical field, and in particular to a kind of real-time white Gaussian noise is hard The Parallel Implementation method of part generator.

Background technology

Wireless channel simulation technology on ground due to that can reappear an ideal, deterioration, even almost real electric wave biography Environment is broadcast, when analog channel is various, the influence propagated signal of space-variant, already can not as technical fields such as communication, observing and controlling The validation test means for lacking.Compared to wire message way, wireless channel is a kind of badness-media of radio wave propagation, with it is random, The complex characteristics such as unpredictable.Radio wave during transmission, can unavoidably be subject to noise jamming, channel fading, Ionospheric scintillation, dynamic rain such as decline at the influence of random non-ideal characteristic.In order to study these non-ideal characteristics to radio wave propagation Influence, domestic and foreign scholars generally by white Gaussian noise modeling based on, then by various complex transformations linearly or nonlinearly come Other non-ideal characteristics to channel are modeled analysis.It can be seen that, white Gaussian noise is that the random non-ideal characteristic of wireless channel grinds The most important thing studied carefully, research white Gaussian noise is theoretical and implementation method is modeled to characteristics of radio channels, emulation and simulation are respectively provided with Significance.

Research data shows that white Gaussian noise is mostly to carry out Gaussian to equally distributed white noise by some algorithms Produced after treatment and obtained.At this stage, the production method of uniform white noise mainly includes linear congruent algorithm, postpones Fibonacci Method, linear shift register method and cellular automaton theory etc..Linear congruential method with postpone Fibonacci method compared with, the former with Effect is poor in the performance tests such as uniformity, the subsequence dependence of the distribution of machine number, but the latter needs more multiplier Resource, FPGA (Field Programmable Gate Array) hardware resource consumption is big.Linear shift register method is current A kind of most widely used method, realizes etc. that protrusion is excellent with algorithm is simple, speed fast, repeatability is strong and is easy to FPGA hardware Point.However, because the method has linear feedback structure, can cause its pseudo random number for producing that there is stronger correlation, Even white noise produces quality relatively poor.Comparatively speaking, cellular automaton theory is the product for being just used for uniform white noise in recent years It is raw, because its noise for producing has the outstanding advantages such as the cycle is long, speed is fast, statistical property good, realization occupancy hardware resource is few, The extensive concern for just receiving domestic and foreign scholars once coming out.

In terms of white Gaussian noise generating algorithm, at present mainly include cumulative distribution function inverse transformation method, refuse-receive method And uniform white noise converter technique etc..The basic thought of cumulative distribution function inverse transformation method is by the accumulation of any given stochastic variable Distribution function does anti-change, so as to obtain the corresponding stochastic variable of the cumulative distribution function.The method is directly perceived, be readily appreciated that, but Need to store the mapping relations between non-linear Gauss cumulative distribution function and white Gaussian noise when hardware is realized, can be inevitable Ground takes a large amount of storage resources.The basic thought of refusal-Receiving is come produced by determining according to some given criterions Stochastic variable whether belong to white Gaussian noise and then decide what to use.However, because the method is needed using cycling condition to defeated Enter variable to be differentiated, give up those it is converted after can not produce the data of white Gaussian noise, thus its is inefficient, and uncomfortable Suitable hardware is realized.Comparatively speaking, uniform white noise converter technique need not solve the inverse transformation of cumulative distribution function, by uniform point The white noise of cloth directly become and brings generation white Gaussian noise.At present, this kind of method is most widely used, mainly including Box- Muller algorithms, central-limit theorem summation, Monty Python algorithms and the piecewise approximation based on angular distribution etc..

In terms of Gaussian white noise generator, the Gaussian white noise generator of early stage is mostly based on computer software carries out reality It is existing, just occur different types of white Gaussian noise hardware generator successively until eighties of last century the 80s and 90s.For example, being based on The white Gaussian noise hardware generator of Ziggurat algorithms, the white Gaussian noise hardware generator based on Box-Muller algorithms and Based on white Gaussian noise hardware generator for postponing Fibonacci design method and central-limit theorem etc..However, above-mentioned hardware occurs The FPGA resource consumption that the research emphasis of device essentially consist in as how relatively low generates high-quality white Gaussian noise, but have ignored height The formation speed of this white noise.Particularly, with broadband, the continuous appearance of radio ultra wide band system, such as how relatively low hardware resource Consumption, generates high-quality white Gaussian noise and seems most important in real time, at high speed.Therefore, the height of white Gaussian noise is studied Speed, parallel generation algorithm and Hardware Implementation are significant.

The content of the invention

In view of this, the invention provides a kind of Parallel Implementation method of real-time white Gaussian noise hardware generator, it is based on Cellular automaton theory and Box_Muller algorithms, realize giving birth in real time, at high speed, parallel for white Gaussian noise hardware generator Into high-quality white Gaussian noise.

The Parallel Implementation method of real-time white Gaussian noise hardware generator of the invention, comprises the following steps：

Step 1, it is the cellular automaton of null boundary 90/150 rule to select cellular automaton rule, under this rule, according to The Cycle Length for intending generation white Gaussian noise calculates the order M and two reciprocal regular vector d for obtaining cellular automaton₁And d₂, Wherein, d₁={ d₁(m), m=1,2 ..., M } and d₂={ d₂(m), m=1,2 ..., M }, the element d in rule vector₁(m) and d₂M () is 0 or 1；

Step 2, sets the initial vector s of cellular automaton₀It is s₀={ s₀(m), m=1,2,3..., M }, and initial vector It is non-vanishing vector；Wherein, element s₀M () is 0 or 1；

Step 3, produces two groups of uniform white noises of Parallel Implementation inside FPGA, specifically includes following sub-step：

Step 3.1, the sample frequency f according to real application systems_sWith the work clock f of FPGA_clk, calculate parallel wayWhereinExpression rounds up；

Step 3.2, according to regular vector d₁With initial vector s₀, obtain regular vector d₁Under parallel each road it is initial to Amount s_p={ s_p(m), m=1,2 ..., M }, p=1,2 ..., N；

Wherein, the 1st road initial vector s₁Middle arbitrary element s₁M () is：

Wherein, symbolTable XOR, m=1,2,3 ..., M；s₀(0) ≡ 0, s₀(M+1)≡0；

Any parallel pth road initial vector s_pMiddle element s_pM () is：

And s_p(0) ≡ 0 and s_p(M+1)≡0

Step 3.3, with step 3.2, according to regular vector d₂With initial vector s₀, obtain regular vector d₂Under it is parallel each The initial vector r on road_p={ r_p(m), m=1,2 ..., M }, p=1,2 ..., N；

Step 3.4, according to the cellular automaton of null boundary 90/150 rule, is derived by regular vector d₁Under parallel each road Recurrence function f；Wherein,P=1,2 ..., N；Wherein,It is pth road, the state at the n-th moment Vector,It is pth road, the state vector at the (n-1)th moment,

Likewise, obtaining regular vector d₂Under parallel each road recurrence function g；Wherein,P= 1,2,…,N；Wherein,It is pth road, the state vector at the n-th moment,For pth road, the state at the (n-1)th moment to Amount,

Step 3.5, N number of initial vector s that step 3.2 is produced_pThe N number of initial vector r produced with step 3.3_pRegard respectively It is two groups of binary numbers of Mbit, according to recurrence function relation f and g that step 3.4 is derived, 2 groups of N roads of parallel generation in FPGA Uniform white noiseWithP=1,2 ..., N；

Step 4：The white Gaussian noise on parallel N roads is generated, following steps are specifically included：

Step 4.1, for the 1st group of uniform white noise of step 3 generationIntended using unequal interval piecewise polynomial In the legal algorithm to Box_MullerIt is fitted, obtains the fitting coefficient of each unequal interval segmentation；To intend Stored after syzygy quantification to FPGA internal storages；Inside FPGA, step 3 is produced parallel according to the fitting coefficient for having stored The 1st group of raw Mbit uniform white noiseParallel polynomial computation is carried out, and intercepts Mbit high as intermediate result

Step 4.2, for the 2nd group of uniform white noise of step 3 generationAccording to the public affairs in Box_Muller algorithms Formula y₂=cosx₂, M bit intermediate results are generated using the parallel computation of CORDIC IP kernels inside FPGA

Step 4.3：The parallel generation pth road white Gaussian noise g inside FPGA_p(n), p=1,2 ..., N：On pth road, will Two Mbit'sWithIt is multiplied, and result of product is intercepted into M high₀Bit is used as the white Gaussian noise g for ultimately generating_p (n)；Wherein, M₀It is the number of significant digit of D/A converter；

Step 5：After carrying out parallel-serial converter treatment in order to the N roads white Gaussian noise that step 4 is generated, through digital-to-analogue conversion Produce final white Gaussian noise.

Further, in the step 1, rule vector is obtained by Euclidean algorithm or table look-up.

Beneficial effect：

Present invention contrast prior art, has the following advantages that：

First, it is proposed that the uniform white noise parallel generation algorithm based on cellular automaton theory and the realization based on FPGA Method.On the basis of cellular automaton theory, the present invention is according to uniform white noise Cycle Length, the height of real system that need to be produced Fast sample frequency and FPGA tick-over clocks, give the choosing method of cellular automaton rule, order and parallel way, push away The recurrence function for having led the computational methods of N roads initial vector and cellular automaton parallel generation algorithm needed for Parallel Implementation is closed System, finally gives the FPGA high-speed parallel implementation methods of the uniform white noise based on cellular automaton.Therefore, the present invention is carried Method has taken into account the plurality of advantages that cellular automaton theory generates uniform white noise, such as the cycle is long, speed is fast, statistical property good, Realize that occupancy hardware resource lacks, while drastically increasing the real-time and formation speed of uniform white noise.

Then, give Box_Muller algorithms a kind of approach method of low complex degree.The method is using unequal interval point The multinomial of section approaches logarithm and extracting operation in original Box_Muller algorithms, and Box_ is carried out using cordic algorithm Cos computings in Muller algorithms.Approached by above-mentioned, Box_Muller algorithms can be reduced to simple multiply-add and CORDIC fortune Calculate, only need to expend a small amount of multiplier and logical resource when FPGA is realized, be particularly well-suited to high speed, the product of paralleling gauss white noise It is raw.

In sum, institute's extracting method of the present invention, can be in relatively low FPGA compared with existing white Gaussian noise hardware generator Under resource consumption, in real time, at high speed generation the cycle it is long, with the measured white Gaussian noise of roomy, matter.

Brief description of the drawings

Fig. 1 realizes structure for any parallel pth road intermediate result 1 is calculated.

Fig. 2 is the structured flowchart of white Gaussian noise hardware generator of the present invention.

Specific embodiment

Develop simultaneously embodiment below in conjunction with the accompanying drawings, and the present invention will be described in detail.

The invention provides a kind of Parallel Implementation method of real-time white Gaussian noise hardware generator, based on cellular automaton Theoretical and Box_Muller algorithms, can it is parallel on FPGA, in real time, generate high-quality white Gaussian noise at high speed.This hair It is bright first according to noise periods length, the high-speed sampling frequency of real system and FPGA tick-over clocks etc., determine cell from The order of motivation, regular and parallel way；Then, according to cellular automaton order and rule, using Euclidean algorithm or look into Table obtains two reciprocal rule vectors；Meanwhile, according to cellular automaton theory, derived by the non-zero initial vector for arbitrarily setting N roads initial vector required during Parallel Implementation and function recurrence relation, and two groups of uniform white noises are generated inside FPGA；Most Afterwards, Box_Muller algorithms are approached using unequal interval fitting of a polynomial and cordic algorithm, it is uniform to parallel two groups for producing White noise carries out Gaussian treatment, and final white Gaussian noise is produced by being put outside parallel-serial converter and D/A.

Comprise the following steps that：

Step 1：The Cycle Length of white Gaussian noise is produced as needed, determines the rule and order of cellular automaton.

It is more long in order to be generated with relatively low cellular automaton order if the Cycle Length for needing to produce white Gaussian noise is L The uniform white noise in cycle, present invention selection null boundary 90/150 cellular automaton rule.Under this cellular automaton rule, rank Secondary M is calculated as follows：

Wherein,Expression rounds up operation.

Step 2：The cellular automaton of null boundary 90/150 rule and order M determined according to step 1, can be by Euclid Algorithm or table look-up obtains two reciprocal rule vectors of M rank cellular automatons, is denoted as respectively：d₁={ d₁(m), m=1, 2 ..., M } and d₂={ d₂(m), m=1,2 ..., M }, wherein element only exists 0 and 1 two kind of possibility, i.e. d in rule vector₁ (m) ∈ { 0,1 } and d₂(m)∈{0,1}。

Step 3：The non-vanishing vector of any M element is set as the initial vector of cellular automaton, wherein each element Only 0 or 1 two kind of value, it is denoted as s₀={ s₀(m), m=1,2,3..., M }, wherein m represents the position of element in vector, and deposits In s₀(m)∈{0,1}。

Step 4：According to cellular automaton rule, order M, regular vector d₁And d₂, initial vector s₀, derive cell automatic The Parallel Implementation algorithm of machine, and two groups of uniform white noises of Parallel Implementation are produced inside FPGA.

It is specific as follows：

Step 4.1：Sample frequency f according to real application systems_sThe work clock to be used is realized with FPGA hardware f_clk, calculate parallel wayWhereinExpression rounds up operation.

Step 4.2：According to regular vector d₁With initial vector s₀, by cellular automaton theory recursion generation Parallel Implementation institute The 1st group of N number of initial vector for needing, is designated as s_p={ s_p(m), m=1,2 ..., M；P=1,2 ..., N }, wherein m ∈ [1, M] table Show the position of element in vector, p ∈ [1, N] represent parallel way.

This step by step concrete principle it is as follows：

According to cellular automaton theory, the initial vector s on parallel pth=1 tunnel₁Middle arbitrary element s₁M () can be by regular vector d₁With initial vector s₀Middle element is calculated as follows：

Wherein, symbolTable XOR, vector element position m=1,2,3 ..., M.According to the cell of null boundary 90/150 , there is s in automatic machine rule₀(0) ≡ 0 and s₀(M+1)≡0。

Similarly, any parallel pth road initial vector s_pMiddle element can be by the road of pth -1 initial vector s_p-₁Middle element and rule Vectorial d₁It is calculated as follows：

Wherein, there is s in p=2,3 ..., N_p(0) ≡ 0 and s_p(M+1)≡0。

Therefore, according to regular vector d₁With initial vector s₀, as needed for recursion by (2) and (3) formula obtains Parallel Implementation N number of initial vector s_p={ s_p(m), m=1,2 ..., M, p=1,2 ..., N }.

Step 4.3：Similarly, according to regular vector d₂With initial vector s₀, it is parallel real by the generation of cellular automaton theory recursion Existing the 2nd group of required N number of initial vector, is designated as r_p={ r_p(m), m=1,2 ..., M；P=1,2 ..., N }, wherein m ∈ [1, M] position of element in vector is represented, p ∈ [1, N] represent parallel way.

What deserves to be explained is, step 4.3 principle is identical with step 4.2 principle, and difference is only that rule vector used not Together.I other words, pth=1 road initial vector r₁Middle arbitrary element can be calculated as follows：

Any pth road initial vector r_pMiddle element is

Wherein, there is r in p=2,3 ..., N_p(0) ≡ 0 and r_p(M+1)≡0。

Step 4.4：According to the cellular automaton of null boundary 90/150 rule, regular vector d during Parallel Implementation is derived₁、d₂Under The function recurrence relation c on any pth road_p(n)=f (c_p(n-1))。

This step by step principle it is as follows：

With regular vector d₁Corresponding 1st group of data instance：

According to cellular automaton theory, any n-th moment state vector s (n)={ s (m, n), m=1 ..., M；N=0, 1 ... } in arbitrary element s (m, n) can be calculated as follows under the rule of null boundary 90/150：

Wherein, d (m) is element in any regular vector d.

It is known quantity and to only exist 0 or 1 two kind of value in view of any regular vector d, therefore by (6) formula recursion 1 time, can

I other words, the state vector s (n+1) at the (n+1)th moment is unrelated with regular vector, can be by the n-th moment state vector s N () is by fixed functional relation f₁Represent, be designated as s (n+1)=f₁(s(n))。

Similarly, recursion is carried out according to (6) (7) two formula again, the functional relation f that s (n+2) and s (n) determines can be obtained₂, it is designated as S (n+2)=f₂(s(n))。

The like, after recursion n times, can obtain

S (n+N)=f (s (n)) (8)

I other words, the n-th+N can be directly calculated by state vector s (n) at the n-th moment according to the functional relation f for determining The state vector s (n+N) at moment.

If in view of cellular automaton by N roads Parallel Implementation, any pth road, the n-th moment Parallel Implementation cellular automaton Produced state vector c_p(n)={ c_p(m, n), m=1 ..., M；N=0,1 ... } original serial cellular automaton should be corresponded to (6) state vector at N × (n-1)+p moment that formula is produced.I other words, there is following relation：

It can be seen from (8) and (9) formula, equal sign the right state vector meets：

S (N × (n-1)+p)=f (s (N × (n-2)+p))

So state vector c of Parallel Implementation_p(n) and c_p(n-1) equally exist：

c_p(n)=f (c_p(n-1)) (10)

I other words, any pth road, the state vector c at the n-th moment_pN () can be by the state vector c of previous moment_p(n-1) press Unified functional relation f is calculated, c_p(0)=s_p。

Likewise, regular vector d can be obtained₂Under parallel each road recurrence function g；Wherein, P=1,2 ..., N；Wherein,It is pth road, the state vector at the n-th moment,It is pth road, the state at the (n-1)th moment Vector,

Step 4.5：The 1st group of N number of initial vector s containing individual 0,1 elements of M that step 4.2 is produced_pIt is considered as Mbit binary systems Number, according to the recurrence function relation f that step 4.4 is derived, the 1st group of N roads uniform white noise of parallel generation in FPGA.

This step by step principle it is as follows：

If settingFor any pth road, the n-th moment produce 1st group of state vector, thenRecursion can obtain as the following formula：

Wherein, subscript " 1 " represents the 1st group,N=1 ..., ∞, p=1 ..., N.

When specific FPGA is realized, first by state vectorMiddle M 0,1 element regards Mbit binary numbers as, then by (11) The functional relation f that formula determines carries out recursion, and thus the i.e. available 1st group of parallel Mbit uniform white noise value for producing, is designated as againP=1,2 ..., N；N=1,2 ....

Step 4.6：While step 4.5 is carried out, the initial vector r containing individual 0,1 elements of M that step 4.3 is produced_pSee Make Mbit binary numbers, according to the recurrence function relation g that step 4.4 is derived, the 2nd group of N road of parallel generation is uniformly white in FPGA Noise.

This step by step principle it is as follows：

If settingFor any pth road, the n-th moment produce 2nd group of uniform white noise, thenRecursion can obtain as the following formula：

Wherein, subscript " 2 " represents the 2nd group,P=1 ..., N.

If by state vectorMiddle M 0,1 element regards Mbit binary numbers as, thus obtains final product the 2nd group of the n-th moment generation Uniform white noise value, be designated as againP=1,2 ..., N；N=1,2 ....

Step 5：Using unequal interval piecewise polynomial fitting method and CORDIC (Coordinate Rotational Digital Computer, Coordinate Rotation Digital is calculated) algorithm approached Box_Muller algorithms, to step inside FPGA The rapid 4 parallel 2 groups of uniform white noises for producing carry out Gaussian treatment, and generation N roads paralleling gauss white noise is denoted as g_p(n), p= 1,2,...,N；N=1,2 ....

Box_Muller algorithmic formulas are as follows：

Wherein, x₁And x₂It is equally distributed white noise on (0,1), and there is x₁∈ (0,1) and x₂∈ (0,1), y are height This white noise.

Step 5.1：According to the 1st group of uniform white noise that step 4 is generatedUsing unequal interval piecewise polynomial fitting The method intermediate result that parallel computation is represented by M bit inside FPGA, is designated as：

This step by step concrete principle it is as follows：

It can be seen from Box_Muller algorithms, intermediate result y₁Calculating be related to natural logrithm and extracting operation.Obviously, The substantial amounts of storage resource in FPGA inside can be inevitably consumed according to traditional table look-at.Therefore, the present invention is using non- Piecewise polynomial fitting method calculates natural logrithm and extracting operation at equal intervals.

According to the required precision of piecewise polynomial fitting, to x₁∈ (0,1) interval carries out unequal interval division, is divided into altogether K sections, it is designated as x₁∈(q_k,q_k+1), wherein k=0,1 ..., K-1, and there is q₀=0 and q_K=1.For any k-th segmentation Speech, using the cubic polynomial shown in (14) formula to functional relationApproached, i.e.,

According to functional relationIn x₁∈(q_k,q_k+1) interval interior to x₁And y₁4 equal interval samplings are carried out, Following system of linear equations is set up by (14) formula：

X_kA_k=Y_k (15)

Wherein, column vector A_k=[a_k b_k c_k d_k]^T, Y_k=[y_k1 y_k2 y_k3 y_k4]^T, and exist

Solve the coefficient of polynomial fitting A that above-mentioned system of linear equations obtains any k-th segmentation_k, so any x₁∈(q_k, q_k+1) functional value in segmentationCan be by the coefficient of polynomial fitting A in current fragment_kAnd x₁Based on (14) formula Obtain.

Quantification treatment need to be carried out when being implemented in view of FPGA, is that this can first to the K fitting system of unequal interval segmentation Number { A_k, k=0,1 ..., K-1 } quantified by (17) formula and stored to FPGA internal storages, i.e.,

Wherein,It is the coefficient of polynomial fitting after quantization, k ∈ [0, K-1], N₁To expand position digit, int [] represents four House five enters operation,Final quantization is M₁(fractional part digit is N to bit signed numbers₁bit)。

So, the 1st group of Mbit uniform white noise for being produced parallel according to step 4The fitting coefficient for having stored Can inside FPGA parallel computation intermediate result

By taking the calculating of any pth road intermediate result as an example, FPGA realizes that structure is as shown in Figure 1.

First, fitting coefficient look-up table means are according to uniform white noiseTable look-up and select multinomial coefficient used.It is right In any k₀∈ [0, K-1], if uniform white noiseMeet：

Then fitting coefficient look-up table means selection exports kth=k₀Individual segmentationFitting coefficient

Then, three rank multinomial computing modules are according to uniform white noiseAnd fitting coefficient It is calculated as follows the intermediate result needed for can obtain well-behaved stepI.e.

Wherein,The downward floor operation of table.The pilot process that above formula is calculated does not carry out cut position treatment, and result of calculation cuts out Low M₂Bit, retain the intermediate result of Mbit high as final Box_Muller algorithmsOutput.

Step 5.2：According to the 2nd group of Mbit uniform white noise that step 4 is produced parallelUsing seat inside FPGA Mark rotary digital calculates (CORDIC-Coordinate Rotational Digital Computer) IP kernel parallel computation cos Function, and automatic calculating generates Mbit intermediate results as the following formulaI.e.

Wherein, subscript " 2 " represents the 2nd group of intermediate result, and int [] represents round up operation, and p ∈ [1, N], n ∈ [1,∞)。

What deserves to be explained is, when being realized inside FPGA, uniform white noise is quantified as M bit unsigned numbers as CORDIC The phase input of IP kernel, the output of IP kernelDirectly it is quantified as M bit signed numbers.

Step 5.3：According to step 5.1 and the 5.2 M bit intermediate results for producingWithPressed inside FPGA Formula is calculated and produces N roads paralleling gauss white noise, i.e.,

Wherein, p ∈ [1, N], n ∈ [1, ∞).During calculating, two Mbit signed numbersWithIt is multiplied, by result Cut out low M₃Bit, reservation M high₀Bit is used as the white Gaussian noise g for ultimately generating_p(n).Wherein, M₀It is the number of significant digit of D/A, and There is M₃=M+M-M₀。

It can be seen that, by step 5.1 to 5.3, the present invention uses unequal interval piecewise polynomial fitting method and CORDUC algorithms Box_Muller algorithms are approached, and to two groups of M bit uniform white noises of step 4 parallel generationWith Gaussian treatment is carried out, N roads M has been generated parallel inside FPGA₀The white Gaussian noise of bit.

Step 6：After carrying out parallel-serial converter treatment in order to the N roads white Gaussian noise that step 5 is generated, through putting product outside D/A The final white Gaussian noise of life.

In sum, presently preferred embodiments of the present invention is these are only, is not intended to limit the scope of the present invention. All any modification, equivalent substitution and improvements within the spirit and principles in the present invention, made etc., should be included in of the invention Within protection domain.

Claims (2)

1. a kind of Parallel Implementation method of real-time white Gaussian noise hardware generator, it is characterised in that comprise the following steps：

Step 1, it is the cellular automaton of null boundary 90/150 rule to select cellular automaton rule, under this rule, is given birth to according to plan Cycle Length into white Gaussian noise calculates the order M and two reciprocal regular vector d of acquisition cellular automaton₁And d₂, its In, d₁={ d₁(m), m=1,2 ..., M } and d₂={ d₂(m), m=1,2 ..., M }, the element d in rule vector₁(m) and d₂ M () is 0 or 1；

Step 2, sets the initial vector s of cellular automaton₀It is s₀={ s₀(m), m=1,2,3..., M }, and initial vector is non- Null vector；Wherein, element s₀M () is 0 or 1；

Step 3, produces two groups of uniform white noises of Parallel Implementation inside FPGA, specifically includes following sub-step：

Step 3.1, the sample frequency f according to real application systems_sWith the work clock f of FPGA_clk, calculate parallel wayWhereinExpression rounds up；

Step 3.2, according to regular vector d₁With initial vector s₀, obtain regular vector d₁Under parallel each road initial vector s_p= {s_p(m), m=1,2 ..., M }, p=1,2 ..., N；

Wherein, the 1st road initial vector s₁Middle arbitrary element s₁M () is：

$s_1\left(m\right)=s_0(m-1)\⊕\[d_1\left(m\right)\×s_0\left(m\right)\]\⊕s_0(m+1)$

Wherein, symbolTable XOR, m=1,2,3 ..., M；s₀(0) ≡ 0, s₀(M+1)≡0；

Any parallel pth road initial vector s_pMiddle element s_pM () is：

$s_p\left(m\right)=s_{p-1}(m-1)\⊕\[d_1\left(m\right)\×s_{p-1}\left(m\right)\]\⊕s_{p-1}(m+1),p=2,3,...,N$

And s_p(0) ≡ 0 and s_p(M+1)≡0

Step 3.3, with step 3.2, according to regular vector d₂With initial vector s₀, obtain regular vector d₂Under parallel each road Initial vector r_p={ r_p(m), m=1,2 ..., M }, p=1,2 ..., N；

Step 3.4, according to the cellular automaton of null boundary 90/150 rule, is derived by regular vector d₁Under parallel each road pass Push away function f；Wherein,P=1,2 ..., N；Wherein,It is pth road, the state vector at the n-th moment,It is pth road, the state vector at the (n-1)th moment,

Likewise, obtaining regular vector d₂Under parallel each road recurrence function g；Wherein,P=1, 2,…,N；Wherein,It is pth road, the state vector at the n-th moment,It is pth road, the state vector at the (n-1)th moment,

Step 3.5, N number of initial vector s that step 3.2 is produced_pThe N number of initial vector r produced with step 3.3_pIt is respectively seen as two The binary number of group Mbit, according to recurrence function relation f and g that step 3.4 is derived, 2 groups of N roads of parallel generation are uniform in FPGA White noiseWithP=1,2 ..., N；

Step 4：The white Gaussian noise on parallel N roads is generated, following steps are specifically included：

Step 4.1, for the 1st group of uniform white noise of step 3 generationUsing unequal interval piecewise polynomial fitting method pair In Box_Muller algorithmsIt is fitted, obtains the fitting coefficient of each unequal interval segmentation；By fitting coefficient Stored after quantization to FPGA internal storages；Inside FPGA, the produced parallel to step 3 according to the fitting coefficient for having stored 1 group of M bit uniform white noiseParallel polynomial computation is carried out, and intercepts M bit high as intermediate result

Step 4.2, for the 2nd group of uniform white noise of step 3 generationFormula y in Box_Muller algorithms₂= cosx₂, M bit intermediate results are generated using the parallel computation of CORDIC IP kernels inside FPGA

Step 4.3：The parallel generation pth road white Gaussian noise g inside FPGA_p(n), p=1,2 ..., N：On pth road, by two M Bit'sWithIt is multiplied, and result of product is intercepted into M high₀Bit is used as the white Gaussian noise g for ultimately generating_p(n)；Its In, M₀It is the number of significant digit of D/A converter；

Step 5：After carrying out parallel-serial converter treatment in order to the N roads white Gaussian noise that step 4 is generated, produced through digital-to-analogue conversion Final white Gaussian noise.

2. the Parallel Implementation method of white Gaussian noise hardware generator in real time as claimed in claim 1, it is characterised in that described In step 1, rule vector is obtained by Euclidean algorithm or table look-up.