CN106774624A - A kind of Parallel Implementation method of real-time white Gaussian noise hardware generator - Google Patents

Abstract

The invention discloses a kind of Parallel Implementation method of real-time white Gaussian noise hardware generator.Using the present invention can realize white Gaussian noise hardware generator in real time, at high speed, the high-quality white Gaussian noise of parallel generation.The present invention is primarily based on the FPGA high-speed parallels realization of the uniform white noise of cellular automaton theory, gives the recurrence function relation of the computational methods of N roads initial vector and cellular automaton parallel generation algorithm needed for Parallel Implementation；Then, give Box_Muller algorithms a kind of approach method of low complex degree, Box_Muller algorithms are reduced to simple multiply-add and CORDIC computings, only need to expend a small amount of multiplier and logical resource when FPGA is realized, so as to can under relatively low FPGA resource consumption, in real time, at high speed the generation cycle it is long, with the measured white Gaussian noise of roomy, matter.

Description

Parallel implementation method of real-time Gaussian white noise hardware generator

Technical Field

The invention relates to the technical field of wireless channel simulation and noise modeling, in particular to a parallel implementation method of a real-time Gaussian white noise hardware generator.

Background

Because an ideal, deteriorated and even nearly real radio wave propagation environment can be reproduced on the ground by the wireless channel simulation technology, the wireless channel simulation technology simulates the influence of various time and space changes of a channel on signal propagation, and has already become an indispensable verification test means in the technical fields of communication, measurement and control and the like. Compared with a wired channel, a wireless channel is a poor medium for radio wave propagation and has complex characteristics of randomness, unpredictability and the like. During the channel transmission process, radio waves are inevitably affected by random non-ideal characteristics such as noise interference, channel fading, ionospheric scintillation, dynamic rain attenuation and the like. In order to study the influence of these non-ideal characteristics on the propagation of radio waves, domestic and foreign scholars usually model and analyze other non-ideal characteristics of a channel through various linear or non-linear complex transformations based on gaussian white noise modeling. It can be seen that the gaussian white noise is the important point in the research of the random non-ideal characteristics of the wireless channel, and the research of the gaussian white noise theory and the implementation method have important significance in modeling, simulating and simulating the characteristics of the wireless channel.

Research data show that the gaussian white noise is mostly generated by gaussian processing of white noise which is uniformly distributed through some algorithms. At present, the generation method of uniform white noise mainly comprises a linear congruence algorithm, a delay Fibonacci method, a linear shift register method, a cellular automaton theory and the like. Compared with the delayed Fibonacci method, the linear congruence method has a poor effect in performance tests such as uniformity of random number distribution, subsequence dependence relationship and the like, but the delayed Fibonacci method needs more multiplier resources, and FPGA (field Programmable Gate array) hardware resources are consumed greatly. The linear shift register method is the most widely applied method at present, and has the outstanding advantages of simple algorithm, high speed, strong repeatability, easy FPGA hardware realization and the like. However, due to the existence of a linear feedback structure in the method, the generated pseudo random numbers have strong correlation, and the quality of uniform white noise generation is relatively poor. In contrast, the cellular automata theory is used for generating uniform white noise in recent years, and the generated noise has the outstanding advantages of long period, high speed, good statistical property, less occupied hardware resources and the like, so that the cellular automata theory has been widely concerned by scholars at home and abroad once the noise is produced.

In the aspect of gaussian white noise generation algorithm, the method mainly includes an inverse cumulative distribution function transform method, a rejection-acceptance method, a uniform white noise transform method, and the like. The basic idea of the cumulative distribution function inverse transformation method is to inverse transform the cumulative distribution function of any given random variable, thereby obtaining the random variable corresponding to the cumulative distribution function. The method is intuitive and easy to understand, but the mapping relation between the nonlinear Gaussian cumulative distribution function and the Gaussian white noise needs to be stored when the hardware is realized, and a large amount of storage resources are inevitably occupied. The basic idea of the reject-receive method is to decide to accept or reject the generated random variable by determining whether it belongs to white gaussian noise according to some given criteria. However, this method is not efficient and is not suitable for hardware implementation because it needs to use a cyclic condition to discriminate the input variables and discard the data that cannot generate white gaussian noise after conversion. In contrast, the uniform white noise transform method generates white gaussian noise by directly transforming uniformly distributed white noise without solving the inverse transform of the cumulative distribution function. At present, the method is most widely applied and mainly comprises a Box-Muller algorithm, a central limit theorem cumulative addition method, a Monty Python algorithm, a segment approximation method based on triangular distribution and the like.

In the context of white gaussian noise generators, early white gaussian noise generators were mostly implemented on a computer software basis, and until the eight ninety years of the last century, hardware generators of different kinds of white gaussian noise were continuously emerging. For example, a hardware generator of white gaussian noise based on Ziggurat algorithm, a hardware generator of white gaussian noise based on Box-Muller algorithm, a hardware generator of white gaussian noise based on delayed fibonacci algorithm and central limit theorem, etc. However, the above hardware generator is mainly focused on how to generate high-quality white gaussian noise with low FPGA resource consumption, but neglects the generation speed of white gaussian noise. In particular, with the continuous emergence of wideband and ultra-wideband systems, it is important to generate high-quality white gaussian noise in real time at high speed with low hardware resource consumption. Therefore, the research on the high-speed parallel generation algorithm and the hardware realization method of the Gaussian white noise has important significance.

Disclosure of Invention

In view of this, the invention provides a parallel implementation method of a real-time white gaussian noise hardware generator, which is based on the cellular automata theory and the Box _ Muller algorithm to implement real-time, high-speed and parallel generation of high-quality white gaussian noise by the white gaussian noise hardware generator.

The invention discloses a parallel realization method of a real-time Gaussian white noise hardware generator, which comprises the following steps:

step 1, selecting a cellular automata rule as a zero boundary 90/150 cellular automata rule, and under the rule, calculating according to the cycle length of pseudo-generated white Gaussian noise to obtain the order M of the cellular automata and two reciprocal rule vectors d₁And d₂Wherein d is₁＝{d₁(M), M ═ 1,2,. ang., M } and d₂＝{d₂(M), M ═ 1, 2.., M }, element d in the regular vector₁(m) and d₂(m) is 0 or 1;

step 2, setting an initial vector s of the cellular automaton₀Is s is₀＝{s₀(M), M is 1,2,3, M }, and the initial vector is a non-zero vector; wherein the element s₀(m) is 0 or 1;

step 3, generating two groups of parallel realized uniform white noises in the FPGA, and specifically comprising the following substeps:

step 3.1, according to the sampling frequency f of the practical application system_sAnd working clock f of FPGA_clkCalculating the number of parallel pathsWhereinRepresents rounding up;

step 3.2, according to the rule vector d₁And an initial vector s₀To obtain a regular vector d₁Initial vector s of each parallel path_p＝{s_p(m),m＝1,2,...,M}，p＝1,2,…,N；

Wherein, the 1 st path initial vectors₁Of (5) any element s₁(m) is:

wherein, the symbolTable xor operation, M ═ 1,2,3,.., M; s₀(0)≡0，s₀(M+1)≡0；

Arbitrary parallel p-th initial vector s_pMiddle element s_p(m) is:

and s_p(0) 0 and s ≡ 0 and s_p(M+1)≡0

Step 3.3, synchronization step 3.2, according to the rule vector d₂And an initial vector s₀To obtain a regular vector d₂Initial vector r of each parallel way_p＝{r_p(m),m＝1,2,...,M}，p＝1,2,…,N；

Step 3.4, according to the rule of the zero boundary 90/150 cellular automata, a rule vector d is obtained through derivation₁A recursive function f of each parallel path; wherein,p ═ 1,2, …, N; wherein,is the state vector of the p-th path and the n-th time,is the state vector of the p-th path at the n-1 th moment,

likewise, a rule vector d is obtained₂A recursive function g of each parallel path; wherein,p ═ 1,2, …, N; wherein,is the state vector of the p-th path and the n-th time,is the state vector of the p-th path at the n-1 th moment,

step 3.5, the N initial vectors s generated in step 3.2 are used_pAnd N initial vectors r generated in step 3.3_pRespectively regarded as two groups of Mbit binary numbers, and 2 groups of N paths of uniform white noise are generated in parallel in the FPGA according to the recursion function relations f and g deduced in the step 3.4Andp＝1,2,…,N；

and 4, step 4: the method for generating the parallel N-path Gaussian white noise specifically comprises the following steps:

step 4.1, for the 1 st group of uniform white noise generated in step 3Using non-equidistant piecewise polynomial fitting method to Box _ Muller algorithmFitting to obtain fitting coefficients of the unequal interval segments; the fitting coefficient is quantized and storedStoring the data into an FPGA internal memory; in FPGA, the 1 st group Mbit uniform white noise generated in parallel in the step 3 is subjected to fitting coefficient storagePerforming parallel polynomial calculations and truncating high Mbit as intermediate results

Step 4.2, for the group 2 uniform white noise generated in step 3According to formula y in Box _ Muller algorithm₂＝cosx₂Generating M bit intermediate result by adopting CORDIC IP core parallel computation inside FPGA

Step 4.3: generating a p-th path of Gaussian white noise g in parallel in the FPGA_p(N), p ═ 1,2, …, N: on the p-th path, two mbits are addedAndmultiply and truncate the product result by high M₀bit as the finally generated white Gaussian noise g_p(n); wherein M is₀Is the significant digit of the digital/analog converter;

and 5: and 4, sequentially carrying out parallel-serial conversion on the N paths of Gaussian white noises generated in the step 4, and then generating final Gaussian white noises through digital-to-analog conversion.

Further, in step 1, the rule vector is obtained by a euclidean algorithm or a table lookup.

Has the advantages that:

compared with the prior art, the invention has the following advantages:

firstly, a uniform white noise parallel generation algorithm based on the cellular automaton theory and an FPGA-based implementation method are provided. On the basis of the cellular automata theory, the invention provides a method for selecting rules, orders and parallel paths of the cellular automata according to the period length of uniform white noise to be generated, the high-speed sampling frequency of an actual system and the low-speed working clock of the FPGA, deduces a calculation method for realizing N paths of initial vectors required in parallel and a recurrence function relation of a parallel generation algorithm of the cellular automata, and finally provides the FPGA high-speed parallel realization method for uniform white noise based on the cellular automata. Therefore, the method provided by the invention has the advantages of generating uniform white noise by the cellular automaton theory, such as long period, high speed, good statistical property, less hardware resource occupation and the like, and greatly improves the real-time property and the generating speed of the uniform white noise.

Subsequently, a low-complexity approximation method of the Box _ Muller algorithm is given. The method adopts a polynomial segmented at unequal intervals to approximate logarithm and an evolution operation in an original Box _ Muller algorithm, and adopts a CORDIC algorithm to carry out cos operation in the Box _ Muller algorithm. Through the approximation, the Box _ Muller algorithm can be simplified into simple multiplication and addition and CORDIC operation, only a small number of multipliers and logic resources are needed to be consumed during FPGA implementation, and the method is particularly suitable for generating high-speed parallel white Gaussian noise.

In summary, compared with the existing white gaussian noise hardware generator, the method provided by the invention can generate the white gaussian noise with long period, large bandwidth and good quality in real time and at high speed under the condition of lower FPGA resource consumption.

Drawings

FIG. 1 is an implementation structure of arbitrary parallel p-th path intermediate result 1 calculation.

FIG. 2 is a block diagram of a Gaussian white noise hardware generator according to the present invention.

Detailed Description

The invention is described in detail below by way of example with reference to the accompanying drawings.

The invention provides a parallel realization method of a real-time white Gaussian noise hardware generator, which can generate high-quality white Gaussian noise on an FPGA in parallel, in real time and at high speed based on the cellular automaton theory and the Box _ Muller algorithm. Firstly, determining the order, the rule and the number of parallel paths of a cellular automaton according to the noise period length, the high-speed sampling frequency of an actual system, the low-speed working clock of an FPGA (field programmable gate array) and the like; then, according to the order and the rule of the cellular automata, two reciprocal rule vectors are obtained by adopting an Euclidean algorithm or table lookup; meanwhile, according to the theory of cellular automata, deducing N paths of initial vectors and function recursion relations required in parallel implementation by using arbitrarily set non-zero initial vectors, and generating two groups of uniform white noises in the FPGA; and finally, approximating a Box _ Muller algorithm by adopting non-equidistant polynomial fitting and a CORDIC algorithm, carrying out Gaussian treatment on two groups of uniform white noises generated in parallel, and then generating final Gaussian white noises through parallel-serial conversion and D/A external amplification.

The method comprises the following specific steps:

step 1: the rules and order of the cellular automata are determined according to the length of the cycle required to generate the white gaussian noise.

Assuming that the period length required to generate gaussian white noise is L, the invention selects the zero boundary 90/150 cellular automata rule in order to generate a longer period of uniform white noise with a lower cellular automata order. Under this cellular automata rule, the order M is calculated as follows:

wherein,indicating a rounding up operation.

Step 2: according to the zero boundary 90/150 cellular automata rule and the order M determined in step 1, two reciprocal rule vectors of the M-order cellular automata can be obtained by Euclidean algorithm or table lookup, and are respectively recorded as: d₁＝{d₁(M), M ═ 1,2,. ang., M } and d₂＝{d₂(M), M1, 2, M, where there are only two possibilities of 0 and 1 for an element in the regular vector, i.e., d₁(m) ∈ {0,1} and d₂(m)∈{0,1}。

And step 3: setting a non-zero vector of any M elements as an initial vector of the cellular automaton, wherein each element has only 0 or 1 value and is marked as s₀＝{s₀(M), M ═ 1,2,3, M }, where M denotes the position of an element in the vector, and s is present₀(m)∈{0,1}。

And 4, step 4: according to cellular automaton rule, order M and rule vector d₁And d₂Initial vector s₀And deducing a parallel implementation algorithm of the cellular automaton, and generating two groups of parallel implemented uniform white noises inside the FPGA.

The method comprises the following specific steps:

step 4.1: according to the sampling frequency f of the actual application system_sWorking clock f to be adopted for realizing FPGA hardware_clkCalculating the number of parallel pathsWhereinIndicating a rounding up operation.

Step 4.2: according to the rule vector d₁And an initial vector s₀Generating a 1 st group of N initial vectors required for parallel implementation according to the theory recursion of the cellular automaton, and recording the N initial vectors as s_p＝{s_p(M), M ═ 1, 2.., M; 1,2, N, which is a radical of formula iMiddle M ∈ [1, M]Indicating the position of the elements in the vector, p ∈ [1, N]Representing the number of parallel paths.

The specific principle of the steps is as follows:

according to the theory of cellular automata, the parallel p is equal to the initial vector s of the 1 st path₁Of (5) any element s₁(m) may be represented by a regular vector d₁And an initial vector s₀The medium element is calculated according to the following formula:

wherein, the symbolTable xor operation, vector element position M is 1,2,3. According to the zero boundary 90/150 cellular automata rule, there is s₀(0) 0 and s ≡ 0 and s₀(M+1)≡0。

In the same way, the p-th initial vector s is arbitrarily parallel_pThe middle element can be formed by a p-1 way initial vector s_p-₁Medium element and rule vector d₁Calculated as follows:

wherein p is 2,3_p(0) 0 and s ≡ 0 and s_p(M+1)≡0。

Thus, according to the rule vector d₁And an initial vector s₀N initial vectors s required by parallel implementation can be obtained by recursion according to the formulas (2) and (3)_p＝{s_p(m),m＝1,2,...,M,p＝1,2,...,N}。

Step 4.3: in the same way, according to the rule vector d₂And an initial vector s₀Generating a 2 nd group of N initial vectors required for parallel implementation according to the theory recursion of the cellular automaton, and recording the N initial vectors as r_p＝{r_p(m),M1, 2, 1, N, wherein M ∈ [1, M]Indicating the position of the elements in the vector, p ∈ [1, N]Representing the number of parallel paths.

It is worth noting that the step 4.3 principle is the same as the step 4.2 principle, with the only difference being that the rule vectors used are different. That is, the p-th 1-way initial vector r₁Any of the elements can be calculated as follows:

any p-th initial vector r_pIn the middle is

Wherein, p is 2,3_p(0) 0 and r ≡ 0 and r_p(M+1)≡0。

Step 4.4: according to the rule of the zero boundary 90/150 cellular automata, a parallel realization time rule vector d is deduced₁、d₂Function recurrence relation c of any p-th path under_p(n)＝f(c_p(n-1))。

The principle of the steps is as follows:

with a regular vector d₁The corresponding data in group 1 is taken as an example:

according to cellular automata theory, an arbitrary nth time state vector s (n) { s (M, n) ═ 1.., M; any element s (m, n) in 0, 1. } may be calculated under the rule of the zero boundary 90/150 as follows:

wherein d (m) is an element in an arbitrary rule vector d.

Considering that any regular vector d is a known quantity and only 0 or 1 value exists, recursion is carried out for 1 time according to the formula (6), and the method can obtain

That is, the state vector s (n +1) at the n +1 th time is independent of the regular vector, and can be represented by the state vector s (n) at the n th time according to the fixed functional relationship f₁Is represented by s (n +1) ═ f₁(s(n))。

Similarly, recursion is carried out again according to the two formulas (6) and (7), and the functional relation f determined by s (n +2) and s (n) can be obtained₂And is denoted as s (n +2) ═ f₂(s(n))。

By analogy, after recursion for N times, the obtained result is

s(n+N)＝f(s(n)) (8)

That is, the state vector s (N + N) at the N + N time can be directly calculated from the state vector s (N) at the N time according to the determined functional relationship f.

Considering that if the cellular automaton is realized by N paths in parallel, the state vector c generated by the cellular automaton is realized in parallel at any p path and N time_p(n)＝{c_p(M, N), M being 1.,. M, N being 0, 1. } corresponds to the state vector at the N × (N-1) + p th time point, which should be generated by the original serial cellular automaton (6).

According to the expressions (8) and (9), the equal-sign right state vector satisfies:

s(N×(n-1)+p)＝f(s(N×(n-2)+p))

the state vector c thus implemented in parallel_p(n) and c_p(n-1) also present:

c_p(n)＝f(c_p(n-1)) (10)

that is, the state vector c at the arbitrary p-th and n-th time points_p(n) the state vector c from the previous time instant_p(n-1) calculation according to a uniform functional relationship f, c_p(0)＝s_p。

Likewise, a regular vector d may be obtained₂A recursive function g of each parallel path; wherein,p ═ 1,2, …, N; wherein,is the state vector of the p-th path and the n-th time,is the state vector of the p-th path at the n-1 th moment,

step 4.5: the 1 st group N initial vectors s containing M0, 1 elements generated in step 4.2_pAnd (4) regarding the binary number as Mbit, and generating a 1 st group of N paths of uniform white noise in the FPGA in parallel according to the recurrence function relation f deduced in the step 4.4.

The principle of the steps is as follows:

if it is provided withFor any p-th way, the 1 st group state vector generated at the n-th time, thenIt can be obtained by recursion according to the following formula:

wherein the superscript "1" denotes group 1,n＝1,...,∞，p＝1,...,N。

when the FPGA is implemented, the state vector is firstly implementedM elements of 0 and 1 are regarded as Mbit binary numbers, and recursion is carried out according to a functional relation f determined by the formula (11), so that Mbit uniform white noise values generated in parallel in the 1 st group can be obtained and are recorded again asp＝1,2,...,N；n＝1,2,...。

Step 4.6: while step 4.5 is being performed, the initial vector r containing M0, 1 elements generated in step 4.3 is applied_pAnd (4) regarding the binary system as Mbit binary number, and generating a 2 nd group of N paths of uniform white noise in the FPGA in parallel according to the recursion function relation g deduced in the step 4.4.

The principle of the steps is as follows:

if it is provided withThe 2 nd group of uniform white noise generated at the nth time of any p-th pathIt can be obtained by recursion according to the following formula:

wherein the superscript "2" indicates group 2,p＝1,...,N。

if the state vector is to beM elements of 0 and 1 are regarded as Mbit binary numbers, so that the uniform white noise value generated at the nth time of the 2 nd group is obtained and is recorded asp＝1,2,...,N；n＝1,2,...。

And 5: approximating the Box _ Muller algorithm by adopting a non-equidistant piecewise polynomial fitting method and a CORDIC (Coordinate rotation digital Computer) algorithm, carrying out gaussing processing on 2 groups of uniform white noises generated in parallel in the step 4 in the FPGA to generate N paths of parallel white gaussians, and recording the N paths of parallel white noises as g_p(n),p＝1,2,...,N；n＝1,2,...。

The Box _ Muller algorithm formula is as follows:

wherein x is₁And x₂Is white noise uniformly distributed on (0,1), and x is present₁∈ (0,1) and x₂∈ (0,1), y is white gaussian noise.

Step 5.1: group 1 uniform white noise generated according to step 4Adopting a non-equidistant piecewise polynomial fitting method to calculate an intermediate result expressed by M bit in parallel in the FPGA, and recording the intermediate result as:

the specific principle of the steps is as follows:

according to the Box _ Muller algorithm, the intermediate result y₁The calculation of (a) involves natural logarithm and evolution. Obviously, if the traditional direct table lookup is adopted, a large amount of storage resources inside the FPGA are inevitably consumed. Therefore, the invention adopts a non-equidistant piecewise polynomial fitting method to calculate the natural logarithm and the evolution.

According to the precision requirement of the piecewise polynomial fitting, for x₁∈ (0,1) interval is divided into K segments, denoted as x₁∈(q_k,q_k+1) Wherein K is 0,1, K-1, and q is present₀0 and q_K1. For any kth segment, a cubic polynomial pair functional relationship shown in formula (14) is adoptedTo proceed with approximation, i.e.

According to functional relationshipAt x₁∈(q_k,q_k+1) Intra-interval pair x₁And y₁Four-point equal-interval sampling is carried out, and the following linear equation set is established by the formula (14):

X_kA_k＝Y_k(15)

wherein, the column vector A_k＝[a_kb_kc_kd_k]^T，Y_k＝[y_k1y_k2y_k3y_k4]^TAnd exist of

Solving the above-mentioned linearityThe equation system obtains a polynomial fitting coefficient A of any k-th subsection_kThus, any x₁∈(q_k,q_k+1) Function value in segmentI.e. can be fitted by a polynomial fitting coefficient a in the current segment_kAnd x₁Calculated according to the formula (14).

Considering that quantization processing is needed in specific implementation of FPGA, fitting coefficients { A ] of K unequal interval segments can be firstly subjected to the quantization processing_kK-0, 1, K-1 is quantized according to equation (17) and stored in the internal memory of the FPGA, i.e. the FPGA

Wherein,to the quantized polynomial fitting coefficients, K ∈ [0, K-1 ]]，N₁To expand the number of bits, int [ ·]Which represents the operation of rounding off,final quantization to M₁bit signed number (fractional part number N)₁bit)。

Thus, the group 1 Mbit uniform white noise generated in parallel according to step 4And stored fitting coefficientsIntermediate results can be parallelly calculated in the FPGA

Taking any p-th path intermediate result calculation as an example, the FPGA implementation structure is shown in fig. 1.

First, the fitting coefficient lookup table module looks up the uniform white noiseThe polynomial coefficients used are selected by a look-up table. For arbitrary k₀∈[0,K-1]If uniform white noiseSatisfies the following conditions:

the fitting coefficient lookup table module selects k-th as k to output₀A segmentFitting coefficient of

Then, a third order polynomial computation module computes a white noise signal based on the uniform white noiseAnd fitting coefficientIntermediate results required by the steps can be obtained by the following calculationNamely, it is

Wherein,the table rounds down. The middle process of the above formula calculation does not carry out bit cutting processing, and the calculation result cuts off the low M₂bit, reserve high Mbit as intermediate result of the final Box _ Muller algorithmAnd (6) outputting.

Step 5.2: group 2 Mbit uniform white noise generated in parallel according to step 4Adopting a Coordinate rotation Digital Computer (CORDIC-Coordinate rotation Digital Computer) IP core to calculate a cos function in parallel in the FPGA, and automatically calculating to generate an Mbit intermediate result according to the following formulaNamely, it is

Where the superscript "2" indicates the set 2 intermediate result, int [. cndot. ] indicates the rounding operation, and p ∈ [1, N ], N ∈ [1, ∞ ].

It is worth to be noted that when the FPGA is implemented inside, uniform white noise is quantized into M bit unsigned number which is used as the phase input of CORDICIP core, and the output of IP coreDirectly quantized to M bit signed number.

Step 5.3: m bit intermediate results generated from steps 5.1 and 5.2Andinside the FPGA, the following formula is calculatedGenerating N-way parallel white Gaussian noise, i.e.

Wherein, p ∈ [1, N]N ∈ [1, ∞) two Mbit signed numbers in the calculationAndmultiplication, cutting the result off by low M₃bit, reserved high M₀bit as the finally generated white Gaussian noise g_p(n) of (a). Wherein M is₀Is a significant digit of D/A, and M is present₃＝M+M-M₀。

It can be seen that, through steps 5.1 to 5.3, the invention adopts the unequal interval piecewise polynomial fitting method and the CORDUC algorithm to approximate the Box _ Muller algorithm, and two groups of M bits of uniform white noise generated in parallel in step 4 are approximated, andandgaussian processing is carried out, and N paths of M are generated in parallel in the FPGA₀White gaussian noise of bit.

Step 6: and (5) sequentially carrying out parallel-serial conversion on the N paths of Gaussian white noises generated in the step (5), and then generating final Gaussian white noises through D/A external amplification.

In summary, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (2)

1. A parallel implementation method of a real-time Gaussian white noise hardware generator is characterized by comprising the following steps:

step 1, selecting a cellular automata rule as a zero boundary 90/150 cellular automata rule, and under the rule, calculating according to the cycle length of pseudo-generated white Gaussian noise to obtain the order M of the cellular automata and two reciprocal rule vectors d₁And d₂Wherein d is₁＝{d₁(M), M ═ 1,2,. ang., M } and d₂＝{d₂(M), M ═ 1, 2.., M }, element d in the regular vector₁(m) and d₂(m) is 0 or 1;

step 2, setting an initial vector s of the cellular automaton₀Is s is₀＝{s₀(M), M is 1,2,3, M }, and the initial vector is a non-zero vector; wherein the element s₀(m) is 0 or 1;

step 3, generating two groups of parallel realized uniform white noises in the FPGA, and specifically comprising the following substeps:

step 3.1, according to the sampling frequency f of the practical application system_sAnd working clock f of FPGA_clkCalculating the number of parallel pathsWhereinRepresents rounding up;

step 3.2, according to the rule vector d₁And an initial vector s₀To obtain a regular vector d₁Initial vector s of each parallel path_p＝{s_p(m),m＝1,2,...,M}，p＝1,2,…,N；

Wherein, the 1 st path initial vector s₁Of (5) any element s₁(m) is:

$s_1\left(m\right)=s_0(m-1)\⊕\[d_1\left(m\right)\×s_0\left(m\right)\]\⊕s_0(m+1)$

wherein, the symbolTable xor operation, M ═ 1,2,3,.., M; s₀(0)≡0，s₀(M+1)≡0；

Arbitrary parallel p-th initial vector s_pMiddle element s_p(m) is:

$s_p\left(m\right)=s_{p-1}(m-1)\⊕\[d_1\left(m\right)\×s_{p-1}\left(m\right)\]\⊕s_{p-1}(m+1),p=2,3,...,N$

and s_p(0) 0 and s ≡ 0 and s_p(M+1)≡0

Step 3.3, synchronization step 3.2, according to the rule vector d₂And an initial vector s₀To obtainTo the regular vector d₂Initial vector r of each parallel way_p＝{r_p(m),m＝1,2,...,M}，p＝1,2,…,N；

Step 3.4, according to the rule of the zero boundary 90/150 cellular automata, a rule vector d is obtained through derivation₁A recursive function f of each parallel path; wherein,p ═ 1,2, …, N; wherein,is the state vector of the p-th path and the n-th time,is the state vector of the p-th path at the n-1 th moment,

likewise, a rule vector d is obtained₂A recursive function g of each parallel path; wherein,p ═ 1,2, …, N; wherein,is the state vector of the p-th path and the n-th time,is the state vector of the p-th path at the n-1 th moment,

step 3.5, the N initial vectors s generated in step 3.2 are used_pAnd N initial vectors r generated in step 3.3_pRespectively regarded as two groups of Mbit binary numbers, and 2 is generated in parallel in the FPGA according to the recurrence function relations f and g deduced in the step 3.4Set of N paths of uniform white noiseAndp＝1,2,…,N；

and 4, step 4: the method for generating the parallel N-path Gaussian white noise specifically comprises the following steps:

step 4.1, for the 1 st group of uniform white noise generated in step 3Using non-equidistant piecewise polynomial fitting method to Box _ Muller algorithmFitting to obtain fitting coefficients of the unequal interval segments; quantizing the fitting coefficients and storing the quantized fitting coefficients into an FPGA internal memory; in the FPGA, the 1 st group of M bits of uniform white noise generated in parallel in the step 3 is subjected to parallel generation according to the stored fitting coefficientPerforming parallel polynomial calculation and intercepting high M bit as intermediate result

Step 4.2, for the group 2 uniform white noise generated in step 3According to formula y in Box _ Muller algorithm₂＝cosx₂Generating M bit intermediate result by adopting CORDIC IP core parallel computation inside FPGA

Step 4.3: generating the p path Gauss white in parallel inside the FPGANoise g_p(N), p ═ 1,2, …, N: on the p-th path, two mbits are addedAndmultiply and truncate the product result by high M₀bit as the finally generated white Gaussian noise g_p(n); wherein M is₀Is the significant digit of the digital/analog converter;

and 5: and 4, sequentially carrying out parallel-serial conversion on the N paths of Gaussian white noises generated in the step 4, and then generating final Gaussian white noises through digital-to-analog conversion.

2. The method for parallel implementation of real-time white gaussian noise hardware generator according to claim 1, wherein in step 1, the rule vector is obtained by euclidean algorithm or table lookup.