CN101887864A - Three-dimension packaging method - Google Patents
Three-dimension packaging method Download PDFInfo
- Publication number
- CN101887864A CN101887864A CN 201010211699 CN201010211699A CN101887864A CN 101887864 A CN101887864 A CN 101887864A CN 201010211699 CN201010211699 CN 201010211699 CN 201010211699 A CN201010211699 A CN 201010211699A CN 101887864 A CN101887864 A CN 101887864A
- Authority
- CN
- China
- Prior art keywords
- semiconductor substrate
- substrate
- dimension packaging
- peel ply
- support substrates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
The invention provides a three-dimension packaging method, comprising the following steps: providing an initial semiconductor substrate of which one surface is prepared into a component, providing N numbered laminated semiconductor substrates which are provided with stripping layers and component layers prepared into components, bonding the initial semiconductor substrate with one laminated semiconductor substrate, stripping the laminated semiconductor substrate in a position where the stripping layer is arranged, carrying out polishing treatment on the stripped surface, preparing a lead wire of the component in the laminated semiconductor substrate, polishing the surface after the lead wire is formed, and forming a three-dimension packaging structure which is provided with two component layers, repeating the above steps, bonding and stripping N numbered semiconductor substrates in sequence and forming the three-dimension packaging structure which is provided with N+1 numbered component layers, wherein N is an integer greater than 1.
Description
[technical field]
The present invention relates to integrated circuit and make the field, relate in particular to three-dimension packaging method.
[background technology]
Following electronic system will need to satisfy following several aspect requirement day by day: volume is little, in light weight, high frequency and high-speed cruising, low-power consumption, sensitivity, multi-functional and low-cost.And three-dimension packaging satisfies the approach of a very attractive of this several aspects requirement just, and it has the advantage that reduces volume and increase the backing material utilance.
Advanced three-dimensional packaging technology requires the continuous attenuate of thickness of chip, the Semiconductor substrate thinning back side of having made device is the very important operation in the package fabrication process, superfine grinding, grinding, polishing, corrosion obtain extensive use in the Semiconductor substrate technique for thinning back side, chip behind the attenuate can improve thermal transpiration efficient, mechanical performance, electrical property, reduce the Chip Packaging volume, alleviates the scribing processing capacity.With the silicon substrate is example, and at present, the silicon substrate of making device of diameter 200mm can be thinned to 0.12-0.15mm, and diameter 300mm silicon substrate will reach this level also needs to adopt technology such as grind after chemico-mechanical polishing, plasma etching, the first scribing.Development trend after this technology order is to be thinned to the following thickness of 0.05mm.The effective thickness of circuit layer is generally 5-10 μ m on the silicon substrate, and for guaranteeing its function, and certain support thickness, the thickness limit of silicon substrate attenuate are arranged is 20-30 μ m.The average thickness of the silicon substrate of diameter 300mm is 775 μ m in the market, the average thickness of the silicon substrate of diameter 200mm is 725 μ m, so thick substrate is for guaranteeing in chip manufacturing, testing, transport enough intensity is arranged in the process, therefore, after circuit layer completes, need carry out thinning back side to it, substrate is thin more, its pliability is good more, and the stress that caused by external impacts is also more little.
But in the present three-dimension packaging technology, existing thinning technique is difficult in the substrate thinning that will be thinned also can satisfy photoetching to the evenness requirement time 50 μ m.
Therefore, present integrated circuit manufacturing field needs a kind of thickness that can reduce the substrate that is thinned, and can improve the three-dimensional packaging technology of the evenness on surface.
[summary of the invention]
Technical problem to be solved by this invention is a kind of thickness that can reduce the substrate that is thinned to be provided, and can to improve the Semiconductor substrate of the evenness on surface, the preparation method and the three-dimension packaging method of Semiconductor substrate.
In order to address the above problem, the invention provides a kind of Semiconductor substrate, comprise device layer, be positioned at the insulating barrier of device layer below, also comprise support substrates that is arranged in the insulating barrier below and the peel ply that is positioned at support substrates.
Optionally, the material of described peel ply is porous silicon or the monocrystalline silicon that contains bubble.
Optionally, the material of described device layer is a monocrystalline silicon.
Optionally, the material of described support substrates is a monocrystalline silicon.
Optionally, the material of described insulating barrier is silica or silicon nitride.
A kind of method for preparing above-mentioned Semiconductor substrate comprises the steps: to provide support substrate and device substrate; The surface of one or two substrates in support substrates and device substrate makes insulating barrier; In support substrates, carry out ion and inject, the modification ion is injected support substrates, in support substrates, form peel ply; In device substrate, carry out ion and inject, in modification ion and activating ion injection device substrate, in device substrate, form active layer; With device substrate and support substrates bonding; Annealing, device substrate is peeled off in the position of active layer, forms the device layer that is retained on support substrates and the insulating barrier; Polishing is done on surface to device layer.
Optionally, described modification ion is a hydrogen.
Optionally, described activating ion is helium, boron or its combination.
Optionally, the temperature of described annealing is 300 ℃ to 1400 ℃, and the time is 0.5 hour to 15 hours, carries out in oxygen-containing atmosphere.
Optionally, the material of described support substrates and device substrate is a monocrystalline silicon.
Optionally, the method for described polishing is chemico-mechanical polishing.
A kind of method for preparing above-mentioned Semiconductor substrate comprises the steps: to provide support substrate and device substrate; Make peel ply on the support substrates surface; Make active layer on the device substrate surface; Make device layer on the active layer surface; The surface of one or two in peel ply and device layer makes insulating barrier; With device substrate and support substrates bonding; Adopt the method for waterpower cutting, device substrate is peeled off in the position of active layer, form the device layer that is retained on support substrates and the insulating barrier; Polishing is done on surface to device layer.
Optionally, the material of described support substrates, device substrate and device layer is a monocrystalline silicon.
Optionally, the method for described making peel ply and active layer is an anode oxidation method.
Optionally, the corrosive liquid of described anodic oxidation employing is HF and C
2H
5The mixed solution of COOH, the current density of employing are 1mA/cm
2To 20mA/cm
2, the anodised time is 1min to 30min.
Optionally, described is the chemical gaseous phase epitaxy in the surperficial method of making device layer of active layer.
Optionally, the method for described polishing is chemico-mechanical polishing.
A kind of method that adopts above-mentioned Semiconductor substrate to carry out three-dimension packaging comprises the following steps: to provide a surface to make the initial Semiconductor substrate of device; Provide N to have the laminated semiconductor substrate that peel ply and device layer and device layer have been made device; Initial Semiconductor substrate and a laminated semiconductor substrate are carried out bonding; Peel off the laminated semiconductor substrate in the position of peel ply; Polishing is carried out on surface after peeling off; Make the lead-in wire of the device in the laminated semiconductor substrate; Polishing forms the surface behind the lead-in wire, forms to have the three-dimension packaging structure of two device layers; Repeat above-mentioned steps, successively with N Semiconductor substrate bonding and peel off, formation has the three-dimension packaging structure of N+1 device layer; Described N is the integer greater than 1.
Optionally, described initial Semiconductor substrate is the silicon substrate on monocrystalline substrate or the insulator.
Optionally, the material of described peel ply is a porous silicon, and stripping means is a water-jet cutting technology.
Optionally, the material of described peel ply is the monocrystalline silicon that contains bubble, and stripping means is annealing.
Optionally, described finishing method is chemico-mechanical polishing.
Compared with prior art, the invention has the advantages that employing to the substrate desquamation technology generations of peel ply for traditional corrosion or grinding technics, the thickness that can reduce the substrate that is thinned, and can improve the evenness on surface.
[description of drawings]
Accompanying drawing 1 is depicted as first embodiment schematic diagram of Semiconductor substrate;
Accompanying drawing 2 is depicted as second embodiment schematic diagram of Semiconductor substrate;
Accompanying drawing 3 is depicted as the preparation method's of Semiconductor substrate the implementation step schematic diagram of first embodiment;
Accompanying drawing 4 to Figure 10 is the preparation method's of Semiconductor substrate the process schematic representation of first embodiment;
Accompanying drawing 11 is depicted as the preparation method's of Semiconductor substrate the implementation step schematic diagram of second embodiment;
Accompanying drawing 12 to Figure 18 is the preparation method's of Semiconductor substrate the process schematic representation of second embodiment;
Accompanying drawing 19 is depicted as the implementation step schematic diagram of three-dimension packaging method embodiment;
Accompanying drawing 20 to Figure 23 is the process schematic representation of three-dimension packaging method embodiment.
[embodiment]
Below in conjunction with accompanying drawing the preparation method of Semiconductor substrate of the present invention, Semiconductor substrate and the embodiment of three-dimension packaging method are described in detail.
At first introduce the embodiment of Semiconductor substrate of the present invention.Be illustrated in figure 1 as first embodiment schematic diagram of Semiconductor substrate, comprise device layer 101, be arranged in device layer below insulating barrier 102, be positioned at the support substrates 103 of insulating barrier 102 belows and be positioned at the peel ply 104 of support substrates 103.Peel ply 104 is positioned at support substrates 103 inside, and support substrates 103 is divided into upper strata support substrates 103a and lower layer support substrate 103b two parts.
The material of described peel ply 104 is porous silicon or the monocrystalline silicon that contains bubble, and the material of device layer 101 is a monocrystalline silicon, and the material of support substrates 103 is a monocrystalline silicon, and the material of insulating barrier 102 is silica or silicon nitride.
Be illustrated in figure 2 as second embodiment schematic diagram of Semiconductor substrate, comprise device layer 201, be arranged in device layer below insulating barrier 202, be positioned at the support substrates 203 of insulating barrier 202 belows and be positioned at the peel ply 204 of support substrates 203.Peel ply 204 is positioned at support substrates 203 side near insulating barriers 202, and with insulating barrier 202 between be connected.
The material of described peel ply 204 is porous silicon or the monocrystalline silicon that contains bubble, and the material of device layer 201 is a monocrystalline silicon, and the material of support substrates 203 is a monocrystalline silicon, and the material of insulating barrier 202 is silica or silicon nitride.
Provide first embodiment of the preparation method of Semiconductor substrate of the present invention below.Be illustrated in figure 3 as the preparation method's of Semiconductor substrate the implementation step schematic diagram of first embodiment.Step S301 provides support substrate and device substrate; Step S302, the surface of one or two substrates in support substrates and device substrate makes insulating barrier; Step S303 carries out ion and injects in support substrates, the modification ion is injected support substrates, forms peel ply in support substrates; Step S304 carries out ion and injects in device substrate, in modification ion and activating ion injection device substrate, form active layer in device substrate; Step S305 is with device substrate and support substrates bonding; Step S306, annealing, device substrate is peeled off in the position of active layer, forms the device layer that is retained on support substrates and the insulating barrier; Step S307 does polishing to the surface of device layer.
Fig. 4 to Figure 10 is the process schematic representation of this embodiment.
Refer step S301 as shown in Figure 4, provides support substrate 301 and device substrate 302.Described support substrates 301 and device substrate 302 are modal monocrystalline substrate in the semiconductor technology.
Refer step S302, the surface of one or two substrates in support substrates 301 and device substrate 302 makes insulating barrier.
Because in following step, the surface of support substrates 301 and device substrate 302 will adhere to by bonding and be integral, therefore can make insulating barrier on one of them surface of support substrates 301 or device substrate 302, also can all make insulating barrier, not influence subsequent technique on the surface of support substrates 301 and device substrate 302.
As shown in Figure 5, for only making the schematic diagram of insulating barrier 303 on support substrates 301 surfaces.Insulating barrier 303 manufacture crafts can adopt oxidation preparation technology ripe in the integrated circuit, as dry-oxygen oxidation technology or " dried oxygen+wet oxygen+dried oxygen " technology.Oxidation technology is carried out under the atmosphere of oxygen, and oxidizing temperature 600-1400 ℃, oxidization time 0.5 hour to 10 hours, the material of the insulating barrier that obtains is a silica, thickness 10nm to 500 nanometer.Insulating barrier 303 also can strengthen additive methods making such as chemical vapour deposition (CVD) (PECVD), physical vapor deposition (PVD), magnetron sputtering or electron beam evaporation by using plasma, and the material of insulating barrier 305 can be silicon nitride, silicon oxynitride, carborundum, aluminium nitride or aluminium oxide etc.
Refer step S303 as shown in Figure 6, carries out ion and injects in support substrates 301, the modification ion is injected support substrates 301, forms peel ply 304 in support substrates 301.
Described modification ion can be a hydrogen, the basic principle of selecting ion is that the modification ion that is injected can produce the hole layer at silicon, change the performance of the material of ion injection phase, form the monocrystalline silicon that contains bubble, make it in follow-up technology, can realize peeling off of device layer.When the modification ion that injects was hydrogen ion, implantation dosage was 1 * 10
14/ cm
2To 1 * 10
18/ cm
2, injecting energy is that 20KeV is to 2000KeV.
Refer step S304 as shown in Figure 7, carries out ion and injects in device substrate 302, in modification ion and activating ion injection device substrate, form active layer 305 in device substrate 302.
Described activating ion can be helium, boron or its combination, and implantation dosage is 1 * 10
14/ cm
2To 1 * 10
18/ cm
2, injecting energy is that 20KeV is to 2000KeV.The activating ion that injects can strengthen the injection activity of modification ion, and the peel ply of formation is easier peeling off in subsequent annealing technology.
Refer step S305, as shown in Figure 8, with device substrate 302 and support substrates 301 bondings.
Described bonding can adopt high temperature bonding or electrostatic bonding the most common in the present semiconductor technology, also can be before bonding the auxiliary plasma activating process.
Refer step S306, as shown in Figure 9, annealing, device substrate 302 is peeled off in the position of active layer 304, forms the device layer 306 that is retained on support substrates 301 and the insulating barrier 305.
Described annealing is carried out in oxygen-containing atmosphere, and temperature is 300 ℃ to 1400 ℃, and the time is 0.5 hour to 15 hours.
Because active layer 304 has adopted modification ion and activating ion to mix the method for injecting in the process of making, the activating ion that injects can strengthen the injection activity of modification ion, makes active layer 304 to realize peeling off in lower annealing temperature and shorter time.So selected annealing time in experiment should satisfy that active layer 304 is peeled off, and peel ply 303 is not peeled off under these process conditions.Effect peel ply 303 will play peeling liner in follow-up three-dimension packaging at the bottom of.
Refer step S307 does polishing to the surface of device layer 306.As shown in figure 10 for polishing the Semiconductor substrate that the back forms.
The method of described polishing is chemico-mechanical polishing (CMP).
Introduce second embodiment of the preparation method of Semiconductor substrate of the present invention below in conjunction with accompanying drawing.Be the preparation method's of Semiconductor substrate the implementation step schematic diagram of second embodiment as shown in figure 11.Step S401 provides support substrate and device substrate; Step S402 makes peel ply on the support substrates surface; Step S403 makes active layer on the device substrate surface; Step S404 makes device layer on the surface of active layer; Step S405, the surface of one or two in support substrates and device layer makes insulating barrier; Step S406 is with device substrate and support substrates bonding; Step S407, the method that adopts waterpower to cut is peeled off device substrate in the position of active layer, form the device layer that is retained on support substrates and the insulating barrier; Step S408 does polishing to the surface of device layer.
Figure 12 to Figure 18 is the process schematic representation of this embodiment.
Refer step S401 provides support substrate and device substrate.Described support substrates and device substrate are modal monocrystalline substrate in the semiconductor technology.
Refer step S402 as shown in figure 12, makes peel ply 403 on support substrates 401 surfaces.
Refer step S403 as shown in figure 13, makes active layer 404 on device substrate 402 surfaces.
The method of above-mentioned making peel ply and active layer is an anode oxidation method.Anode oxidation method is the method for preparing porous silicon common in the semiconductor technology.The corrosive liquid that anodic oxidation condition adopts is HF and C
2H
5The mixed solution of COOH, the volume ratio that both mix is 100: 1 to 1: 100, preferred mixed proportion is 1: 1; Anodised current density is 1mA/cm
2To 20mA/cm
2Between; Anodizing time is that 1min is between the 30min.
Refer step S404 as shown in figure 14, makes device layer 405 on active layer 404 surfaces.
Described method of making device layer on the active layer surface is chemical gaseous phase epitaxy (CVD), also can be molecular beam epitaxy (MBE), low pressure chemical vapour phase epitaxy (LPCVD), high vacuum chemical vapour phase epitaxy (UHVCVD) or ultra vacuum electron beam evaporation etc.Adopting pre-oxidation process, the temperature of pre-oxidation process before the extension is 100 ℃ to 1000 ℃, and preoxidation time is 5 minutes to 10 hours, and the monocrystalline silicon layer thickness of extension is that 30nm is to 100 μ m.
Also can be according to the needs of subsequent applications, the surface that is chosen in peel ply 403 also makes one deck epitaxial loayer, and the process of preparation is identical with the technology of making active layer 405.Surface at peel ply 403 also makes epitaxial loayer, will obtain aforementioned structure shown in Figure 1 after the bonding, and peel ply 403 surfaces do not make epitaxial loayer, will obtain aforementioned structure shown in Figure 2 behind the bonding.
Refer step S405, the surface of one or two in peel ply 403 and device layer 405 makes insulating barrier 406.
Because in following step, the surface of peel ply 403 and device layer 405 will adhere to by bonding and be integral, therefore can make insulating barrier on one of them surface of peel ply 403 or device layer 405, also can all make insulating barrier, not influence subsequent technique on the surface of peel ply 403 and device layer 405.
As shown in figure 15, for only making the schematic diagram of insulating barrier 406 on peel ply 403 surfaces.Preparation technology can be with reference to the technology of the insulating barrier 305 in the last embodiment.
Refer step S406, as shown in figure 16, with device substrate 402 and support substrates 401 bondings.
Described bonding can adopt high temperature bonding or electrostatic bonding the most common in the present semiconductor technology, also can be before bonding the auxiliary plasma activating process.
Refer step S407 as shown in figure 17, adopts the method for waterpower cutting, and device substrate 402 is peeled off in the position of active layer 404, forms the device layer 405 that is retained on support substrates 402 and the insulating barrier 406.
Described waterpower cutting is the common technology of semiconductor fine manufacture field, its operation principle is that water is forced into needed cutting pressure by booster, generally at 250Mpa to 350Mpa, in water, add abrasive material, and spray to workpiece with the form of thin water arrow by energy converter, abrasive particle forms very strong cutting power under the drive of current, the water emery wheel of a similar high speed can play the effect of cutting.
Step S408 does polishing to the surface of device layer 405.As shown in figure 18 for polishing the Semiconductor substrate that the back forms.
The method of described polishing is chemico-mechanical polishing.
Introduce the embodiment of three-dimension packaging method of the present invention below in conjunction with accompanying drawing.As shown in figure 19, be the implementation step schematic diagram of three-dimension packaging method embodiment of the present invention.Step S501 provides a surface to make the initial Semiconductor substrate of device; Step S502 provides N laminated semiconductor substrate that has peel ply and made device; Step S503 carries out bonding with initial Semiconductor substrate and a laminated semiconductor substrate; Step S504 peels off the laminated semiconductor substrate in the position of peel ply; Step S505 carries out polishing to the surface after peeling off; Step S506, the lead-in wire of the device in the making laminated semiconductor substrate; Step S507, polishing forms the surface behind the lead-in wire, forms to have the three-dimension packaging structure of two device layers.
Repeat above-mentioned steps, successively with N Semiconductor substrate bonding and peel off, formation has the three-dimension packaging structure of N+1 device layer.Described N is the integer greater than 1.
Figure 20 to Figure 23 is the process schematic representation of this embodiment.
Refer step S501 as shown in figure 20, provides a surface to make the initial Semiconductor substrate 501 of device.
The bill of materials crystal silicon of described initial Semiconductor substrate 501 also can be other substrates such as silicon on the insulator or stress silicon.Described device is by the interconnected integrated circuit that forms of alloy-layer by other devices such as several metal-oxide semiconductor fieldeffect transistors (MOSFETs) and electric capacity, resistance, also can be common semiconductor device, for example bipolar device or power device etc. in other integrated circuit fields.
Refer step S502 provides N laminated semiconductor substrate that has peel ply and made device.Described laminated semiconductor substrate with peel ply and device layer is meant the Semiconductor substrate of being introduced in the embodiment of preamble Semiconductor substrate.
Refer step S503 as shown in figure 21, carries out bonding with initial Semiconductor substrate 501 and a laminated semiconductor substrate.The laminated semiconductor substrate comprises peel ply 502 and insulating barrier 503.
Refer step S504 as shown in figure 22, peels off the laminated semiconductor substrate in the position of peel ply 502.The material of described peel ply 502 is a porous silicon, and stripping means adopts water-jet cutting technology.If the material of described peel ply 502 is the monocrystalline silicon that contains bubble, then stripping means is annealing.Water conservancy cutting and annealing process can be with reference to the embodiments of preamble preparation method of semiconductor substrate.
Refer step S505 carries out polishing to the surface after peeling off.Chemico-mechanical polishing is adopted in described polishing.
Step S506, the lead-in wire of the device in the making laminated semiconductor substrate.
By photoetching and deep etching technique etched features layer, realize at the pin place of the alloy line of semiconductor device from stopping, subsequently deposition dielectric film and utilize plating mode to electroplate layer of copper as lead-in wire.Above-mentioned photoetching, deep erosion, deposition medium film and electroplating technology are the known technology of those skilled in that art, do not add to be described in detail herein.
Step S507, polishing forms the surface behind the lead-in wire, forms to have the three-dimension packaging structure of two device layers.Chemico-mechanical polishing is adopted in described polishing.
As shown in figure 23, the three-dimension packaging structural representation for adopting this method to make with two device layers
Continue the stack device layer as need, only need to repeat above-mentioned steps, successively N Semiconductor substrate is bonded to the surface of three-dimension packaging structure and peels off, formation has the three-dimension packaging structure of N+1 device layer.
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (7)
1. the method for a three-dimension packaging is characterized in that, comprises the following steps:
Provide a surface to make the initial Semiconductor substrate of device;
N laminated semiconductor substrate is provided, described Semiconductor substrate comprises device layer, be arranged in the device layer below insulating barrier, be positioned at the support substrates of insulating barrier below and be positioned at the peel ply of support substrates, and made device in the device layer;
Initial Semiconductor substrate and a laminated semiconductor substrate are carried out bonding;
Peel off the laminated semiconductor substrate in the position of peel ply;
Polishing is carried out on surface after peeling off;
Make the lead-in wire of the device in the laminated semiconductor substrate;
Polishing forms the surface behind the lead-in wire, forms to have the three-dimension packaging structure of two device layers;
Repeat above-mentioned steps, successively with N Semiconductor substrate bonding and peel off, formation has the three-dimension packaging structure of N+1 device layer;
Described N is the integer greater than 1.
2. the method for three-dimension packaging according to claim 1 is characterized in that, described initial Semiconductor substrate is the silicon substrate on monocrystalline substrate or the insulator.
3. the method for three-dimension packaging according to claim 1 is characterized in that, the material of described peel ply is a porous silicon.
4. the method for three-dimension packaging according to claim 3 is characterized in that, described stripping means is a water-jet cutting technology.
5. the method for three-dimension packaging according to claim 1 is characterized in that, the material of described peel ply is the monocrystalline silicon that contains bubble.
6. the method for three-dimension packaging according to claim 5 is characterized in that, described stripping means is annealing.
7. the method for three-dimension packaging according to claim 1 is characterized in that, described finishing method is chemico-mechanical polishing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010211699 CN101887864B (en) | 2007-12-26 | 2007-12-26 | Three-dimension packaging method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010211699 CN101887864B (en) | 2007-12-26 | 2007-12-26 | Three-dimension packaging method |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007101730957A Division CN101471347B (en) | 2007-12-26 | 2007-12-26 | Semiconductor substrate, method for preparing the same and three-dimensional encapsulation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101887864A true CN101887864A (en) | 2010-11-17 |
| CN101887864B CN101887864B (en) | 2011-09-28 |
Family
ID=43073706
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201010211699 Expired - Fee Related CN101887864B (en) | 2007-12-26 | 2007-12-26 | Three-dimension packaging method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101887864B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102214613A (en) * | 2011-05-13 | 2011-10-12 | 上海新傲科技股份有限公司 | Three-dimensional packaging method |
| CN102637607A (en) * | 2011-12-29 | 2012-08-15 | 上海新傲科技股份有限公司 | Three-dimensional encapsulation method |
-
2007
- 2007-12-26 CN CN 201010211699 patent/CN101887864B/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102214613A (en) * | 2011-05-13 | 2011-10-12 | 上海新傲科技股份有限公司 | Three-dimensional packaging method |
| CN102637607A (en) * | 2011-12-29 | 2012-08-15 | 上海新傲科技股份有限公司 | Three-dimensional encapsulation method |
| CN102637607B (en) * | 2011-12-29 | 2016-02-24 | 上海新傲科技股份有限公司 | Three-dimension packaging method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101887864B (en) | 2011-09-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100595928C (en) | Semiconductor substrate, preparing technique and application in advanced three-dimensional electronic packaging | |
| CN101471347B (en) | Semiconductor substrate, method for preparing the same and three-dimensional encapsulation method | |
| JP6803901B2 (en) | Insulation layer structure for semiconductor products and its manufacturing method | |
| EP1453096B1 (en) | Method for producing a bonded wafer | |
| WO2004012268A1 (en) | Soi wafer manufacturing method | |
| KR20090009887A (en) | Semiconductor on glass insulator made using improved thinning process | |
| WO2004064145A1 (en) | Method of producing soi wafer and soi wafer | |
| CN101174640A (en) | Insulating layer upper semiconductor structure with low dielectric constant as insulation buried layer and its method | |
| CN101615590B (en) | Method for preparing silicon-on-insulator material using selective corrosion process | |
| CN101101891A (en) | Silicon of insulator and its making technology | |
| CN103579103A (en) | Three-dimensional lamination packing method and production method of image sensor | |
| CN102832160A (en) | Preparation method of SOI (silicon on insulator) silicon wafer | |
| WO2014005379A1 (en) | Method for fabricating goi wafer structure | |
| CN101887864B (en) | Three-dimension packaging method | |
| Li et al. | Room temperature wafer bonding by surface activated ALD-Al2O3 | |
| WO2003046994A1 (en) | Method for producing cemented wafer | |
| Zhang et al. | Operating TSV in Stable Accumulation Capacitance Region by Utilizing $\hbox {Al} _ {2}\hbox {O} _ {3} $-Induced Negative Fixed Charge | |
| WO2003046992A1 (en) | Soi wafer manufacturing method | |
| US6420243B1 (en) | Method for producing SOI wafers by delamination | |
| CN114188362A (en) | SOI (silicon on insulator) with special structure and preparation method thereof | |
| WO2004010505A1 (en) | Soi wafer and production method therefor | |
| JP2012253333A (en) | Wiring board having through electrode, and manufacturing method of the same | |
| JP2013526030A (en) | Method for migrating at least one microtechnical layer | |
| CN101930919A (en) | Semiconductor device and manufacture method thereof | |
| CN113539940B (en) | Preparation method of semiconductor substrate and semiconductor substrate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110928 Termination date: 20141226 |
|
| EXPY | Termination of patent right or utility model |