CN101882602B - Manufacturing method of phase-changing random access memory - Google Patents
Manufacturing method of phase-changing random access memory Download PDFInfo
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- CN101882602B CN101882602B CN2009100509881A CN200910050988A CN101882602B CN 101882602 B CN101882602 B CN 101882602B CN 2009100509881 A CN2009100509881 A CN 2009100509881A CN 200910050988 A CN200910050988 A CN 200910050988A CN 101882602 B CN101882602 B CN 101882602B
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Abstract
The invention relates to a manufacturing method of a phase-changing random access memory, comprising the following steps: providing a semiconductor substrate at least provided with a memory region, a peripheral circuit region and a plurality of polysilicon plugs connected with the memory region and the peripheral circuit region; etching the polysilicon plugs; performing ion implantation to the polysilicon plugs; filling a sacrifice electrolyte layer on a vertical diode; removing the sacrifice electrolyte layer filled on the vertical diode in the peripheral circuit region; removing the vertical diode of the peripheral circuit region; forming metallic plugs in plug holes of the peripheral circuit region; removing the sacrifice electrolyte layer in the plug holes in the memory region; and filling the phase-changing memory material in the plug holes in the memory region. Compared with the prior art, the plug hole in the memory region are filled by the sacrifice electrolyte layer, so, in the manufacturing process of the device, the metallic plugs cannot form in the plug holes in the memory region, thereby conquering the problem of short circuit. etc caused by the residual metal when removing the metallic plugs in the plug holes in the memory region.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to the manufacturing approach of phase change random access memory devices.
Background technology
(Phase Change RAM PCRAM) is the novel memory of a kind of replacement and non-flash memory (NAND Flash) to phase change random access memory devices.In phase change random access memory devices, the phase change layer that has wherein write down data can be through heat-treating the value that changes memory to it.The phase-change material of said formation phase change layer can get into crystalline state or noncrystalline state owing to the heats of applying electric current.When phase change layer was in crystalline state, the resistance of PCRAM was lower, and this moment, the memory assignment was " 0 ".When phase change layer was in noncrystalline state, the resistance of PCRAM was higher, and this moment, the memory assignment was " 1 ".Therefore, PCRAM utilizes resistance difference when phase change layer is in crystalline state or noncrystalline state to write/nonvolatile memory of reading of data.
The core texture of typical phase change random access memory devices is as shown in Figure 1, comprising: Semiconductor substrate 609; First insulating barrier 603 on the Semiconductor substrate 609; Grid 604 on first insulating barrier 603; First doped region 601 in the Semiconductor substrate 609 of first insulating barrier 603 and grid 604 both sides and second doped region 602; On the Semiconductor substrate 609, isolate first insulating barrier 603 and go up second insulating barrier 610 of grid 604; Connector 605 in second insulating barrier 610; First electrode layer 606 on second insulating barrier 610; Phase change layer 607 on first electrode layer 606; The second electrode lay 608 on the phase change layer 607; The side wall 612 of first electrode layer 606, phase change layer 607 and the second electrode lay 608 both sides; On second insulating barrier 610, isolate the 3rd insulating barrier 611 of the second electrode lay 608, first electrode layer 606, phase change layer 607 and the second electrode lay 608 both sides side walls 612.
And a complete memory circuitry structure also comprises decoding circuit and peripheral MOS circuit in above-mentioned core texture periphery., United States Patent (USP), the application number of for example US6759267B2 can also find more information relevant in being 200610121663.4 one Chinese patent application with above-mentioned phase change random access memory devices.
In addition, industry has also proposed a kind of brand-new phase change random access memory (pram) device structure---vertical diode Drive Structure.Its maximum characteristics are all to be placed on diode, phase-change material in the vertical insulating material hole; Fully utilized the strong advantage of diode driving force; Device size is at utmost reduced, and crosstalking between the device cell at utmost reduces, and phase transition process stability strengthens.Utilize this structure to prepare the maximum test chip of present capacity, its application prospect is very tempting.
Yet; In the prior art; The core texture of phase change random access memory devices and decoding circuit and peripheral MOS circuit are integrated manufacturings; Used metal plug is residual at the consent sidewall in the time of can't avoiding that some make decoding circuits and peripheral MOS circuit when making core texture, thereby causes short circuit.
In addition, when making decoding circuit and peripheral MOS circuit, in the process of removing metal plug, the loss of dielectric layer and polysilicon pillar is too many, causes made device quality to descend.
Summary of the invention
Technical problem to be solved by this invention is: it is residual to avoid phase change random access memory devices in manufacture process, to form metal sidewall.
For addressing the above problem; According to an aspect of the present invention; A kind of manufacturing approach of phase change random access memory devices is provided, comprises step: Semiconductor substrate is provided, has memory areas and peripheral circuit region on the said Semiconductor substrate at least; Also be provided with dielectric layer on said memory areas and the peripheral circuit region, have many polysilicon plugs in the said dielectric layer; The said polysilicon plug of etching forms consent on said dielectric layer; Said polysilicon plug is carried out ion inject, form vertical diode; On said vertical diode, fill sacrificial dielectric layer; Remove the sacrificial dielectric layer of filling on the vertical diode in the peripheral circuit region; Remove the vertical diode of said peripheral circuit region; In the consent of said peripheral circuit region, form metal plug; Remove the interior sacrificial dielectric layer of consent of said memory block; In the consent of said memory block, fill phase-change storage material.
Alternatively, also comprise the decoder district on the said Semiconductor substrate.
Alternatively, there are many polysilicon plugs to be connected on the said Semiconductor substrate with said decoder district; In addition, also comprise step: remove the sacrificial dielectric layer of filling on the vertical diode in the said decoder district; In the consent in said decoder district, form metal plug.
The sacrificial dielectric layer of filling on the vertical diode in said decoder district and the said peripheral circuit region alternatively, is removed in the lump.
Alternatively, the material of said sacrificial dielectric layer is selected from silicon nitride or silicon oxynitride.
Alternatively, the step of in the consent of said memory block, filling phase-change storage material is specially: the consent inwall in said memory block forms the liner dielectric, in said consent, fills phase-change storage material then.
According to another aspect of the present invention; A kind of manufacturing approach of phase change random access memory devices is provided; Comprise step: Semiconductor substrate is provided; At least have memory areas and peripheral circuit region on the said Semiconductor substrate, also be provided with dielectric layer on said memory areas and the peripheral circuit region, have many polysilicon plugs in the said dielectric layer; Polysilicon plug in the etching memory areas forms consent on said dielectric layer; Polysilicon plug in the memory areas is carried out ion inject, form vertical diode; On said vertical diode, fill sacrificial dielectric layer; Remove the polysilicon plug in the peripheral circuit region, form consent; In the consent of said peripheral circuit region, form metal plug; Remove the interior sacrificial dielectric layer of consent of said memory block; In the consent of said memory block, fill phase-change storage material.
Alternatively, also comprise the decoder district on the said Semiconductor substrate.
Alternatively, there are many polysilicon plugs to be connected on the said Semiconductor substrate with said decoder district; In addition, also comprise step: the polysilicon plug in the etching decoder district forms consent on dielectric layer; Polysilicon plug in the decoder district is carried out ion inject the vertical diode of formation; Remove the sacrificial dielectric layer of filling on the vertical diode in the decoder district; In the consent in said decoder district, form metal plug.
Alternatively, the material of said sacrificial dielectric layer is selected from silicon nitride or silicon oxynitride.
Alternatively, the step of in the consent of said memory block, filling phase-change storage material is specially: the consent inwall in said memory block forms the liner dielectric, in said consent, fills phase-change storage material then.
Compared with prior art; The present invention is with the consent in the sacrificial dielectric layer filling memory areas; Thereby in the manufacture process of device; Do not have in the consent that metal plug is formed on memory areas, thereby leave the problems such as short circuit that metal residues brings when having overcome in the prior art metal plug in the consent of removing the memory block.
And, even the sacrificial dielectric layer in the consent of memory areas can not be removed fully, also only be that the size to consent exerts an influence, do not influence the electric property of entire device.
In addition, because silicon nitride has very high selection ratio to dielectric layer and polysilicon plug, thereby the loss of dielectric layer in the manufacture process and polysilicon plug is less.
Description of drawings
Fig. 1 is the structural representation of phase change random access memory devices in the prior art;
Fig. 2 is the manufacturing approach flow chart of one embodiment of the invention phase change random access memory devices;
Fig. 3 to Figure 11 is a sketch map of making phase change random access memory devices according to flow process shown in Figure 2;
Figure 12 is the manufacturing approach flow chart of another embodiment of the present invention phase change random access memory devices;
Figure 13 to Figure 21 is a sketch map of making phase change random access memory devices according to flow process shown in Figure 12.
Embodiment
In one embodiment of the invention, a kind of manufacturing approach of phase change random access memory devices is provided, as shown in Figure 2, comprise step:
S11; Semiconductor substrate is provided; Have memory areas, decoder district and peripheral circuit region on the Semiconductor substrate; Memory areas, decoder district and peripheral circuit region are covered by dielectric layer, have many polysilicon plugs in the said dielectric layer, and said polysilicon plug is connected with peripheral circuit region with said memory areas, decoding district respectively;
S12, the said polysilicon plug of etching forms consent on said dielectric layer;
S13 carries out ion to said polysilicon plug and injects, and forms vertical diode;
S14 fills sacrificial dielectric layer on vertical diode;
S15 removes the sacrificial dielectric layer of filling on the vertical diode in decoder district and the peripheral circuit region;
S16, the vertical diode in the consent of removal peripheral circuit region;
S17 forms metal plug in the consent of decoder district and peripheral circuit region;
S18 removes the interior sacrificial dielectric layer of consent of memory block;
S19 fills phase-change storage material in the consent of memory block.
Be elaborated below in conjunction with accompanying drawing.
At first execution in step S11 provides Semiconductor substrate 101 as shown in Figure 3.Semiconductor substrate 101 is provided with memory areas 102, decoder district 103 and peripheral circuit region 104.Be respectively equipped with memory, decoder and transistor etc. in memory areas 102, decoder district 103 and the peripheral circuit region 104.Between memory, decoder and the transistor by 105 isolation of fleet plough groove isolation structure.The surface of whole Semiconductor substrate 101 is covered by dielectric layer 106, also is that memory areas 102, decoder district 103 and peripheral circuit region 104 are all covered by dielectric layer 106.In one embodiment of the invention, dielectric layer 106 is formed by the technology of high-density plasma (HDP).Can also include transistor 107 in the peripheral circuit region 104.
Having many polysilicon plugs 120 in the dielectric layer 106 is connected with memory areas 102 interior memory, decoder district 103 interior decoder or peripheral circuit region 104 interior transistors respectively.
Execution in step S12 is as shown in Figure 4 then, and etch polysilicon embolism 120 forms consent 111,112,113 on said dielectric layer.Here, consent the 111,112, the 113rd is used for follow-up filling contact electrode or phase-change material.The method that forms consent 111,112,113 can be the method for plasma etching, and concrete technological parameter is well known to those skilled in the art, repeats no more at this.
Execution in step S13 is as shown in Figure 5 again, the polysilicon plug 120 of memory areas 102, decoder district 103 and peripheral circuit region 104 is carried out ion inject, and forms vertical diode 114.Form vertical diode 114 in one embodiment of the invention and specifically also comprise step: Semiconductor substrate 101 is carried out wet-cleaned; Polysilicon plug 120 is carried out P type ion to be injected; Said polysilicon plug 120 is carried out oxidation being lower than under 800 ℃ the environment, thereby form satisfactory vertical diode 114.Certainly, the description to the electrical upper and lower relation of the PN junction of vertical diode 114 only is an example here, in the present invention, also can be and the electrical opposite vertical diode 114 of the foregoing description.
Execution in step S14 fills sacrificial dielectric layer 115 on the vertical diode 114 in consent 111,112,113 then, forms structure as shown in Figure 6.The material of sacrificial dielectric layer 115 is dielectrics that dielectric layer 106 and vertical diode 114 are had enough etching selection ratio, for example can be silicon nitride or silicon oxynitride.In one embodiment of the invention, the concrete grammar of filling sacrificial dielectric layer 115 can be to adopt the method for PECVD to carry out the silicon nitride deposition adopts cmps afterwards again to the unnecessary sacrificial dielectric layer outside the consent 111,112,113 115 method removal.
Then execution in step S15 removes the sacrificial dielectric layer 115 of filling on the vertical diode 114 in decoder district 103 and the peripheral circuit region 104, forms structure as shown in Figure 7.The method of removal sacrificial dielectric layer 115 is specifically in decoder district 103 and peripheral circuit region 104 in one embodiment of the invention: on Semiconductor substrate 101, form mask layer; Pattern mask layer and expose decoder district 103 and peripheral circuit region 104; Utilize the sacrificial dielectric layer 115 in the method etching consent 112,113 of plasma etching, be used to remove sacrificial dielectric layer 115; Remove mask layer at last.When removing sacrificial dielectric layer 115, even if exist certain residual also be acceptable, to the not influence of electric property of entire device, thereby can reduce the difficulty of whole manufacturing process.
Execution in step S16 again removes the vertical diode 114 in the consent 113 of peripheral circuit region 104.The method of removing the vertical diode 114 in the consent 113 of peripheral circuit region 104 in one embodiment of the invention is specifically: on Semiconductor substrate 101, form mask layer; Pattern mask layer and expose peripheral circuit region 104; Utilize vertical diode 114 in the method etching consent 113 of plasma etching to removing fully; Remove mask layer at last, form structure as shown in Figure 8.
Then execution in step S17 forms metal plug 116 in the consent 112,113 of decoder district 103 and peripheral circuit region 104, promptly forms structure as shown in Figure 9.In one embodiment of the invention, the method that in the consent 112,113 of decoder district 103 and peripheral circuit region 104, forms metal plug 116 is specifically: through sputtering at the inwall formation Ti/TiN inner membrance of consent 112,113; Semiconductor substrate 101 is carried out quick thermal annealing process; In consent 112,113, fill metal W; Method with cmp is removed the metal W outside the consent 112,113.
Execution in step S18 again removes the sacrificial dielectric layer 115 in the consent 111 of memory block 102, forms structure shown in figure 10.In step S18, the method for removing sacrificial dielectric layer 115 specifically can be the method for plasma etching.When removing sacrificial dielectric layer 115, even if exist certain residual also be acceptable, to the not influence of electric property of entire device, thereby can reduce the difficulty of whole manufacturing process.Also overcome simultaneously and in the consent 211 of memory block 202, left the deficiency that metal residues brings in the prior art.
Last execution in step S19 fills phase-change storage material 117 in the consent 111 of memory block 102.In one embodiment of the invention, the concrete grammar of filling phase-change storage material 117 is: method deposited silicon nitride layer in consent 111 of utilizing PECVD; The plasma etching silicon nitride layer, thus liner silicon nitride layer 118 formed at the inwall of consent 111; In consent 111, fill phase-change storage material 117, form structure shown in figure 11.
In another embodiment of the present invention, the manufacturing approach of another kind of phase change random access memory devices is provided, shown in figure 12, comprise step:
S21; Semiconductor substrate is provided; Have memory areas, decoder district and peripheral circuit region on the Semiconductor substrate; Memory areas, decoder district and peripheral circuit region are covered by dielectric layer, have many polysilicon plugs in the said dielectric layer, and said polysilicon plug is connected with peripheral circuit region with said memory areas, decoding district respectively;
S22, the polysilicon plug in etching memory areas and the decoder district forms consent on dielectric layer;
S23 carries out ion to the polysilicon plug in memory areas and the decoder district and injects the vertical diode of formation;
S24 fills sacrificial dielectric layer on vertical diode;
S25 removes the polysilicon in the peripheral circuit region consent;
S26 removes the sacrificial dielectric layer of filling on the vertical diode in the decoder district;
S27 forms metal plug in the consent of decoder district and peripheral circuit region;
S28 removes the interior sacrificial dielectric layer of consent of memory block;
S29 fills phase-change storage material in the consent of memory block.
Be elaborated below in conjunction with accompanying drawing.
At first execution in step S21 provides Semiconductor substrate 201 shown in figure 13.Semiconductor substrate 201 is provided with memory areas 202, decoder district 203 and peripheral circuit region 204.Be respectively equipped with memory, decoder and transistor etc. in memory areas 202, decoder district 203 and the peripheral circuit region 204.Between memory, decoder and the transistor by 205 isolation of fleet plough groove isolation structure.The surface of whole Semiconductor substrate 201 is covered by dielectric layer 206, also is that memory areas 202, decoder district 203 and peripheral circuit region 204 are all covered by dielectric layer 206.In one embodiment of the invention, dielectric layer 206 is formed by the technology of high-density plasma (HDP).Can also include transistor 207 in the peripheral circuit region 204.
Having many polysilicon plugs 220 in the dielectric layer 206 is connected with memory areas 202 interior memory, decoder district 203 interior decoder or peripheral circuit region 204 interior transistors respectively.
Execution in step S22 is shown in figure 14 then, and the polysilicon plug 220 in etching memory areas 202 and the decoder district 203 forms consent 211,212 on dielectric layer 206.The method that forms consent 211,212 can be the method for plasma etching, and concrete technological parameter is well known to those skilled in the art, repeats no more at this.
Execution in step S23 is shown in figure 15 again, memory areas 202 is carried out ion with decoder district 203 interior polysilicon plugs 220 inject, and forms vertical diode 214.The concrete grammar that forms vertical diode 214 in one embodiment of the invention comprises step: Semiconductor substrate 201 is carried out wet-cleaned; Memory areas 202 is carried out P type ion with decoder district 203 interior polysilicon plugs 220 to be injected; Polysilicon plug 220 is carried out oxidation being lower than under 800 ℃ the environment, thereby form satisfactory vertical diode 214; Remove mask layer at last.Certainly, the description to the electrical upper and lower relation of the PN junction of vertical diode 214 only is an example here, in the present invention, also can be and the electrical opposite vertical diode 214 of the foregoing description.
Execution in step S24 fills sacrificial dielectric layer 215 on vertical diode 214 then, forms structure shown in figure 16.The material of sacrificial dielectric layer 215 is easily by the dielectric of removing fully, for example can be silicon nitride or silicon oxynitride.In one embodiment of the invention, the concrete grammar of filling sacrificial dielectric layer 215 can be to adopt the method for PECVD to carry out the silicon nitride deposition adopts cmps afterwards again to the unnecessary sacrificial dielectric layer outside the consent 211,212 215 method removal.
Then execution in step S25 forms the mask layer that exposes peripheral circuit region 204 on Semiconductor substrate 101, and the polysilicon plug 220 in the consent 213 of removal peripheral circuit region 204 forms consent 213, promptly forms structure shown in figure 17.Remove the method for the polysilicon plug 220 in the consent 213 and shown in those skilled in the art, know, repeat no more at this.
Execution in step S26 removes the sacrificial dielectric layer 215 of filling on the vertical diode 214 in the decoder district 203 again, forms structure shown in figure 18.The method of in decoder district 203, removing sacrificial dielectric layer 215 in one embodiment of the invention is specifically: on Semiconductor substrate 201, form mask layer; Pattern mask layer and expose decoder district 203; Utilize the method for plasma etching to remove the sacrificial dielectric layer 215 in the consent 212.When removing sacrificial dielectric layer 215, even if exist certain residual also be acceptable, to the not influence of electric property of entire device, thereby can reduce the difficulty of whole manufacturing process.
Then execution in step S27 forms metal plug 216 in the consent 212,213 of decoder district 203 and peripheral circuit region 204, promptly forms structure shown in figure 19.In one embodiment of the invention, the method that in the consent 212,213 of decoder district 203 and peripheral circuit region 204, forms metal plug 216 is specifically: form the mask layer that exposes decoder district 203 and peripheral circuit region 204; Through sputter, at the inwall formation Ti/TiN of consent 212,213 inner membrance; Semiconductor substrate 201 is carried out quick thermal annealing process; In consent 212,213, fill metal W; Method with cmp is removed the metal W outside the consent 212,213.
Because removing the process of the sacrificial dielectric layer 215 of filling on the vertical diode 214 in the decoder district 203 among polysilicon plug 220 among the step S25 in the removal consent 213 and the step S26 can not disturb mutually; Therefore, formed mask layer can be the mask layer that exposes decoder district 203 and peripheral circuit region 204 among step S25 and the step S26.And employed mask layer also is the mask layer that exposes decoder district 203 and peripheral circuit region 204 among the step S27.That is to say that step S25 can use same mask layer to step S27, thereby can reduce processing step, reduce manufacturing cost.
Execution in step S28 again removes the sacrificial dielectric layer 215 in the consent 211 of memory block 202, forms structure shown in figure 20.In step S28, the method for removing sacrificial dielectric layer 215 specifically can be the method for plasma etching.When removing sacrificial dielectric layer 115, even if exist certain residual also be acceptable, to the not influence of electric property of entire device, thereby can reduce the difficulty of whole manufacturing process.Also overcome simultaneously and in the consent 211 of memory block 202, left the deficiency that metal residues brings in the prior art.
Last execution in step S29 fills phase-change storage material 217 in the consent 211 of memory block 202.In one embodiment of the invention, the concrete grammar of filling phase-change storage material 217 is: method deposited silicon nitride layer in consent 211 of utilizing PECVD; The plasma etching silicon nitride layer, thus liner silicon nitride layer 218 formed at the inwall of consent 211; In consent 211, fill phase-change storage material 217, form structure shown in figure 21.
In the above-described embodiments, the existence in decoder district is also inessential, and the step that therefore relates to the decoder district is an optional step of the present invention.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting claim; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (8)
1. the manufacturing approach of a phase change random access memory devices is characterized in that, comprises step:
Semiconductor substrate is provided, has memory areas and peripheral circuit region on the said Semiconductor substrate at least, also be provided with dielectric layer on said memory areas and the peripheral circuit region, have many polysilicon plugs in the said dielectric layer;
The part of the said polysilicon plug of etching forms consent on said dielectric layer;
Said polysilicon plug is carried out ion inject, form vertical diode;
On said vertical diode, fill sacrificial dielectric layer;
Remove the sacrificial dielectric layer of filling on the vertical diode in the peripheral circuit region;
Remove the vertical diode of said peripheral circuit region;
In the consent of said peripheral circuit region, form metal plug;
Remove the interior sacrificial dielectric layer of consent of said memory areas;
In the consent of said memory areas, fill phase-change storage material.
2. the manufacturing approach of a phase change random access memory devices is characterized in that, comprises step:
Semiconductor substrate is provided; Have memory areas, decoder district and peripheral circuit region on the said Semiconductor substrate; Said memory areas, decoder district and peripheral circuit region are provided with dielectric layer; Have many polysilicon plugs in the said dielectric layer, some of said many polysilicon plugs are connected with said decoding district;
The part of the said polysilicon plug of etching forms consent on said dielectric layer;
Said polysilicon plug is carried out ion inject, form vertical diode;
On said vertical diode, fill sacrificial dielectric layer;
Remove the sacrificial dielectric layer of filling on the vertical diode in peripheral circuit region and the decoder district;
Remove the vertical diode of said peripheral circuit region;
In the consent of said decoder district and peripheral circuit region, form metal plug;
Remove the interior sacrificial dielectric layer of consent of said memory areas;
In the consent of said memory areas, fill phase-change storage material.
3. according to claim 1 or claim 2 the manufacturing approach of phase change random access memory devices is characterized in that the material of said sacrificial dielectric layer is selected from silicon nitride or silicon oxynitride.
4. the manufacturing approach of phase change random access memory devices as claimed in claim 1; It is characterized in that; The step of in the consent of said memory areas, filling phase-change storage material is specially: the consent inwall in said memory areas forms the liner dielectric, in said consent, fills phase-change storage material then.
5. the manufacturing approach of a phase change random access memory devices is characterized in that, comprises step:
Semiconductor substrate is provided, has memory areas and peripheral circuit region on the said Semiconductor substrate at least, also be provided with dielectric layer on said memory areas and the peripheral circuit region, have many polysilicon plugs in the said dielectric layer;
The part of the polysilicon plug in the etching memory areas forms consent on said dielectric layer;
Polysilicon plug in the memory areas is carried out ion inject, form vertical diode;
On said vertical diode, fill sacrificial dielectric layer;
Remove the polysilicon plug in the peripheral circuit region, form consent;
In the consent of said peripheral circuit region, form metal plug;
Remove the interior sacrificial dielectric layer of consent of said memory areas;
In the consent of said memory areas, fill phase-change storage material.
6. the manufacturing approach of a phase change random access memory devices is characterized in that, comprises step:
Semiconductor substrate is provided; Have memory areas, decoder district and peripheral circuit region on the said Semiconductor substrate; Also be provided with dielectric layer on said memory areas and the peripheral circuit region; Have many polysilicon plugs in the said dielectric layer, some of said many polysilicon plugs are connected with said decoder district;
The part of the polysilicon plug in etching memory areas and the decoder district forms consent on dielectric layer;
Polysilicon plug in memory areas and the decoder district is carried out ion inject, form vertical diode;
On said vertical diode, fill sacrificial dielectric layer;
Remove the polysilicon plug in the peripheral circuit region, form consent;
Remove the sacrificial dielectric layer of filling on the vertical diode in the decoder district;
In the consent in said peripheral circuit region and decoder district, form metal plug;
Remove the interior sacrificial dielectric layer of consent of said memory areas;
In the consent of said memory areas, fill phase-change storage material.
7. like the manufacturing approach of claim 5 or 6 described phase change random access memory devices, it is characterized in that: the material of said sacrificial dielectric layer is selected from silicon nitride or silicon oxynitride.
8. the manufacturing approach of phase change random access memory devices as claimed in claim 5; It is characterized in that; The step of in the consent of said memory areas, filling phase-change storage material is specially: the consent inwall in said memory areas forms the liner dielectric, in said consent, fills phase-change storage material then.
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| CN2009100509881A CN101882602B (en) | 2009-05-08 | 2009-05-08 | Manufacturing method of phase-changing random access memory |
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| CN102447060B (en) * | 2010-10-14 | 2014-01-08 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for phase change memory |
| CN102479921B (en) * | 2010-11-25 | 2013-12-04 | 中芯国际集成电路制造(北京)有限公司 | Manufacture method of phase change memory |
| CN102487068B (en) * | 2010-12-02 | 2015-09-02 | 中芯国际集成电路制造(北京)有限公司 | Phase transition storage manufacture method |
| CN102569648B (en) * | 2010-12-27 | 2014-09-03 | 中芯国际集成电路制造(北京)有限公司 | Phase change memory and manufacturing method thereof |
| CN102544358B (en) | 2010-12-27 | 2014-02-05 | 中芯国际集成电路制造(北京)有限公司 | Phase change memory and preparation method thereof |
| CN102655090B (en) * | 2011-03-04 | 2014-11-26 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of vertical diode array |
| CN103296049B (en) * | 2012-03-02 | 2016-01-06 | 中芯国际集成电路制造(上海)有限公司 | Phase transition storage and manufacture method thereof |
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| US20080303016A1 (en) * | 2005-02-24 | 2008-12-11 | Woo-Yeong Cho | Phase change memory devices employing cell diodes and methods of fabricating the same |
| US20090034319A1 (en) * | 2007-07-31 | 2009-02-05 | Samsung Electronics Co., Ltd. | Phase change memory device having schottky diode and method of fabricating the same |
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| US20070285963A1 (en) * | 2003-04-03 | 2007-12-13 | Kabushiki Kaisha Toshiba | Resistance change memory device |
| US20080303016A1 (en) * | 2005-02-24 | 2008-12-11 | Woo-Yeong Cho | Phase change memory devices employing cell diodes and methods of fabricating the same |
| US20080200014A1 (en) * | 2007-02-21 | 2008-08-21 | Samsung Electronics Co., Ltd. | Method of forming a vertical diode and method of manufacturing a semiconductor device using the same |
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