CN101870449A - Multilayer line manufacturing process of wafer-level micro electromechanical system chip encapsulation technology - Google Patents

Multilayer line manufacturing process of wafer-level micro electromechanical system chip encapsulation technology Download PDF

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CN101870449A
CN101870449A CN200910031524A CN200910031524A CN101870449A CN 101870449 A CN101870449 A CN 101870449A CN 200910031524 A CN200910031524 A CN 200910031524A CN 200910031524 A CN200910031524 A CN 200910031524A CN 101870449 A CN101870449 A CN 101870449A
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copper
layer
wafer
chemical
photoresist
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CN101870449B (en
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陈闯
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KUNSHAN XITAI MICROELECTRONICS TECHNOLOGY Co Ltd
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KUNSHAN XITAI MICROELECTRONICS TECHNOLOGY Co Ltd
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Abstract

The invention discloses a multilayer line manufacturing process of wafer-level micro electromechanical system chip encapsulation technology. The process comprises the following flows of: pre-processing, wafer thinning, exposure and development, etching, insulating layer coating, laser drilling, copper sputtering, chemical copper plating pretreatment, chemical copper plating, electric copper plating, exposure and development, copper etching, insulating layer coating and exposure and development, laser drilling, copper sputtering, chemical copper plating pretreatment, chemical copper plating, electric copper plating, exposure and development, copper etching, N (N is more than or equal to 0) times (insulating layer coating and exposure and development, laser drilling, copper sputtering, chemical copper plating pretreatment, chemical copper plating, electric copper plating, exposure and development, copper etching), acid chemical nickel plating, chemical cyanide gilding, solder mask coating and exposure and development, BGA forming, and subsequent cutting, testing and packing. The process for forming a multilayer mutual conduction line effectively deals with product size reduction and line denseness, and improves the yield of products.

Description

The multilayer line manufacturing process of wafer-level micro electromechanical system chip encapsulation technology
Technical field
The present invention relates to the manufacture craft field of circuit and weld pad in the wafer-level chip of micro-electro-mechanical system through-silicon-via encapsulation technology product.
Background technology
(the English abbreviation: MEMS) (English is called for short the chip through-silicon-via wafer current level micro electromechanical system: TSV) in the encapsulation technology manufacturing process, generally adopt individual layer line layout form, expose wafer inner conductive piece (English abbreviation: pad) by preceding operation, sputtering aluminum, photoresistance coating exposure imaging, nickel plating, remove photoresist, deluster and carve the aluminium of glue-line, etching, nickel plating gold, welding resisting layer coating exposure imaging, paste solder printing, technologies such as Reflow Soldering make the wafer inside and outside electrically interconnected, produce needed circuit and BGA (English abbreviation: BGA) weld pad.General line width and circuit or weld pad spacing are at the 40-100 micrometer range, spacing between the weld pad edge is many about 300 microns, electrically interconnectedly in the spacing about 300 microns go out three to four circuits from the wafer inside and outside, and satisfy the requirement of live width line-spacing, operation faces various problems under the prior art condition, there is etching unclean during as etching, disconnected short circuit problem etc., it is extremely difficult to avoid bad problem, directly influence output and yield, and the design of customer line must be drawn three or above circuit sometimes in spacing between the weld pad edge, make production technology face adverse conditions, the yield cost advantage no longer, thereby the restriction competitiveness of product.
Summary of the invention
In order to overcome above-mentioned defective, the invention provides a kind of multilayer line manufacturing process of wafer-level micro electromechanical system chip encapsulation technology, multi-line on client's small size, wide circuit and little weld pad spacing each side needs can be reached, and the product yield can be effectively improved.
The present invention for the technical scheme that solves its technical problem and adopt is:
A kind of multilayer line manufacturing process of wafer-level micro electromechanical system chip encapsulation technology, with the integrated circuit of wafer (the English abbreviation: IC) face is a wafer frontside, is undertaken by following processing step:
1.. preceding processing procedure: simultaneously form the macromolecule resin class photoresist face that the IC with wafer frontside is complementary at glass, be bonded together by the photoresist face and the wafer frontside of bonding machine with described glass;
2.. wafer attenuate: wafer is thinned to the setting dimensional thickness from grinding back surface, the internal stress that produces when again wafer rear being carried out plasma etching with the removal grinding;
3.. exposure imaging: after wafer rear applies photoresist, toast, developed in the photoresist exposure back of wafer rear, need the etched photoresist developing that applies in the localities to fall wafer rear by design;
4.. etching: wafer is put into plasma etcher, wafer rear need be etched away and form groove in etched place, not needing etched place can be not etched because surface-coated has the photoresist protection, and this groove comes out the conducting block of wafer frontside part;
5.. be coated with insulating layer coating: adopt the mode of electrophoresis to apply macromolecule polymeric material, toast behind the formation insulating barrier at wafer rear;
6.. laser drill: be in the insulating barrier and the conducting block at wafer groove place by laser breakdown, the conducting block that punctures the position is come out from insulating barrier;
7.. sputter copper: the copper sputter is formed one deck conductive copper layer at whole wafer rear, and the conducting block that exposes after making step 6. is connected with conductive copper layer, thereby the conducting block of wafer inside IC is communicated with and is directed to wafer rear by spattering copper-plated mode;
8.. electroless copper pre-treatment: make the conductive copper layer rough surface by acid etching, make conductive copper layer that a good binding surface be arranged when the electroless copper of postorder;
9.. electroless copper: form certain thickness chemical copper layer on the conductive copper layer surface, because during sputter copper, the thickness of the thickness of ditch buried copper and the surperficial copper of wafer rear variant (1: 6), and it is thinner to spatter copper plate, electroless copper has the degree of depth and evenly plating preferably, and making postorder electroplate tube has the favorable conductive effect;
10.. electro-coppering: plate layer of copper by plating mode at the chemical copper laminar surface of step after 9., form copper electroplating layer, because copper electroplating layer compact structure, good conductivity, with conductive copper layer and chemical copper layer be same metal, do not exist the electromotive force potential difference of different metal to cause, and copper metal oxidation resistance and electric conductivity are all good than aluminum metal in conjunction with unusual problem;
Figure B2009100315246D0000031
Exposure imaging: the mode by electrophoresis is at surface-coated one deck photoresist of copper electroplating layer, to the circuit that form to need behind the photoresist exposure imaging and the figure of BGA (BGA) weld pad, the photoresist of the unwanted part surface of copper electroplating layer beyond the figure is developed by design;
Figure B2009100315246D0000032
The copper etching: by the method for alkaline etching, the unwanted partial etching of copper electroplating layer beyond the figure is fallen, form circuit and BGA weld pad, the certain thickness pure tin has corrosion resistance to alkaline etch bath, has only the copper of exposure to be removed under the attack of alkaline etch bath;
Figure B2009100315246D0000033
Insulating barrier coating and exposure imaging: apply the anti-welding dielectric ink of one deck by the mode that sprays or rotate at wafer rear, and by exposure imaging mode the anti-welding dielectric ink beyond the BGA weld pad part of road and setting of going offline that develops, make anti-welding dielectric ink covering protection circuit, and with the selectable covering protection of BGA weld pad or come out;
Figure B2009100315246D0000041
Laser drill: by design the BGA weld pad of circuit and setting is partly gone up the anti-welding dielectric ink that applies by laser and puncture, be convenient to the UNICOM and the processing of successive process circuit;
Figure B2009100315246D0000042
Sputter copper: the copper sputter is formed one deck conductive copper layer at whole wafer rear, make step The back is connected with conductive copper layer by the circuit of the anti-welding dielectric ink part of design puncture and the BGA weld pad of setting;
Figure B2009100315246D0000044
Electroless copper pre-treatment: make the conductive copper layer rough surface by acid etching;
Figure B2009100315246D0000045
Electroless copper: form certain thickness chemical copper layer on the conductive copper layer surface;
Electro-coppering: plate layer of copper at the chemical copper laminar surface of step after 9. by plating mode, form copper electroplating layer;
Figure B2009100315246D0000047
Exposure imaging: the mode by electrophoresis is at surface-coated one deck photoresist of copper electroplating layer, to the circuit that form to need behind the photoresist exposure imaging and the figure of BGA weld pad, the photoresist of the unwanted part surface of copper electroplating layer beyond the figure is developed by design;
Figure B2009100315246D0000048
By the method for alkaline etching, the unwanted partial etching of copper electroplating layer beyond the figure is fallen, form circuit and BGA weld pad;
Figure B2009100315246D0000049
By design number of times repeating step Form line layer with this by design number of times+2 layer of design mutual conduction, reach multilayer and blind buried via hole designing requirement, easier when circuit is made, promote competitiveness of product (this example described by design mutual conduction be by blind buried via hole manufacturing technology reach mutual conduction between multilayer line);
Acid chemical plating nickel: chemical nickel plating on the circuit of wafer rear and BGA weld pad, form chemical Ni-plating layer, the chemical nickel plating coating of compact structure can play the effect of protection to the copper layer;
Figure B2009100315246D0000051
The cyanide chemical gilding: the surface at chemical Ni-plating layer is thin golden by form coating one deck of chemical gilding, form Gold plated Layer, because the nickel dam on circuit and the BGA weld pad is suitable oxidized, problem comes off in the time of can causing corrosion and welding, therefore need be at the form coating one deck thin gold of nickel surface by chemical gilding, play route protection, but reach the effect that the BGA weld pad reaches good layer;
Figure B2009100315246D0000052
Welding resisting layer coating and exposure imaging: the mode by rotation is at surface-coated one deck anti-solder ink of Gold plated Layer, and develops to fall by the anti-solder ink of exposure imaging mode with the logicalnot circuit part, thereby with the circuit covering protection, the BGA weld pad come out;
Figure B2009100315246D0000053
The BGA moulding: lead-free tin cream is coated on the steel mesh, and the mode by the scraper printing is imprinted on BGA weld pad place with the lead-free tin cream on the steel mesh, with the Reflow Soldering mode tin cream is melt into the tin ball forming;
Figure B2009100315246D0000054
Follow-up cutting testing package: wafer is cut back test and vacuum-packed by design.
The invention has the beneficial effects as follows: through repeatedly welding resisting layer coating development, utilize the technology of insulating barrier coating, copper etching, laser drill and electroless plating to realize client's multi-line on small size, the each side of wide circuit and little weld pad spacing needs; Pass through repeating step
Figure B2009100315246D0000055
And the formation multilayer mutual conduction line successfully manages product size downsizing and product circuit densification, improves the product yield.
The specific embodiment
Embodiment: a kind of multilayer line manufacturing process of wafer-level micro electromechanical system chip encapsulation technology is a wafer frontside with the IC face of wafer, is undertaken by following processing step:
1.. preceding processing procedure: simultaneously form the macromolecule resin class photoresist face that the IC with wafer frontside is complementary at glass, be bonded together by the photoresist face and the wafer frontside of bonding machine with described glass;
2.. wafer attenuate: wafer is thinned to the setting dimensional thickness from grinding back surface, the internal stress that produces when again wafer rear being carried out plasma etching with the removal grinding;
3.. exposure imaging: after wafer rear applies photoresist, toast, developed in the photoresist exposure back of wafer rear, need the etched photoresist developing that applies in the localities to fall wafer rear by design;
4.. etching: wafer is put into plasma etcher, wafer rear need be etched away and form groove in etched place, not needing etched place can be not etched because surface-coated has the photoresist protection, and this groove comes out the conducting block of wafer frontside part;
5.. be coated with insulating layer coating: adopt the mode of electrophoresis to apply macromolecule polymeric material, toast behind the formation insulating barrier at wafer rear;
6.. laser drill: be in the insulating barrier and the conducting block at wafer groove place by laser breakdown, the conducting block that punctures the position is come out from insulating barrier;
7.. sputter copper: the copper sputter is formed one deck conductive copper layer at whole wafer rear, and the conducting block that exposes after making step 6. is connected with conductive copper layer, thereby the conducting block of wafer inside IC is communicated with and is directed to wafer rear by spattering copper-plated mode;
8.. electroless copper pre-treatment: make the conductive copper layer rough surface by acid etching, make conductive copper layer that a good binding surface be arranged when the electroless copper of postorder;
9.. electroless copper: form certain thickness chemical copper layer on the conductive copper layer surface, because during sputter copper, the thickness of the thickness of ditch buried copper and the surperficial copper of wafer rear variant (1: 6), and it is thinner to spatter copper plate, electroless copper has the degree of depth and evenly plating preferably, and making postorder electroplate tube has the favorable conductive effect;
10.. electro-coppering: plate layer of copper by plating mode at the chemical copper laminar surface of step after 9., form copper electroplating layer, because copper electroplating layer compact structure, good conductivity, with conductive copper layer and chemical copper layer be same metal, do not exist the electromotive force potential difference of different metal to cause, and copper metal oxidation resistance and electric conductivity are all good than aluminum metal in conjunction with unusual problem;
Exposure imaging: the mode by electrophoresis is at surface-coated one deck photoresist of copper electroplating layer, to the circuit that form to need behind the photoresist exposure imaging and the figure of BGA (BGA) weld pad, the photoresist of the unwanted part surface of copper electroplating layer beyond the figure is developed by design;
Figure B2009100315246D0000072
The copper etching: by the method for alkaline etching, the unwanted partial etching of copper electroplating layer beyond the figure is fallen, form circuit and BGA weld pad, the certain thickness pure tin has corrosion resistance to alkaline etch bath, has only the copper of exposure to be removed under the attack of alkaline etch bath;
Figure B2009100315246D0000073
Insulating barrier coating and exposure imaging: apply the anti-welding dielectric ink of one deck by the mode that sprays or rotate at wafer rear, and by exposure imaging mode the anti-welding dielectric ink beyond the BGA weld pad part of road and setting of going offline that develops, make anti-welding dielectric ink covering protection circuit, and with the selectable covering protection of BGA weld pad or come out;
Figure B2009100315246D0000074
Laser drill: by design the BGA weld pad of circuit and setting is partly gone up the anti-welding dielectric ink that applies by laser and puncture, be convenient to the UNICOM and the processing of successive process circuit;
Figure B2009100315246D0000075
Sputter copper: the copper sputter is formed one deck conductive copper layer at whole wafer rear, make step
Figure B2009100315246D0000076
The back is connected with conductive copper layer by the circuit of the anti-welding dielectric ink part of design puncture and the BGA weld pad of setting;
Figure B2009100315246D0000081
Electroless copper pre-treatment: make the conductive copper layer rough surface by acid etching;
Electroless copper: form certain thickness chemical copper layer on the conductive copper layer surface;
Figure B2009100315246D0000083
Electro-coppering: plate layer of copper at the chemical copper laminar surface of step after 9. by plating mode, form copper electroplating layer;
Figure B2009100315246D0000084
Exposure imaging: the mode by electrophoresis is at surface-coated one deck photoresist of copper electroplating layer, to the circuit that form to need behind the photoresist exposure imaging and the figure of BGA weld pad, the photoresist of the unwanted part surface of copper electroplating layer beyond the figure is developed by design;
Figure B2009100315246D0000085
By the method for alkaline etching, the unwanted partial etching of copper electroplating layer beyond the figure is fallen, form circuit and BGA weld pad;
Figure B2009100315246D0000086
By design number of times repeating step
Figure B2009100315246D0000087
Form line layer with this by design number of times+2 layer of design mutual conduction, reach multilayer and blind buried via hole designing requirement, easier when circuit is made, promote competitiveness of product (this example described by design mutual conduction be by blind buried via hole manufacturing technology reach mutual conduction between multilayer line);
Acid chemical plating nickel: chemical nickel plating on the circuit of wafer rear and BGA weld pad, form chemical Ni-plating layer, the chemical nickel plating coating of compact structure can play the effect of protection to the copper layer;
Figure B2009100315246D0000089
The cyanide chemical gilding: the surface at chemical Ni-plating layer is thin golden by form coating one deck of chemical gilding, form Gold plated Layer, because the nickel dam on circuit and the BGA weld pad is suitable oxidized, problem comes off in the time of can causing corrosion and welding, therefore need be at the form coating one deck thin gold of nickel surface by chemical gilding, play route protection, but reach the effect that the BGA weld pad reaches good layer;
Figure B2009100315246D00000810
Welding resisting layer coating and exposure imaging: the mode by rotation is at surface-coated one deck anti-solder ink of Gold plated Layer, and develops to fall by the anti-solder ink of exposure imaging mode with the logicalnot circuit part, thereby with the circuit covering protection, the BGA weld pad come out;
The BGA moulding: lead-free tin cream is coated on the steel mesh, and the mode by the scraper printing is imprinted on BGA weld pad place with the lead-free tin cream on the steel mesh, with the Reflow Soldering mode tin cream is melt into the tin ball forming;
Figure B2009100315246D0000092
Follow-up cutting testing package: wafer is cut back test and vacuum-packed by design.

Claims (1)

1. the multilayer line manufacturing process of a wafer-level micro electromechanical system chip encapsulation technology, it is characterized in that: the integrated circuit face with wafer is a wafer frontside, is undertaken by following processing step:
1.. preceding processing procedure: simultaneously form the macromolecule resin class photoresist face that the integrated circuit with wafer frontside is complementary at glass, be bonded together by the photoresist face and the wafer frontside of bonding machine with described glass;
2.. wafer attenuate: wafer is thinned to the setting dimensional thickness from grinding back surface, again wafer rear is carried out plasma etching;
3.. exposure imaging: after wafer rear applies photoresist, toast, developed in the photoresist exposure back of wafer rear, need the etched photoresist developing that applies in the localities to fall wafer rear by design;
4.. etching: wafer is put into plasma etcher, need etched place to etch away and form groove wafer rear, this groove comes out wafer frontside conducting block partly;
5.. be coated with insulating layer coating: adopt the mode of electrophoresis to apply macromolecule polymeric material, toast behind the formation insulating barrier at wafer rear;
6.. laser drill: be in the insulating barrier and the conducting block at wafer groove place by laser breakdown, the conducting block that punctures the position is come out from insulating barrier;
7.. sputter copper: the copper sputter is formed one deck conductive copper layer at whole wafer rear, and the conducting block that exposes after making step 6. is connected with conductive copper layer;
8.. electroless copper pre-treatment: make the conductive copper layer rough surface by acid etching;
9.. electroless copper: form certain thickness chemical copper layer on the conductive copper layer surface;
10.. electro-coppering: plate layer of copper at the chemical copper laminar surface of step after 9. by plating mode, form copper electroplating layer;
Figure F2009100315246C0000021
Exposure imaging: the mode by electrophoresis is at surface-coated one deck photoresist of copper electroplating layer, to the circuit that form to need behind the photoresist exposure imaging and the figure of BGA weld pad, the photoresist of the unwanted part surface of copper electroplating layer beyond the figure is developed by design;
Figure F2009100315246C0000022
Copper etching: by the method for alkaline etching, the unwanted partial etching of copper electroplating layer beyond the figure is fallen, form circuit and BGA weld pad;
Figure F2009100315246C0000023
Insulating barrier coating and exposure imaging: apply the anti-welding dielectric ink of one deck in the mode of wafer rear by spraying or rotation, and by exposure imaging mode the anti-welding dielectric ink beyond the BGA weld pad part of road and setting of going offline that develops;
Figure F2009100315246C0000024
Laser drill: by design the BGA weld pad of circuit and setting is partly gone up the anti-welding dielectric ink that applies by laser and puncture, be convenient to the UNICOM and the processing of successive process circuit;
Figure F2009100315246C0000025
Sputter copper: the copper sputter is formed one deck conductive copper layer at whole wafer rear, make step The back is connected with conductive copper layer by the circuit of the anti-welding dielectric ink part of design puncture and the BGA weld pad of setting;
Figure F2009100315246C0000027
Electroless copper pre-treatment: make the conductive copper layer rough surface by acid etching;
Figure F2009100315246C0000028
Electroless copper: form certain thickness chemical copper layer on the conductive copper layer surface;
Figure F2009100315246C0000029
Electro-coppering: plate layer of copper at the chemical copper laminar surface of step after 9. by plating mode, form copper electroplating layer;
Figure F2009100315246C00000210
Exposure imaging: the mode by electrophoresis is at surface-coated one deck photoresist of copper electroplating layer, to the circuit that form to need behind the photoresist exposure imaging and the figure of BGA weld pad, the photoresist of the unwanted part surface of copper electroplating layer beyond the figure is developed by design;
Figure F2009100315246C0000031
By the method for alkaline etching, the unwanted partial etching of copper electroplating layer beyond the figure is fallen, form circuit and BGA weld pad;
Figure F2009100315246C0000032
By design number of times repeating step
Figure F2009100315246C0000033
Form line layer with this by design number of times+2 layer of design mutual conduction;
Figure F2009100315246C0000034
Acid chemical plating nickel: chemical nickel plating on the circuit of wafer rear and BGA weld pad forms chemical Ni-plating layer;
Figure F2009100315246C0000035
The cyanide chemical gilding: the surface at chemical Ni-plating layer is thin golden by form coating one deck of chemical gilding, forms Gold plated Layer;
Figure F2009100315246C0000036
Welding resisting layer coating and exposure imaging: the mode by rotation is at surface-coated one deck anti-solder ink of Gold plated Layer, and develops to fall by the anti-solder ink of exposure imaging mode with the logicalnot circuit part;
Figure F2009100315246C0000037
The BGA moulding: lead-free tin cream is coated on the steel mesh, and the mode by the scraper printing is imprinted on BGA weld pad place with the lead-free tin cream on the steel mesh, with the Reflow Soldering mode tin cream is melt into the tin ball forming;
Figure F2009100315246C0000038
Follow-up cutting testing package: wafer is cut back test and vacuum-packed by design.
CN200910031524.6A 2009-04-22 2009-04-22 Multilayer line manufacturing process of wafer-level micro electromechanical system chip encapsulation technology Expired - Fee Related CN101870449B (en)

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CN102548243A (en) * 2010-12-08 2012-07-04 北大方正集团有限公司 Method and system for manufacturing bumps on circuit boards and circuit board utilizing same
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CN104201118A (en) * 2014-08-26 2014-12-10 南通富士通微电子股份有限公司 Chip level packaging method
CN111799178A (en) * 2020-07-17 2020-10-20 绍兴同芯成集成电路有限公司 Double-sided copper-plating thick film process for ultrathin wafer

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Publication number Priority date Publication date Assignee Title
CN102548243A (en) * 2010-12-08 2012-07-04 北大方正集团有限公司 Method and system for manufacturing bumps on circuit boards and circuit board utilizing same
CN102548243B (en) * 2010-12-08 2015-12-16 北大方正集团有限公司 Make the method for circuit board salient point, system and circuit board
CN102591138A (en) * 2011-01-07 2012-07-18 昆山西钛微电子科技有限公司 Double-light-resistance wall and preparation method thereof
CN102591138B (en) * 2011-01-07 2014-05-28 昆山西钛微电子科技有限公司 Double-light-resistance wall applied in silicon perforation wafer level packaging and preparation method thereof
CN104201118A (en) * 2014-08-26 2014-12-10 南通富士通微电子股份有限公司 Chip level packaging method
CN111799178A (en) * 2020-07-17 2020-10-20 绍兴同芯成集成电路有限公司 Double-sided copper-plating thick film process for ultrathin wafer
CN111799178B (en) * 2020-07-17 2022-02-01 绍兴同芯成集成电路有限公司 Double-sided copper-plating thick film process for ultrathin wafer

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