CN101866928A - Word line-sharing contactless SONOS split gate type flash memory - Google Patents
Word line-sharing contactless SONOS split gate type flash memory Download PDFInfo
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Abstract
The invention provides a word line-sharing contactless SONOS split gate type flash memory. In the obtained flash memory device, two storage bit cells share one word line, different operating voltages are applied to the word line, a first control gate, a second control gate, a first bit line and a second bit line to read, program and erase the storage bit cells, and the bit line-sharing structure enables the split gate type flash memory to effectively reduce the area of a chip under the condition of keeping the electric isolation performance of the chip unchanged and simultaneously can avoid the over-erase problems. Meanwhile, the contactless design enables the flash memory device to have the characteristics of small size and process compatibility with the CMOS traditional process, thereby being beneficial to further reducing the size of the device.
Description
Technical field
The present invention relates to semiconductor design and make the field, and be particularly related to a kind of contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory of shared word line.
Background technology
Flash memory is convenient with it, the storage density height, and advantages such as good reliability become the focus of studying in the non-volatility memorizer.Since first flash memory products comes out from the 1980s, development and the demand of each electronic product along with technology to storing, flash memory is widely used in mobile phone, notebook, palmtop PC and USB flash disk etc. move and communication apparatus in, flash memory is a kind of non-volatility memory, its operation principles is to control the switch of gate pole passage to reach the purpose of storage data by the critical voltage that changes transistor or memory cell, make the data that are stored in the memory can be, and flash memory be a kind of special construction of electric erasable and programmable read-only memory because of power interruptions does not disappear.Nowadays flash memory has occupied most of market share of non-volatile semiconductor memory, becomes non-volatile semiconductor memory with fastest developing speed.
Yet existing flash memory is in the high storage density of marching toward more, owing to be subjected to the restriction of program voltage, improve storage density by reduction of device size and will face very big challenge, thereby the flash memory of development high storage density is the important motive force of flash memory technology development.Traditional flash memory owing to be subjected to the restriction of structure, realizes that the program voltage of device further reduces to be faced with very big challenge in the high storage density of marching toward more.
Generally speaking, flash memory is the combination of grid dividing structure or stacking gate structure or two kinds of structures.Gate-division type flash memory is because its special structure, compare the stacking gate flash memory and all embody its particular performances advantage in programming with when wiping, therefore divide grid formula structure owing to have high programming efficiency, the structure of word line can be avoided advantages such as " cross and wipe ", uses particularly extensive.Thereby but since gate-division type flash memory with respect to the stacking gate flash memory many a word line make area of chip also can increase, the size that therefore how further reduces chip in the raising chip performance is to need the problem of solution badly.
Simultaneously, along with the memory device size is constantly dwindled continuous rising with storage density, the size that is formed at the contact hole in the inner layer dielectric layer also can become littler, yet this inner layer dielectric layer must keep rational thickness, make this contact hole need keep sizable depth-to-width ratio (depth/width), thereby make the contact point on the Semiconductor substrate occupy the sizable ratio of whole memory unit area, become the key factor that restriction memory device size and storage density further develop.
Summary of the invention
The present invention proposes a kind of contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory of shared word line, and its flush memory device that obtains can dwindle area of chip effectively under the constant situation of the electric isolation performance that keeps chip, also can avoid the problem of wiping simultaneously.
In order to achieve the above object, the present invention proposes a kind of contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory of shared word line, comprising:
Semiconductor substrate has the source region and the drain region that are provided with at interval on it;
Channel region is between described source region and drain region;
First bit line and second bit line are connected to described source region and drain region;
The silicon nitride memory cell is positioned at described channel region top;
Word line is positioned at described silicon nitride memory cell top, and described word line both sides have arcuate structure and extend to described first bit line and second bit line top, and isolated by insulating barrier and described first bit line and the second bit line top;
First control gate and second control gate, be arranged at described silicon nitride memory cell and word line both sides respectively, wherein, described silicon nitride memory cell comprises first memory cell and second memory cell, contiguous first control gate of described first memory cell, contiguous second control gate of described second memory cell.
Further, respectively described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied first storage bit unit and read voltage, realize that first storage bit unit reads.
Further, first storage bit unit that described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied reads voltage and is respectively 2.5V, 2V, 4V, 0V and 0.8V, realizes that first storage bit unit reads.
Further, respectively described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied second storage bit unit and read voltage, realize that second storage bit unit reads.
Further, second storage bit unit that described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied reads voltage and is respectively 2.5V, 4V, 2V, 0.8V and 0V, realizes that second storage bit unit reads.
Further, respectively described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied the first storage bit unit program voltage, realize the programming of first storage bit unit.
Further, the first storage bit unit program voltage that described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied is respectively 1.4V, 8V, 5V, 0V and 5V, realizes the programming of first storage bit unit.
Further, respectively described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied the second storage bit unit program voltage, realize the programming of second storage bit unit.
Further, the second storage bit unit program voltage that described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied is respectively 1.4V, 5V, 8V, 5V and 0V, realizes the programming of second storage bit unit.
Further, respectively described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied the storage bit unit erasing voltage, realize that first storage bit unit and second storage bit unit wipe.
Further, the storage bit unit erasing voltage that described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied is respectively 0V, 10.5V, 10.5V, 10.5V and 10.5V, realizes that first storage bit unit and second storage bit unit wipe.
The contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory of the shared word line that the present invention proposes, the flush memory device that obtains is shared two storage bit unit and is used a word line, realize reading, programming and wiping by word line, first control gate, second control gate, first bit line and second bit line being applied different operating voltages to storage bit unit, the structure of share bit lines make gate-division type flash memory its can be under the constant situation of the electric isolation performance that keeps chip, dwindle area of chip effectively, also can avoid the problem of wiping simultaneously.Adopt contactless design simultaneously, it is little to make that flush memory device has size, and the characteristics of technology and CMOS traditional handicraft compatibility help device size and further dwindle.
Description of drawings
Figure 1 shows that the contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory structural representation of the shared word line of preferred embodiment of the present invention.
Embodiment
In order more to understand technology contents of the present invention, especially exemplified by specific embodiment and cooperate appended graphic being described as follows.
The present invention proposes a kind of contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory of shared word line, and its flush memory device that obtains can dwindle area of chip effectively under the constant situation of the electric isolation performance that keeps chip, also can avoid the problem of wiping simultaneously.
Please refer to Fig. 1, Figure 1 shows that the contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory structural representation of the shared word line of preferred embodiment of the present invention.The present invention proposes a kind of contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory of shared word line, comprising: Semiconductor substrate 10 has the source region 11 and the drain region 12 that are provided with at interval on it; Channel region 13 is between described source region 11 and drain region 12; First bit line 21 and second bit line 22 are connected to described source region 11 and drain region 12; Silicon nitride memory cell 30 is positioned at described channel region 13 tops; Word line 50, be positioned at described silicon nitride memory cell 30 tops, described word line 50 both sides have arcuate structure 51,52 and extend to described first bit line 21 and second bit line, 22 tops, and it is isolated to pass through insulating barrier 61,62 and described first bit line 21 and second bit line, 22 tops; First control gate 41 and second control gate 42, be arranged at described silicon nitride memory cell 30 and word line 50 both sides respectively, wherein, described silicon nitride memory cell 30 comprises first memory cell 31 and second memory cell 32, described first memory cell, 31 contiguous first control gates 41, described second memory cell, 32 contiguous second control gates 42.
The preferred embodiment according to the present invention, first bit line 21 of the present invention and second bit line 22, be directly connected in described source region 11 and drain region 12 respectively, and the mode that does not need to form contact point by the making contact hole on Semiconductor substrate 10 connects, design with non-contact-point, make flush memory device have littler size, help device size and further dwindle.
In the preferred embodiment of the present invention, there is electric current between source region 11 and drain region 12, to flow in the raceway groove 13, described first storage bit unit 31 and second storage bit unit 32 have or not charge storage can influence size of current in the raceway groove 13, when described first storage bit unit 31 and second storage bit unit 32 have electric charge, electric current is very little in the raceway groove 13, otherwise when described first storage bit unit 31 and second storage bit unit, 32 no electric charges, electric current is very big in the raceway groove 13, setting raceway groove 13 interior little current status is " 0 ", setting raceway groove 130 interior current states is " 1 ", described like this first storage bit unit 31 and second storage bit unit 32 have or not the state of charge storage to can be used as differentiation storage " 0 " or " 1 " information state, realize the function that first storage bit unit 31 and second storage bit unit, 32 information stores read.
The preferred embodiment according to the present invention applies first storage bit unit to described word line 50, described first control gate 41, described second control gate 42, described first bit line 21 and described second bit line 22 respectively and reads voltage, realizes that first storage bit unit reads.
Further, first storage bit unit that described word line 50, described first control gate 41, described second control gate 42, described first bit line 21 and described second bit line 22 are applied reads voltage and is respectively 2.5V, 2V, 4V, 0V and 0.8V, realizes that first storage bit unit reads.
The preferred embodiment according to the present invention applies second storage bit unit to described word line 50, described first control gate 41, described second control gate 42, described first bit line 21 and described second bit line 22 respectively and reads voltage, realizes that second storage bit unit reads.
Further, second storage bit unit that described word line 50, described first control gate 41, described second control gate 42, described first bit line 21 and described second bit line 22 are applied reads voltage and is respectively 2.5V, 4V, 2V, 0.8V and 0V, realizes that second storage bit unit reads.
Source-drain electrodes voltage between source region 11 and drain region 12 is enough high, is enough to cause some high energy electron to cross insulation dielectric layer, and enters the storage space unit on the insulation dielectric layer, and this process is called hot electron and injects.And the composition of described insulation dielectric layer is the oxide of silicon or the nitride of silicon, and as materials such as silicon dioxide or silicon nitrides, it is between Semiconductor substrate 10 and described first storage bit unit 31 and second storage bit unit 32.
The preferred embodiment according to the present invention, described respectively word line 50, described first control gate 41, described second control gate 42, described first bit line 21 and described second bit line 22 apply the first storage bit unit program voltage, realize the programming of first storage bit unit.In the preferred embodiment of the present invention, after applying programing work voltage, have electronics 12 to flow to source region 11 from the drain region in the raceway groove 13, portions of electronics is injected in described first storage bit unit 31 by the hot electron injection mode, realizes the programming operation of first storage bit unit.
Further, the first storage bit unit program voltage that described word line 50, described first control gate 41, described second control gate 42, described first bit line 21 and described second bit line 22 are applied is respectively 1.4V, 8V, 5V, 0V and 5V, realizes the programming of first storage bit unit.
The preferred embodiment according to the present invention applies the second storage bit unit program voltage to described word line 50, described first control gate 41, described second control gate 42, described first bit line 21 and described second bit line 22 respectively, realizes the programming of second storage bit unit.In the preferred embodiment of the present invention, after applying programing work voltage, have electronics 11 to flow to drain region 12 from the source region in the raceway groove 13, portions of electronics is injected in second storage bit unit 32 by the hot electron injection mode, realizes the programming operation of second storage bit unit.
Further, the second storage bit unit program voltage that described word line 50, described first control gate 41, described second control gate 42, described first bit line 21 and described second bit line 22 are applied is respectively 1.4V, 5V, 8V, 5V and 0V, realizes the programming of second storage bit unit.
The preferred embodiment according to the present invention, respectively described word line 50, described first control gate 41, described second control gate 42, described first bit line 21 and described second bit line 22 are applied the storage bit unit erasing voltage, realize that first storage bit unit and second storage bit unit wipe.Apply under the operating voltage condition at this, the electronics FN (Fowler-Nordheim) under high electric field that is stored in described first storage bit unit 31 and second storage bit unit 32 is tunneling to Semiconductor substrate 10 ends, flow away by Semiconductor substrate 10 ends, realize the erase operation of first storage bit unit 31 and second storage bit unit 32.
The storage bit unit erasing voltage that further described word line 50, described first control gate 41, described second control gate 42, described first bit line 21 and described second bit line 22 is applied is respectively 0V, 10.5V, 10.5V, 10.5V and 10.5V, realizes that first storage bit unit and second storage bit unit wipe.
The contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory of the shared word line that the present invention proposes, the flush memory device that obtains is shared two storage bit unit and is used a word line, realize reading, programming and wiping by word line, first control gate, second control gate, first bit line and second bit line being applied different operating voltages to storage bit unit, the structure of share bit lines make gate-division type flash memory its can be under the constant situation of the electric isolation performance that keeps chip, dwindle area of chip effectively, also can avoid the problem of wiping simultaneously.Adopt contactless design simultaneously, it is little to make that flush memory device has size, and the characteristics of technology and CMOS traditional handicraft compatibility help device size and further dwindle.
Though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (11)
1. the contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory of a shared word line is characterized in that, comprising:
Semiconductor substrate has the source region and the drain region that are provided with at interval on it;
Channel region is between described source region and drain region;
First bit line and second bit line are connected to described source region and drain region;
The silicon nitride memory cell is positioned at described channel region top;
Word line is positioned at described silicon nitride memory cell top, and described word line both sides have arcuate structure and extend to described first bit line and second bit line top, and isolated by insulating barrier and described first bit line and the second bit line top;
First control gate and second control gate, be arranged at described silicon nitride memory cell and word line both sides respectively, wherein, described silicon nitride memory cell comprises first memory cell and second memory cell, contiguous first control gate of described first memory cell, contiguous second control gate of described second memory cell.
2. the contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory of shared word line according to claim 1, it is characterized in that, respectively described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied first storage bit unit and read voltage, realize that first storage bit unit reads.
3. the contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory of shared word line according to claim 2, it is characterized in that, first storage bit unit that described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied reads voltage and is respectively 2.5V, 2V, 4V, 0V and 0.8V, realizes that first storage bit unit reads.
4. the contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory of shared word line according to claim 1, it is characterized in that, respectively described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied second storage bit unit and read voltage, realize that second storage bit unit reads.
5. the contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory of shared word line according to claim 4, it is characterized in that, second storage bit unit that described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied reads voltage and is respectively 2.5V, 4V, 2V, 0.8V and 0V, realizes that second storage bit unit reads.
6. the contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory of shared word line according to claim 1, it is characterized in that, respectively described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied the first storage bit unit program voltage, realize the programming of first storage bit unit.
7. the contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory of shared word line according to claim 6, it is characterized in that, the first storage bit unit program voltage that described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied is respectively 1.4V, 8V, 5V, 0V and 5V, realizes the programming of first storage bit unit.
8. the contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory of shared word line according to claim 1, it is characterized in that, respectively described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied the second storage bit unit program voltage, realize the programming of second storage bit unit.
9. the contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory of shared word line according to claim 8, it is characterized in that, the second storage bit unit program voltage that described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied is respectively 1.4V, 5V, 8V, 5V and 0V, realizes the programming of second storage bit unit.
10. the contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory of shared word line according to claim 1, it is characterized in that, respectively described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied the storage bit unit erasing voltage, realize that first storage bit unit and second storage bit unit wipe.
11. the contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory of shared word line according to claim 10, it is characterized in that, the storage bit unit erasing voltage that described word line, described first control gate, described second control gate, described first bit line and described second bit line are applied is respectively 0V, 10.5V, 10.5V, 10.5V and 10.5V, realizes that first storage bit unit and second storage bit unit wipe.
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| CN101694845A (en) * | 2009-10-13 | 2010-04-14 | 上海宏力半导体制造有限公司 | Split-gate flash memory sharing word line |
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| US20050012135A1 (en) * | 2002-01-04 | 2005-01-20 | Chia-Ta Hsieh | Split-gate flash with source/drain multi-sharing |
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