CN101860253B - Control system of cascaded high-voltage inverter and method thereof - Google Patents
Control system of cascaded high-voltage inverter and method thereof Download PDFInfo
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- CN101860253B CN101860253B CN2010101851262A CN201010185126A CN101860253B CN 101860253 B CN101860253 B CN 101860253B CN 2010101851262 A CN2010101851262 A CN 2010101851262A CN 201010185126 A CN201010185126 A CN 201010185126A CN 101860253 B CN101860253 B CN 101860253B
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Abstract
The invention discloses a control system of a cascaded inverter, which comprises a cascaded voltage source inverter and a plurality of power units arranged in the cascaded voltage source inverter. The control system is characterized in that each power unit is respectively connected with a field programmable gate array through control fiber, and the field programmable gate array is connected with a main control CPU. Since the field programmable gate array is used as a PWM control pulse generator, and the design adopts the software programming method, compared with the conventional method, the invention has the advantages of low cost, short development cycle and high hardware reliability.
Description
Technical field
The present invention relates to a kind of cascaded inverter control system and method, relate in particular to a kind of cascaded inverter control system and method, belong to mesohigh motor frequency change speed regulating device field with memory output function and reserve troubleshooting function.
Background technology
Cascaded high-voltage frequency converter has become one type of staple product in high voltage converter field because its input, output waveform harmonic content are few, with and modularized design, obtained to use widely in high-power speed governing occasion.But, on the one hand because its power model is numerous, its control system more complicated; On the other hand, cascaded high-voltage frequency converter is used in the driving occasion of visual plant mostly, and is higher to the reliability requirement of its control system.
Cascaded high-voltage frequency converter adopts the mode of power unit cascade to obtain high pressure output, and each power cell adopts modularized design, can replace mutually, and difference is to control the pwm signal difference of each power cell, i.e. phase-shifting carrier wave control.Because power cell quantity is more, thereby needs master control system that more pwm control signal is provided.With 6 grades/6kV concatenated frequency changer is example; Each includes 6 power cells mutually; Three-phase is totally 18 power cells; Need master control system that 18 road pwm control signals are provided, and general maximum 12 road pwm signals that can only provide of DSP, thereby the cascade connection type frequency converter need solve having problems of power cell control signal.
The mode that the control system of cascaded high-voltage frequency converter produces pwm signal mainly contains based on the timing chip form with based on CPLD (CPLD or FPGA) mode.
Adopt the timing chip form, the comparison by DSP accomplishes sinusoidal modulation wave and triangular carrier produces pwm waveform; Utilizing the timing chip to realize the phase shift of pwm signal, need more timing chip, is example with 10 grades of concatenated frequency changer control system; Master control system needs 20 timing chips, has increased control system cost and board area, simultaneously when the DSP fault; System must shut down, and reliability is not high.
Based on CPLD (CPLD or FPGA) mode, two kinds of control modes are arranged:
1) DSP accomplishes the comparison of sinusoidal modulation wave and triangular carrier, and the duration of output high-low level is given programmable logic device, utilizes the phase shift of the clocking capability realization pwm signal of programmable logic device;
2) DSP output modulated sinusoid signal is given programmable logic device, utilizes the clocking capability of programmable logic device to produce each the road triangular carrier through phase shift, and compares with sinusoidal modulation wave, exports each road pwm control signal.With respect to the mode that adopts the timing chip, this dual mode has all been realized reducing the target of number of chips and board area, but still the problem of system-down can't solve the DSP fault time.And when adopting CPLD, receive the restriction of number of logic cells, generally also need three even more CPLD chips.
The present invention has carried out useful improvement for above problem.
Summary of the invention
Technical problem to be solved by this invention is to overcome the deficiency of prior art, and a kind of simple, reliable, practical, cascade connection type Frequency Converter Control system and method flexibly is provided.
Another technical problem to be solved by this invention is to provide a kind of cascade connection type Frequency Converter Control system with memory output function and reserve troubleshooting function.
In order to solve the problem of above-mentioned existence, the present invention adopts following technical scheme:
A kind of control system of cascaded inverter; Comprise the cascade connection type voltage source inverter; A plurality of power cells are set in the cascade connection type voltage source inverter; It is characterized in that: said each power cell links to each other with field programmable gate array (FPGA) through control optical fiber respectively, and said field programmable gate array links to each other with master cpu.
Aforesaid cascaded high-voltage frequency converter control system is characterized in that: said master cpu is digital signal processor (DSP).
The control system of aforesaid cascaded inverter is characterized in that: described cascade connection type voltage source inverter, and the circuit topology that adopts the power cell phase shift to connect, said power cell is the voltage source inverter unit of insulated gate bipolar transistor.
Aforesaid cascaded high-voltage frequency converter control system is characterized in that: said programmable gate array comprises following each functional unit:
CPU Status Monitor: be used to receive the state pulse signal of master cpu, judge the operating state of master cpu to the FPGA timed sending;
Status register: the malfunction, bypass condition and the running frequency information that are used to store frequency converter;
Dual port RAM: be used to receive and preserve the three-phase modulations ripple signal data that master cpu sends, supply FPGA to read and compare to produce the PWM control impuls; Master cpu can read the information of the status register among the FPGA through dual port RAM simultaneously;
Sinusoidal wave address generator: the state information that receives running frequency information and master cpu; After receiving CPU abnormal state signal, according to running frequency information generating address, reading of data gets into buffer memory from dual port RAM;
Triangular-wave generator: according to fault message in the status register and bypass information, produce the multichannel triangular carrier signal of out of phase, and input comparator;
Buffer memory: be used for from the dual port RAM reading of data;
Comparator: compare modulation wave signal and triangular carrier signal in the buffer memory, produce the SPWM signal of power controlling cell power switch on and off;
Communication signal converter: receive the control of reserve failure processor, the parallel SPWM conversion of signals that comparator is produced is to be fit to the serial signal that optical fiber sends.
A kind of control method of cascaded inverter may further comprise the steps: digital signal processor (DSP) sends the three-phase modulations ripple signal data that is used for the control voltage source inverter; The modulation wave signal data that field programmable gate array (FPGA) receiving digital signals processor (DSP) sends, and compare with the triangular carrier of out of phase and to produce the PWM control impuls;
The control method of aforesaid a kind of cascaded inverter, said digital signal processor (DSP) are used for the enforcement and the transaction (control logic, troubleshooting etc.) of PWM control algolithm; Field programmable gate array (FPGA) is used to produce multichannel triangular carrier signal, and the pwm control signal that relatively produces voltage source inverter through modulating wave and triangular carrier, and memory output function and reserve troubleshooting function also realize in FPGA.
The control method of aforesaid a kind of cascaded inverter; Said memory output function is: when digital signal processor (DSP) is out of service in short-term (as crashing); Field programmable gate array (FPGA) latchs the modulation wave signal data that receive; Continuation compares triangular carrier and the modulating wave that latchs and produces the PWM control impuls, the continuation stable operation thereby realization frequency converter frequency converter when DSP withdraws from short-term maintains the original state; After digital signal processor (DSP) resets normally; Read the status register of field programmable gate array (FPGA); Continue to produce three-phase modulations ripple signal according to current frequency converter running status by digital signal processor (DSP), guarantee " seamless switching " of digital signal processor (DSP);
The control method of aforesaid a kind of cascaded inverter; Reserve troubleshooting function is: under the DSP normal operating conditions; Troubleshooting is carried out by digital signal processor (DSP), field programmable gate array (FPGA) with the frequency converter failure state storage in status register; When digital signal processor (DSP) was out of service in short-term, (FPGA) handled frequency converter failure by field programmable gate array, thereby guaranteed the security of operation of frequency convertor system when DSP withdraws from short-term.
The present invention compared with prior art has following advantage:
1, the present invention adopts a slice field programmable gate array (FPGA) as the PWM clamp-pulse generator, adopts the software programming mode to design, and is lower than method cost commonly used, the construction cycle is short, hardware reliability is high;
2, after the employing memory output function, when DSP withdrawed from short-term, frequency convertor system can maintain the original state and continue to move and need not shut down, and has improved the reliability of system greatly;
3, after the employing reserve troubleshooting function, guaranteed the basic protection of system's frequency converter during DSP withdraws from, the fail safe of raising system self.
Description of drawings
Fig. 1 is a cascade connection type voltage source inverter main circuit diagram;
Fig. 2 is field programmable gate array (FPGA) memory output function and reserve troubleshooting schematic diagram of the function;
Fig. 3 is a reserve troubleshooting schematic diagram of the function.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is further described:
The control system of cascaded high-voltage frequency converter of the present invention as shown in Figure 1 has comprised digital signal processor (DSP) and field programmable gate array (FPGA), and both interfaces are as shown in Figure 1.
The production process of PWM control impuls is following among the present invention:
1) at first initialization after system powers on, digital signal processor (DSP) obtains target frequency, initial frequency and raising frequency, frequency reducing curve; Its triangular-wave generator of programmable gate array (FPGA) initialization is provided with each road triangular carrier initial phase and amplitude.
2) digital signal processor (DSP) is responsible for the realization of control algolithm, calculates required three-phase modulations ripple signal Mx (p represents out of phase a, b, c), and sends into field programmable gate array (FPGA) through bus.Produce modulation wave signal by digital signal processor (DSP), can on same control system platform, realize easily various control algolithm having increased the flexibility of control system;
3) programmable gate array (FPGA) produces the multichannel triangular carrier signal Ci (i represents the numbering of out of phase power cell not at the same level) of identical amplitude according to certain phase place.Triangular-wave generator is given interruption of DSP at the valley place of each triangular wave, and notice DSP upgrades the data of modulation wave signal Mx.DSP each upgrade the Mx data in, also update mode register.From dual port RAM, read the modulation wave signal data at the peak value place of each triangular wave and get into buffer memory.The real-time triangular carrier with data cached with corresponding of multichannel comparator compares, and produces the SPWM control waveform.
The concrete implementation method of the memory output function among the present invention is as shown in Figure 2, and its concrete implementation method is described below:
1) for realizing the memory output function, in the FPGA internal structure DSP house dog and system mode memory.During the DSP operate as normal, every ms will send a feeding-dog signal to FPGA, this feeding-dog signal of DSP house dog real time monitoring; The system mode memory is preserved the current running status of frequency convertor system, comprising: current system by-path running status, malfunction, running frequency.
2) when DSP is in proper working order; The data of three-phase modulations ripple signal Mx send to the data buffer of programmable gate array (FPGA) by digital signal processor (DSP) generation and through data/address bus; Comparator compares this modulation wave signal and each road triangular carrier signal Ci in real time, produces the PWM control impuls;
3) when DSP operation irregularity (as crash), feeding-dog signal can not normally send, and the DSP house dog surpasses 2ms and do not receive this signal, then thinks the DSP operation irregularity, and notifies sinusoidal wave address generator and reserve failure processor with this abnormality.After sinusoidal wave address generator is received DSP abnormal state signal; From its address register of status register reading frequency information updating; No longer read modulation wave signal Data Update buffer memory from data/address bus; But producing the address according to the data in the Current Address Register, reading of data is sent into buffer memory from dual port RAM, thereby realizes keeping when DSP crashes the output frequency and the phase place of frequency converter.
4) the in-built status register of FPGA has guaranteed that DSP resets and can devote oneself to work again after the success and do not influence the frequency convertor system output waveform.Bypass operation information, fault message and the running frequency of status register storage frequency converter; After DSP resets success; Three groups of information datas in the reading state memory; And carry out algorithm again according to this state and implement, produce three-phase modulations ripple signal Mx, guaranteed that DSP drops into the continuity of back frequency converter output.
Reserve troubleshooting function among the present invention as shown in Figures 2 and 3, in the FPGA internal structure reserve fault processing module, during the DSP operation irregularity, be responsible for frequency convertor system fault and power cell fault are handled.Its concrete implementation method is described below:
When 1) DSP was in proper working order, frequency convertor system fault and power cell fault were responsible for completion by DSP, do not enable the reserve fault management capability, and FPGA receives only system failure word ERR_SYS and power cell fault word ERR_CELL, but does not handle.
2) after the DSP house dog detects the DSP abnormal state, notify the reserve fault processing module with abnormality, DSP abnormal signal ERR_CPU is 1, authorizes the reserve fault processing module that frequency convertor system is protected.The real-time receiving system fault of reserve fault management module word ERR_SYS and power cell fault word ERR_CELL, when detecting the fault generation, fault processing module carries out the corresponding protection action according to predetermined logic to frequency converter failure.
The predetermined troubleshooting logic of reserve fault processing module is: the pulse of system failure envelope is shut down, comprise input output overcurrent, input overvoltage, communication failure, output phase shortage; The power cell fault is carried out by-pass operation and is handled, promptly when a certain power cell fault, and fault processing module receiving element fault word, the failure judgement element number is also controlled through pwm signal and all to be exported 0 level with three power cells of one-level.
3) between the DSP age at failure, fault processing module deposits malfunction and result in the status register in after receiving fault and processing, reads after resetting in order to DSP;
4) after DSP resets success, at first read the status register in the programmable gate array (FPGA), obtain current by-pass operation state, malfunction and output frequency, normal operation input again through data/address bus.
Claims (5)
1. the control system of a cascaded high-voltage frequency converter; Comprise the cascade connection type voltage source inverter; A plurality of power cells are set in the cascade connection type voltage source inverter; It is characterized in that: said each power cell links to each other with field programmable gate array through control optical fiber respectively, and said field programmable gate array links to each other with master cpu;
Said programmable gate array comprises following each functional unit:
CPU Status Monitor: be used to receive the state pulse signal of master cpu, judge the operating state of master cpu to the field programmable gate array timed sending;
Status register: the malfunction, bypass condition and the running frequency information that are used to store frequency converter; Dual port RAM: be used to receive and preserve the three-phase modulations ripple signal data that master cpu sends, supply field programmable gate array to read and compare to produce the PWM control impuls; Master cpu can read the information of the status register in the field programmable gate array through dual port RAM simultaneously;
Sinusoidal wave address generator: the state information that receives running frequency information and master cpu; After receiving CPU abnormal state signal, according to running frequency information generating address, reading of data gets into buffer memory from dual port RAM;
Triangular-wave generator: according to fault message in the status register and bypass information, produce the multichannel triangular carrier signal of out of phase, and input comparator;
Buffer memory: be used for from the dual port RAM reading of data;
Comparator: compare modulation wave signal and triangular carrier signal in the buffer memory, produce the SPWM signal of power controlling cell power switch on and off;
Communication signal converter: receive the control of reserve failure processor, the SPWM conversion of signals that comparator is produced is to be fit to the serial signal that optical fiber sends.
2. the control system of cascaded high-voltage frequency converter according to claim 1, it is characterized in that: said master cpu is a digital signal processor.
3. the control system of cascaded high-voltage frequency converter according to claim 1; It is characterized in that: described cascade connection type voltage source inverter; Adopt the circuit topology of power cell phase shift series connection, said power cell is the voltage source inverter unit of insulated gate bipolar transistor.
4. the control method of cascaded high-voltage frequency converter control system according to claim 1 is characterized in that: may further comprise the steps:
1) digital signal processor sends the three-phase modulations ripple signal data that is used for the control voltage source inverter;
2) the field programmable gate array receiving digital signals processor modulation wave signal data of sending, and compare with the triangular carrier of out of phase and to produce the PWM control impuls;
When digital signal processor is out of service in short-term; Field programmable gate array latchs the modulation wave signal data that receive; Continuation compares triangular carrier and the modulating wave that latchs and produces the PWM control impuls, the continuation stable operation thereby realization inverter inverter when digital signal processor withdraws from short-term maintains the original state;
After digital signal processor resets normally, read the status register of field programmable gate array, continue to produce three-phase modulations ripple signal according to current invertor operation state by digital signal processor, guarantee " seamless switching " of digital signal processor.
5. the control method of cascaded high-voltage frequency converter control system according to claim 4; It is characterized in that: under the digital signal processor normal operating conditions; Troubleshooting is carried out by digital signal processor, field programmable gate array with the fault of converter state storage in status register; When digital signal processor is out of service in short-term, by field programmable gate array fault of converter is handled, thereby guaranteed the security of operation of inverter system when digital signal processor withdraws from short-term.
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| CN102969876B (en) * | 2012-12-01 | 2016-09-28 | 哈尔滨九洲电气股份有限公司 | A kind of core control panel controlling 36 power cells |
| CN103580523B (en) * | 2013-11-19 | 2016-03-23 | 苏州爱科博瑞电源技术有限责任公司 | Based on the multichannel phase-shift PWM ripple generative circuit of FPGA |
| CN105743336B (en) * | 2014-12-10 | 2019-08-02 | 沈阳远大电力电子科技有限公司 | A kind of cascaded high-voltage frequency converter and its master control system |
| CN108233391B (en) * | 2017-12-31 | 2021-05-25 | 长园深瑞继保自动化有限公司 | Cascade SVG serial-parallel cooperative communication controller |
| CN108306485B (en) * | 2018-02-26 | 2019-12-03 | 新风光电子科技股份有限公司 | A kind of generation method of tandem type high voltage transducer power unit pwm signal |
| CN108808629A (en) * | 2018-06-11 | 2018-11-13 | 四川长虹电器股份有限公司 | PWM inverter control module and its control method with defencive function and self recovery |
| CN111145529B (en) * | 2019-12-31 | 2023-10-13 | 深圳库马克科技有限公司 | Communication method of cascade power unit of high-voltage frequency converter |
| CN111145530B (en) * | 2019-12-31 | 2023-10-13 | 深圳库马克科技有限公司 | Communication method of high-voltage frequency converter power unit |
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| CN101714848A (en) * | 2009-12-07 | 2010-05-26 | 浙江大学 | Multiphase induction motor electronic pole-changing transmission device |
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Application publication date: 20101013 Assignee: NANJING SAC NEW ENERGY TECHNOLOGY CO., LTD. Assignor: Nanjing Automation Co., Ltd., China Electronics Corp. Contract record no.: 2014320000462 Denomination of invention: Control system of cascaded high-voltage inverter and method thereof Granted publication date: 20120926 License type: Exclusive License Record date: 20140529 |
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