CN202818224U - Double-ARM processor based control structure for frequency converter - Google Patents
Double-ARM processor based control structure for frequency converter Download PDFInfo
- Publication number
- CN202818224U CN202818224U CN2012204118973U CN201220411897U CN202818224U CN 202818224 U CN202818224 U CN 202818224U CN 2012204118973 U CN2012204118973 U CN 2012204118973U CN 201220411897 U CN201220411897 U CN 201220411897U CN 202818224 U CN202818224 U CN 202818224U
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- frequency converter
- control structure
- apu
- communication processor
- logic communication
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Abstract
Disclosed is a double-ARM processor based control structure for a frequency converter for controlling the operation state of a frequency converter. The control structure comprises a CPU responsible for driving algorithm and a CPU responsible for logic communication, wherein the driving algorithm processor collects and/or utilizes the logic communication processor to collect the operation parameters of each component of the frequency converter and generate control signals, thereby controlling the operation and maintenance of the motor. The control structure of the utility model adopts the double-ARM processor mode to process the frequency converter data in the frequency converter. Besides raising the data processing rate, the control structure reduces the data processing complexity of each processor. In addition, the control structure adopts an ARM-based processor which is simple in structure, thereby the cost is substantially cut down compared to the FPGA. Moreover, the design complexity is decreased.
Description
Technical field
The utility model relates to a kind of control structure of frequency converter, particularly relates to a kind of control structure of the frequency converter based on two arm processors.
Background technology
At present in the frequency converter field, the main control part of most of producer adopts single CPU(processor more) scheme, DSP(Digital Signal Processing that adopt TI companies (Texas Instruments) wherein) more or ST company (ST Microelectronics) based on ARM(Advanced RISC Machines, advanced reduced instruction set computer machine) processor chips, along with the complexity to the Frequency Converter Control algorithm, the requirement of feedback speed and arithmetic speed improves constantly, demand to the complexity of computing and calculation resources and speed is also more and more higher, many producers adopt the ARM chips to add the FPGA(field programmable gate array) or dsp chip to add the fpga chip scheme in the majority, this scheme can increase the cost of fpga chip and peripheral circuit undoubtedly, thereby causes cost to increase.
The utility model content
The technical problems to be solved in the utility model is in order to overcome the high defective of available technology adopting master control unit structural load and cost, a kind of control structure of the frequency converter based on two arm processors is provided, by adopting the mode of dual processor, when improving data processing speed, also reduced a complexity that each processor its data is processed, so reduced cost, and also simplified the complexity of design.
The utility model solves above-mentioned technical problem by following technical proposals:
The utility model provides a kind of control structure of the frequency converter based on two arm processors, is used for the running status of control one frequency converter, is characterized in, described control structure adopts two arm processors jointly to finish the operation of frequency converter all functions.
Wherein said pair of arm processor can be divided into by major function and drive APU and logic Communication processor; Drive the APU collection and/or gather by described logic Communication processor described frequency converter all parts operational factor and generate control signal, the operational factor of described logic Communication processor collection motor and collection peripheral interface parameter and process information are to make logical process and to send to the driving APU, and wherein said driving APU and described logic Communication processor are the processor of ARM kernel.
Wherein said frequency converter is frequency converter commonly used in the prior art, so the kind of the operational factor of described frequency converter and control signal etc. are parameter or signal habitual in the frequency converter, therefore gives unnecessary details no longer in detail herein.
Preferably, described driving APU and logic Communication processor are STM32F103XC, the STM32F103XD of STMicw Electronics or STM32F103XE etc.
Preferably, the collection of described driving APU and/or gather electric current, temperature, busbar voltage, the IGBT(insulated gate bipolar transistor of described frequency converter by described logic Communication processor) overcurrent, IGBT short circuit, power, fan operating state, relay status, brake status and motor encoder signal.
Wherein said parameters is the state parameter that produces in all parts course of work in the existing frequency converter, so the character of parameters is given unnecessary details no longer in detail herein.
Preferably, described logic Communication processor is by RS485(proposed standard 485), CAN(Controller Area Network, controller local area network) bus or SPI(Serial Peripheral Interface (SPI)) be electrically connected with external equipment.
Realize the communication of logic Communication processor and peripheral hardware in the utility model by various communication modes.
Preferably, carry out data interaction by a USART mouth (universal synchronous/asynchronous serial reception/transmitter) between described driving APU and the logic Communication processor.
Preferably, the control structure of described frequency converter also comprises a 8MHz crystal oscillator, and described crystal oscillator is as the common work clock signal source of described driving APU and logic Communication processor.
Preferably, the control structure of described frequency converter also comprises a buffer, is used for the parameter that the described driving APU of buffer memory and described driving APU are controlled described frequency converter and motor operation.
Wherein buffer described in the utility model is used for temporarily storing the collection of described driving APU and/or described driving APU gather all parts of described frequency converter by described logic Communication processor operational factor, after this, described driving APU can read described operational factor from described buffer, and carries out correspondingly subsequent treatment.
Preferably, described buffer is the EEPROM(EEPROM (Electrically Erasable Programmable Read Only Memo)).Even so data are not lost yet after the power down of buffer described in the utility model.Thereby avoid instant power-down on the impact of the data of buffer memory.
Preferably, the control structure of described frequency converter also comprises a under-voltage reset unit, be used for when the supply voltage that electric energy is provided for described driving APU and described logic Communication processor is under-voltage, sending reseting controling signal to described driving APU and described logic Communication processor.
Wherein reseting controling signal described in the utility model is used for described driving APU and described logic Communication processor are carried out initialization, thereby so that described driving APU and described logic Communication processor return to initial running status again.So described reseting controling signal of the present utility model can be the initialization control signal of described driving APU and described logic Communication processor.
Preferably, the control structure of described frequency converter also comprises a real-time clock module, is used for providing the time data of frequency converter operation, what time appears at several a few minutess at quarter such as: the fault of frequency converter, and can power to CPU by the storage battery of self.
Real-time clock module described in the utility model is used for the operational factor of the random time point of record frequency converter running, thereby is convenient to troubleshooting and the debugging of follow-up frequency converter.
Preferably, described logic Communication processor is electrically connected by the expansion board of a SPI interface with the outside.
Wherein said outside expansion board is the expansion board of commonly using in the frequency converter in the prior art, emphasizes mainly in the utility model that each processor carries out transfer of data by SPI interface and expansion board, so no longer described expansion board is given unnecessary details herein.
Preferably, described driving APU and described logic Communication processor also are electrically connected with an external burning interface.
Wherein the utility model is by described external burning interface, and by the mode of sheet choosing described driving APU and described logic Communication processor carried out the burning operation.
Positive progressive effect of the present utility model is:
The control structure of the frequency converter based on two arm processors of the present utility model by adopting the mode of dual processor, when improving data processing speed, has also reduced the complexity that each processor its data is processed.
And adopt processor based on ARM in the utility model, and and because the processor self of ARM simple in structure, thus cost reduced significantly with respect to FPGA scheme etc., and simplified the complexity of design.
Description of drawings
Fig. 1 is the structural representation of preferred embodiment of the control structure of the frequency converter based on two arm processors of the present utility model.
Embodiment
Provide the better utility model of the utility model below in conjunction with accompanying drawing, to describe the technical solution of the utility model in detail.
32 8-digit microcontroller chip STM32F103 series of products of two ARM kernels have been selected based on function and cost consideration present embodiment, wherein a chip is as the CPU1(CPU) be responsible for driving and the algorithm of frequency converter, another chip is responsible for logic and the communication of peripheral interface as CPU2, thereby CPU1 can carry out complicated control algolithm computing, because the reduction of CPU1 Processing tasks, the electric current loop of Electric Machine Control and the response time of speed ring shorten greatly; CPU2 receives the digital quantity analog quantity of peripheral interface and the data of industry spot simultaneously, processes, and the rear portion that is disposed is issued the closed loop response control that CPU1 carries out motor again, and another part is controlled peripheral controller.The clarification in certain roles of two CPU tasks can effectively utilize the resource of chip, solves the task that single CPU can not finish.
So comprise in the control structure based on the frequency converter of two arm processors of present embodiment as shown in Figure 1: one drives APU 1, a logic Communication processor 2, a crystal oscillator 3, a buffer 4, a under-voltage reset unit 5 and a real-time clock module 6.
Wherein drive the operational factor that APU 1 and described logic Communication processor 2 all gather all parts of described frequency converter described in the present embodiment, wherein said logic Communication processor 2 also is sent to described driving APU 1 with the operational factor that gathers.
Described driving APU 1 generates control signal based on all operational factors, thereby controls the running status of frequency converter by described control signal.Wherein said logic Communication processor 2 is controlled the operation of described frequency converter based on described control signal.
And frequency converter described in the present embodiment is frequency converter commonly used in the prior art, so the operational factor of described frequency converter and the kind of control signal etc. are parameter or signal habitual in the frequency converter, so the operational factor of frequency converter described in the present embodiment comprises electric current, temperature, busbar voltage, IGBT overcurrent, IGBT short circuit, power, fan operating state, relay status, brake status and the motor encoder signal etc. of described frequency converter.Described control signal for a change or keep the command signal of operating state of the parts of frequency converter described above namely.
In addition because the critical index signal of the frequency converter work such as electric current, voltage and temperature of frequency converter, thus when driving operational factor that APU 1 and described logic Communication processor 2 all gather all parts of described frequency converter described in the present embodiment and can prevent that single processor from gathering above-mentioned signal because the misoperation that the time-delay of signal causes in the transmission communication.
Such as: drive APU 1 described in the present embodiment and mainly gather: export 6 road PWM(pulse-width modulations) signal, current sample and to electric current process, temperature detection, busbar voltage detections, IGBT short-circuit protection, IGBT overcurrent protection, power identification, braking detection, fans drive, fan detection, relay driving and motor encoder signals collecting etc.
The Communication processor of logic described in the present embodiment 2 mainly gathers: the driving of the input and output of digital quantity, the input and output of analog quantity, relay, expansion board identification, busbar voltage detection, temperature detection and current detecting etc.
And the Communication processor 2 of logic described in the present embodiment is sent to described frequency converter by SPI with described control signal, and described logic Communication processor 2 can also by other communication modes, come transmission of control signals such as RS485 or CAN bus etc. in addition.
In addition described logic Communication processor 2 and drive the collection of operational factor that APU 1 also can realize by above-mentioned communication modes all parts of frequency converter.
In addition because logic Communication processor 2 and drive the transmission that also needs signal between the APU 1, thus connect by USART between described driving APU 1 and the logic Communication processor 2, thus realize the mutual transmission of operational factor and control signal.
And as mentioned above, described driving APU 1 and the logic Communication processor 2 of present embodiment all adopt arm processor, for example the processor of the STM32F103 series of STMicw Electronics.Thereby has lower cost with respect to dsp chip and fpga chip.Wherein said driving APU 1 and logic Communication processor 2 preferably adopt the processor of STM32F103XC, STM32F103XD or STM32F103XE.
Crystal oscillator described in the present embodiment 3 provides 8MHz work clock signal for described driving APU 1 and logic Communication processor 2, thereby so that the work schedule of described driving APU 1 and logic Communication processor 2 is synchronous.
Described buffer 4 is for the operational factor of all parts of the described frequency converter of the described driving APU 1 of buffer memory and 2 collections of described logic Communication processor.Thereby realize the temporary transient storage to described operational factor, after this, described driving APU 1 can read described operational factor from described buffer 4, and carries out correspondingly subsequent treatment.
Wherein buffer described in the present embodiment 4 is EEPROM, thereby even so that after the described buffer power down data do not lose yet.Thereby avoid instant power-down on the impact of the data of buffer memory.
The under-voltage reset unit 5 of present embodiment is used for sending reseting controling signals to described driving APU 1 and described logic Communication processor 2 when the under-voltage of the power supply that electric energy is provided for described driving APU 1 and described logic Communication processor 2.Because driving APU 1 and described logic Communication processor 2 are the processor of the STM32F103 series of STMicw Electronics in the present embodiment, so the reseting controling signal of described processor self is determined.For example: supply power voltage normally is 3.3V, when voltage is lower than 2.6V, simultaneously two chips are sent reseting controling signal, and utilize the described reseting controling signal of described processor self that described driving APU and described logic Communication processor are carried out initialization, thereby so that described driving APU and described logic Communication processor recover initial running status again.
Described real-time clock module 6 is used for the time data of record frequency converter operation.Wherein real-time clock module described in the present embodiment 6 is used for intactly recording the operational factor of the random time point of described frequency converter running, so be different from the data cached function of above-mentioned buffer 4, the operational factor of described real-time clock module 6 records is used for the troubleshooting of follow-up frequency converter and debugging etc.Wherein real-time clock module described in the present embodiment 6 directly records the time parameter of the operation of the common all parts that gathers frequency converters of described driving APU 1 and logic Communication processor 2.
Thereby present embodiment improves arithmetic speed and operation efficiency by distribute different functions to reduce the complexity of the computing on the single ARM chip in realization complex calculation function at two ARM chips.
The specific works flow process of present embodiment is as follows:
Before the frequency converter operation, enter to control the algorithm that frequency converter moves to driving APU 1 programming respectively by the sheet choosing, drive, the protection supervisor is to the program of 2 programmings of logic Communication processor such as control logic and communication etc.
Wherein drive between APU 1 and the logic Communication processor 2 described in the present embodiment and carry out communication and transfer of data by serial ports, two chips are selected different chips by the sheet choosing equally, increase simultaneously three anti-programming error detection bits, burn wrong program to prevent two chips.
Crystal oscillator ceaselessly provides clock signal all the time in described driving APU 1 and logic Communication processor 2 courses of work simultaneously.To change first the operational factor of frequency converter in the buffer 4 when powering on, to adapt to different frequency converter running statuses.In frequency converter when operation,, described driving APU 1 can according to the signal of the parameter in frequency converter running status, the buffer 4, drive plate feedback with from the data of the various communications of logic Communication processor 2, be carried out the dynamic response that frequency converter is controlled in computing.
Simultaneously; logic Communication processor 2 can constantly receive from each interface in the frequency converter running; field control integrated circuit board and the transducer operational parameter that calls in the buffer 4; and after carrying out logical process; feed back to the field integrated circuit board or equipment; data can be transferred to described driving APU 1 after will processing simultaneously; so common cooperation guarantees the coordinated operation of frequency converter; when excess temperature occurring; overvoltage; overcurrent; described driving APU 1 and logic Communication processor 2 can be accepted fault-signal simultaneously during the faults such as short circuit; make corresponding processing; such as stopping pwm signal, stop the safeguard measures such as output current.Real-time clock module 6 can also be preserved the state recording of operation in order to call later on and debug.
Although more than described embodiment of the present utility model, it will be understood by those of skill in the art that these only illustrate, protection range of the present utility model is limited by appended claims.Those skilled in the art can make various changes or modifications to these execution modes under the prerequisite that does not deviate from principle of the present utility model and essence, but these changes and modification all fall into protection range of the present utility model.
Claims (12)
1. control structure based on the frequency converter of two arm processors is used for the running status of control one frequency converter, it is characterized in that described control structure comprises: one first arm processor and one second arm processor;
Wherein said the first arm processor is as driving APU, and described the second arm processor is as the logic Communication processor;
The collection of described driving APU and/or gather by described logic Communication processor described frequency converter all parts operational factor and generate control signal, described logic Communication processor gathers the operational factor of frequency converter and motor and gathers frequency converter peripheral interface parameter and process and sends to the driving APU.
2. the control structure of frequency converter as claimed in claim 1 is characterized in that, described driving APU and logic Communication processor are STM32F103XC, STM32F103XD or the STM32F103XE of STMicw Electronics.
3. the control structure of frequency converter as claimed in claim 1 is characterized in that, described control structure comprises that also a real-time clock module is used for the time data of record frequency converter operation.
4. the control structure of frequency converter as claimed in claim 1, it is characterized in that described driving APU collection and/or gather electric current, temperature, busbar voltage, IGBT overcurrent, IGBT short circuit, power, fan operating state, relay status, brake status and the motor encoder signal of described frequency converter by described logic Communication processor.
5. the control structure of frequency converter as claimed in claim 1 is characterized in that, described logic Communication processor is electrically connected with external equipment by RS485, CAN bus or SPI.
6. the control structure of frequency converter as claimed in claim 1 is characterized in that, carries out data interaction by a USART mouth between described driving APU and the logic Communication processor.
7. the control structure of frequency converter as claimed in claim 1 is characterized in that, the control structure of described frequency converter also comprises a 8MHz crystal oscillator, and described crystal oscillator provides clock signal for described driving APU and logic Communication processor.
8. the control structure of frequency converter as claimed in claim 1, it is characterized in that, the control structure of described frequency converter also comprises a buffer, is used for the parameter that the described driving APU of buffer memory and described driving APU are controlled described frequency converter and motor operation.
9. the control structure of frequency converter as claimed in claim 8 is characterized in that, described buffer is EEPROM.
10. the control structure of frequency converter as claimed in claim 1, it is characterized in that the control structure of described frequency converter is used for sending to described driving APU and described logic Communication processor a under-voltage reset unit of reseting controling signal when also being included in and providing the under-voltage of a power supply of electric energy for described driving APU and described logic Communication processor.
11. the control structure of frequency converter as claimed in claim 1 is characterized in that, described logic Communication processor is electrically connected by the expansion board of a SPI interface with the outside.
12. the control structure of frequency converter as claimed in claim 1 is characterized in that, described driving APU and described logic Communication processor also are electrically connected with an external burning interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012204118973U CN202818224U (en) | 2012-08-17 | 2012-08-17 | Double-ARM processor based control structure for frequency converter |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2012204118973U CN202818224U (en) | 2012-08-17 | 2012-08-17 | Double-ARM processor based control structure for frequency converter |
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| CN202818224U true CN202818224U (en) | 2013-03-20 |
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| CN2012204118973U Expired - Lifetime CN202818224U (en) | 2012-08-17 | 2012-08-17 | Double-ARM processor based control structure for frequency converter |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103791920A (en) * | 2014-03-05 | 2014-05-14 | 新杰克缝纫机股份有限公司 | Sensor interface expansion board |
| CN104167974A (en) * | 2014-08-28 | 2014-11-26 | 辽宁荣信电气传动技术有限责任公司 | Encoder signal acquisition topological structure based on high-voltage inverters |
| CN106612064A (en) * | 2015-10-20 | 2017-05-03 | 中车大连电力牵引研发中心有限公司 | Converter control circuit, converter and data interaction method |
| CN108052065A (en) * | 2017-12-27 | 2018-05-18 | 哈尔滨广瀚燃气轮机有限公司 | A kind of distributed multi-processor gas turbine monitoring device |
| CN109754676A (en) * | 2018-12-17 | 2019-05-14 | 浙江理工大学 | A kind of roller Braille reading pen for the identification of papery books for the blind |
| CN113110124A (en) * | 2021-03-11 | 2021-07-13 | 上海新时达电气股份有限公司 | double-MCU control method and control system |
-
2012
- 2012-08-17 CN CN2012204118973U patent/CN202818224U/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103791920A (en) * | 2014-03-05 | 2014-05-14 | 新杰克缝纫机股份有限公司 | Sensor interface expansion board |
| CN104167974A (en) * | 2014-08-28 | 2014-11-26 | 辽宁荣信电气传动技术有限责任公司 | Encoder signal acquisition topological structure based on high-voltage inverters |
| CN106612064A (en) * | 2015-10-20 | 2017-05-03 | 中车大连电力牵引研发中心有限公司 | Converter control circuit, converter and data interaction method |
| CN108052065A (en) * | 2017-12-27 | 2018-05-18 | 哈尔滨广瀚燃气轮机有限公司 | A kind of distributed multi-processor gas turbine monitoring device |
| CN109754676A (en) * | 2018-12-17 | 2019-05-14 | 浙江理工大学 | A kind of roller Braille reading pen for the identification of papery books for the blind |
| CN113110124A (en) * | 2021-03-11 | 2021-07-13 | 上海新时达电气股份有限公司 | double-MCU control method and control system |
| CN113110124B (en) * | 2021-03-11 | 2022-08-19 | 上海新时达电气股份有限公司 | double-MCU control method and control system |
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Granted publication date: 20130320 |
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