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A method of controlling the core board 36 of the power unit

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Publication number
CN102969876B
CN102969876B CN 201210506064 CN201210506064A CN102969876B CN 102969876 B CN102969876 B CN 102969876B CN 201210506064 CN201210506064 CN 201210506064 CN 201210506064 A CN201210506064 A CN 201210506064A CN 102969876 B CN102969876 B CN 102969876B
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CN 201210506064
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CN102969876A (en )
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孙敬华
陈晨
何建华
王瑞舰
肖心凯
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哈尔滨九洲电气股份有限公司
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Abstract

本发明设计的是一种变流器的核心控制板方案,可控制不大于由36个H桥功率单元构成的级联型变流器,主要用于级联静止型无功发生器、级联型高压变频器、级联型同相供电电源变流器等。 The core design of the present invention is a control board scheme converter can be controlled not more than cascaded converter 36 by the H-bridge power units, mainly for cascading Static Var Generator, a cascade high voltage frequency, cascaded with the same power supply converter and the like. 本发明方案主要包括:用于产生36个H桥功率单元控制脉冲信号和接收功率单元状态信号的FPGA芯片,用于核心控制算法的DSP芯片,用于同外界连接的开关量输入、输出及通讯联络的CPLD芯片,用于接收模拟信号的运算放大器A1~A18,用于为各个芯片供电的电源芯片IC1~IC4,用于检测本电路环境温度湿度的芯片IC5,用于保存参数的芯片EEPROM等。 Embodiment of the present invention mainly comprises: generating FPGA chip 36 for H-bridge power control unit and a pulse signal received power status signal unit for controlling the DSP chip core algorithm for connecting with the outside of the switch input, output, and communication liaison CPLD chip, for receiving the analog signal of the operational amplifier A1 ~ A18, a power supply for each chip chip IC1 ~ IC4, the present circuit for detecting ambient temperature and humidity chip IC5, a parameter stored in EEPROM chip or the like . 本电路运行稳定、使用范围广泛。 This circuit is stable, using a wide range.

Description

一种控制36个功率单元的核心控制板 A method of controlling the core board 36 of the power unit

技术领域 FIELD

[0001]本发明设计的是一种变流器的核心控制板方案,具体设计的是一种可以控制不大于36个功率单元所构成的变流器的核心控制板。 [0001] The present invention is a core board design scheme converter, a particular design is not greater than the core board can be controlled converter power unit 36 ​​constituted.

背景技术 Background technique

[0002]级联型变流器在不大于35kV高压系统中得到了广泛的应用,如级联型静止无功发生器SVG,级联型高压变频器,级联型同相供电电源变流器等。 [0002] Cascaded converter not greater than 35kV high pressure system has been widely used as power supply phase Cascade STATCOM the SVG, cascaded high voltage frequency, cascaded with like power converters . 但是,目前控制这类变流器的核心控制电路方案存在以下缺点: However, the core of such a control current converter circuit control scheme has the following disadvantages:

[0003] 1、一般由多个板卡构成的插卡式结构,接插件多,结构复杂,可靠性较低; [0003] 1, a general card structure consisting of a plurality of boards, connectors and more complex structure, low reliability;

[0004] 2、一般采用总线式电路结构,板卡与板卡之间线路较长,总线之间不仅易受到串扰,也容易受外界扰动; [0004] 2, the general circuit configuration of the bus type, between the board and long board line, susceptible to crosstalk between the bus only, is also vulnerable to external disturbances;

[0005] 3、板卡与板卡相邻,板卡与板卡元之间易产生的相互干扰; [0005] 3, adjacent to the board and the board, between the board and the board is easy to produce mutual interference element;

[0006] 4、板卡封闭在机箱内,散热性能较差; [0006] 4, enclosed within a chassis board, heat dissipation is poor;

[0007] 5、对板卡上的信号难于检测和测量,必需制做和使用专门设计的辅助部件进行测量,给生产检测增加了难度; [0007] 5, the signal on the board difficult to detect and measure, and making necessary the use of specially designed auxiliary member was measured, to the production and testing more difficult;

[0008] 6、板卡式控制电路,一般只能针对某一个具体的级联型变流器,如:要么是针对级联型静止无功发生器SVG的控制电路,要么是针对级联型高压变频器的控制电路,要么是针对级联型同相供电电源变流器的控制电路,而不能通用于上述各个类型变流器。 [0008] 6, control circuit board, generally only for a certain type of a particular converter cascade, such as: either the control circuit for the cascaded STATCOM SVG, either for cascaded high-voltage inverter control circuit, a control circuit for either cascade-phase power supply converter, and not common to the respective type of converter.

发明内容 SUMMARY

[0009]本发明设计的是一种变流器的核心控制电路,这种电路可控制不大于由36个H桥功率单元构成的级联型变流器。 [0009] The design of the present invention is a variation of the core of the current control circuit, which can control the cascade is not greater than 36 by the inverter H-bridge power units. 此类级联型变流器主要可广泛应用于级联静止型无功发生器、级联型高压变频器、级联型同相供电电源变流器等设备上。 Such cascaded converters can be widely used mainly cascades Static Var Generator, a cascade-type high voltage inverter, with the cascade phase power supply converter and other equipment.

[0010]本发明是这样实现的:一种控制36个功率单元的核心控制板,主要是由通用的现场可编程门阵列FPGA芯片、3片通用数字信号处理DSP芯片,其中I片用于核心控制算法的DSPl,其外部存储器RAMl;可选的用于辅助计算的DSP2,其外部存储器RAM2;用于本电路与外界协调控制的DSP3,其外部存储器RAM3、通用复杂可编程逻辑器件CPLD芯片、通用运算放大器Al〜A18、通用的电源芯片ICl〜IC4、通用的检测温度湿度芯片IC5、用于保存参数的通用芯片EEPROM、脉冲宽度调制PWM口、输入输出1口组成的,其特征是:在器件布局上若以P丽口为上方,那么P丽口的下方是FPGA,FPGA的下方是DSPI,DSPI的下方是DSP3,DSP3的下方是1口,DSP1的右方是DSP2,DSP2的上方是RAM2,DSP1的左上方是RAM1,DSP3的左方是CPLD,CPLD的上方是RAM3,DSP3的背部是EEPR0M,FPGA的左方是IC1、IC2、IC3、IC4,RAM1和RAM3之间的左侧是IC5 [0010] The present invention is implemented as follows: the core board 36 for controlling power units, mainly by general Field Programmable Gate Array FPGA chip, three general purpose digital signal processing DSP chip, which I used for core sheet DSPl control algorithm, which is an external memory Raml; optionally an auxiliary calculation DSP2, external memory RAM2; DSP3 present coordinated control circuit and the outside, which is an external memory RAM 3, a complex programmable logic device CPLD common chip, operational Amplifiers Al~A18, universal power chip ICl~IC4, generic chip IC5 detected temperature and humidity, common chip EEPROM for storing parameters, a pulse width modulation (PWM) port, an input-output component, wherein: the in terms of device layout on upward port P Li, P Li then the port is below the FPGA, the FPGA is DSPI below, it is below the DSPI DSP3, DSP3 is below 1, the upper right DSP1 DSP2, DSP2 is RAM2, upper left DSP1 is RAM1, DSP3 is CPLD the left, above the CPLD is RAM3, back DSP3 is EEPR0M, FPGA is left IC1, left between IC2, IC3, IC4, RAM1 and RAM3 are IC5 DSP2的下方是运算放大器Al〜A18,10 口在最下方;在电路原理上PWM口与FPGA电信号连接,RAMl与DSPl电信号连接,RAM2与DSP2电信号连接,RAMl、DSP1、RAM2、DSP2分别与FPGA电信号连接,RAM3与DSP3电信号连接,DSP3分别与DSPI和DSP2电信号连接,0?0)分别与03?1、03?2、03?3、1^13、10口电信号连接,通用运算放大器41〜八18分别与DSP1、DSP2、DSP3、10口电信号连接,通用电源芯片ICl〜IC4与1口电信号连接,并为各器件提供不同电压的电源,通用芯片IC5与DSP3、EEPR0M、10口电信号连接。 DSP2 is below the lower port of the operational amplifier Al~A18,10 at most; and the mouth of the PWM electrical signal connecting FPGA, RAMl electrical connection with DSPl, RAM2 DSP2 connected in electrical circuit theory, RAMl, DSP1, RAM2, DSP2 respectively FPGA and electrical connections, RAM3 connected DSP3 electrical signal, DSP3 are connected to the electrical DSPI and DSP2, 0? 0), respectively, and 03? 1,03? 2,03? 3,1 ^ 13, 10 port electrical connector , eight 41~ 18, DSP2, DSP3,10 port electrical connector, the universal power chip ICl~IC4 an electrical connection to a general operational amplifier DSP1 respectively, and provide a different power supply voltages for the device, and the universal chip IC5 DSP3 , EEPR0M, 10 port electrical connector.

[0011 ]本发明还具有以下技术特征: [0011] The present invention has the following technical features:

[0012] 1、所述的FPGA采用的芯片是EP3C16240C8N型。 [0012] 1, the FPGA chip uses EP3C16240C8N type.

[0013] 2、所述的DSP1、DSP2、DSP3采用TI公司的TMS320x28x系列器件。 [0013] 2, according to DSP1, DSP2, DSP3 TMS320x28x TI's family of devices.

[0014] 3、所述的CPLD采用的芯片是EPM1270T144C5型。 [0014] 3, the chip uses a CPLD EPM1270T144C5 type.

[0015]本电路运行稳定、使用范围广泛。 [0015] This circuit is stable, using a wide range.

附图说明 BRIEF DESCRIPTION

[0016]图1是本发明的元器件布局排列图 [0016] FIG. 1 is a layout of components of the present invention, the arrangement of FIG.

[0017]图2是本发明的电气原理方框图 [0017] FIG. 2 is a block electrical schematic of the present invention

具体实施方式 detailed description

[0018]下面结合附图和具体实施例对本发明作进一步的详细说明: Drawings and specific embodiments of the present invention will be further described in detail [0018] below with:

[0019]如图1所示,一种控制36个功率单元的核心控制板,主要是由用于产生36个H桥功率单元控制脉冲信号和接收功率单元状态信号的通用现场可编程门阵列FPGA芯片、3片通用数字信号处理DSP芯片,其中I片用于核心控制算法的DSPl,其外部存储器RAMl;可选的用于辅助计算的DSP2,其外部存储器RAM2;用于本电路与外界协调控制的DSP3,其外部存储器RAM3、用于连接本电路与外界之间的开关量输入、输出及通讯联络的通用复杂可编程逻辑器件CPLD芯片、用于接收模拟信号的通用运算放大器Al〜A18、用于为各个芯片供电的通用电源芯片ICl〜IC4、用于检测本电路环境温度湿度的通用芯片IC5、用于保存参数的芯片EEPROM等组成的。 [0019] 1, the core board 36 for controlling power units, mostly due to common site 36 H-bridge power control unit and a pulse signal received power unit status signal by a programmable gate array FPGA for chip, three general purpose digital signal processing DSP chip, in which the I-slice DSPl core control algorithm for which the external memory Raml; optional calculation for assisting DSP2, RAM 2 external memory; and present outside coordinated control circuit General operational amplifier DSP3, external memory RAM 3, for connection between this circuit and external digital input, output and communications general complex programmable logic device CPLD chip, for receiving the analog signal Al~A18, with to a universal power supply chip ICl~IC4 individual chips, a circuit for detecting ambient temperature and humidity of this common chip IC5, a parameter stored in EEPROM chip or the like thereof.

[0020] 1、电源实现方式 [0020] 1, implementation of power

[0021] 如图2所示,本发明通用电源芯片ICl〜IC4通过其1 口向内部提供+5V数字电源以及土5V模拟电源,+5V数字电源经IC1、IC2、IC3、IC4构成电源电路稳压输出1.2V、1.9V、 [0021] As shown, the universal power chip ICl~IC4 the present invention provides, through its interior to a 2 + 5V power supply and digital soil 5V analog, + 5V power supply via the digital IC1, IC2, IC3, IC4 constitute a stable power supply circuit output voltage 1.2V, 1.9V,

2.5V、3.3V电压,为FPGA、DSP1〜DSP3、CPLD、RAM1〜RAM3等电路提供电源,土5V模拟电源直接送给运算放大器Al〜A18。 2.5V, 3.3V voltage to provide power to the FPGA, DSP1~DSP3, CPLD, RAM1~RAM3 other circuit, directly to the soil 5V analog operational amplifier Al~A18.

[0022] 2、10 口信号 [0022] 2,10 port signal

[0023]如图2所示,本发明的1口信号主要包括:I路转速编码器信号EN⑶DER,有3根信号、16路开关量输入信号1[16]、10路开关量输出信号0[ 10]、2路异步串行信号SC1-1,有收、发各I根信号和SC1-2,有收、发各I根信号、I路CANbus总线,有收、发各I根信号,以上信号均连接至CPLD且可重新再定义;还有I路I2C总线,有时钟、数据各I根信号,直接连至DSP3、EEPROM和IC5,18路模拟量输入信号Ain[18]连至运算放大器Al〜A18。 [0023] 2, a main signal according to the present invention comprising: I road speed encoder signal EN⑶DER, there are three signals, digital input signals 16 1 [16], 10-way switching outputs 0 [ 10], 2-way asynchronous serial signals SC1-1 with sending and receiving of signal and each I SC1-2, there is the sending and receiving of signal for each I, I road CANbus bus with sending and receiving of signal for each I, above signals are coupled to the CPLD and may be re-defined; and the I I2C bus with a clock, data of each of signal I, is directly connected to the DSP3, EEPROM, and IC5,18 analog input signal Ain [18] connected to an operational amplifier Al~A18.

[0024] 3、PWM 口信号 [0024] 3, PWM signal port

[0025]如图2所示,本发明的P丽口信号主要有:36路发送信号TX[36],36路接收信号RX [0025] 2, P Li port signal present invention are: 36-way transmission signal TX [36], 36 channel reception signal RX

[36],均连至FPGA芯片。 [36], are connected to the FPGA chip.

[0026] 4、CPLD与DSPl相连的信号 [0026] 4, the signal connected to the CPLD DSPl

[0027] 如图2所示,本发明的CPLD与DSPl相连的信号主要有:I路CANbus总线ICANbus信号,有收、发各I根信号、I路编码器捕获信号1EQEP,有3根信号,I路异步串行信号ISCI,有收、发各I根信号。 [0027] 2, the signal is connected to the CPLD DSPl the present invention are mainly: I CANbus. ICANbus signal path, there is the sending and receiving of signal for each I, I-encoder signal capture 1EQEP, there are three signals, the ISCI asynchronous serial signal path I, there is the sending and receiving of signal for each I.

[0028] 5、CPLD与DSP2相连的信号 [0028] 5, CPLD and DSP2 connected to the signal

[0029] 如图2所示,本发明的CPLD与DSP2相连的信号主要有:1路CANbus总线2CANbus信号,有收、发各I根信号、I路异步串行信号2SCI,有收、发各I根信号。 [0029] 2, the CPLD and DSP2 connected to a signal of the present invention are: 1 CANbus. 2CANbus signal path, there is the sending and receiving of signal for each I, I channel asynchronous serial signal 2SCI, there are sending and receiving the respective I signal root.

[0030] 6、CPLD与DSP3相连的信号 [0030] 6, the signal connected to the CPLD DSP3

[0031] 如图2所示,本发明的CPLD与DSP3相连的信号主要有:2路CANbus总线3CANbus信号,有收、发各I根信号和4CANbus信号有收、发各I根信号、2路异步串行信号3SCI,有收、发各I根信号和4SCI,有收、发各I根信号、16根数据总线3Data[15:0]、19根地址总线3Addr[18:0]、4根控制总线3(:廿1[4]。30&七&[15:0]、34(1办[18:0]和3(:廿1[4]也连接至存储器RAM3o [0031] 2, the signal is connected to the CPLD DSP3 the present invention are: 2-way CANbus. 3CANbus signal with the sending and receiving of signal and the respective I have 4CANbus signal sending and receiving of signal for each I, 2 asynchronous serial signal 3SCI, there is the sending and receiving of signal and the respective I 4SCI, there are sending and receiving the respective plurality of signal I, data bus 16 3Data [15: 0], 19 root address bus 3Addr [18: 0], 4 root control bus 3 (: Twenty 1 [4] & .30 & seven [15: 0], 34 (1 do [18: 0] and 3 (: Twenty 1 [4] is also connected to the memory RAM3o

[0032] 7、FPGA与DSPl相连的信号 [0032] 7, FPGA and connected to a signal DSPl

[0033] 如图2所示,本发明的FPGA与DSPl相连的信号主要有:6根P丽信号1PWM[6]、I根故障捕获信号1了2、16根数据总线10&丨&[15:0]、8根地址总线14(1办[7:0]、4根控制总线1(:壮1[4]。10&七3[15:0]、^(1(^[7:0]和1(:壮1[4]也连接至存储器1^11。 [0033] 2, the signal is connected to the FPGA DSPl invention are: 6 Li signal P 1PWM [6], I 1 the root fault signal captured data bus root 2,16 & 10 & Shu [15: 0], 8 address bus 14 (1 do [7: 0], four control bus 1 (: strong 1 [4] .10 & seven 3 [15: 0], ^ (1 (^ [7: 0] and 1 (: 1 Zhuang [4] ^ 1 is also connected to a memory 11.

[0034] 8、? [0034] 8 ,? ?6六与03?2相连的信号 ? 6 six signal with 03? 2 connected

[0035] 如图2所示,本发明的FPGA与DSP2相连的信号主要有:6根P丽信号2PWM[6]、1根故障捕获信号2了2、16根数据总线20&丨&[15:0]、8根地址总线24(1办[7:0]、4根控制总线2(:壮1[4 ]。2Data [ 15:0 ]、2Addr [ 7:0 ]和2Ctr I [ 4 ]也连接至存储器RAM2。 [0035] 2, the FPGA signal DSP2 connected with the present invention are: 6 Li signal P 2PWM [6], 1 2 the root fault signal captured data bus root 2,16 & 20 & Shu [15: 0], address bus 24 8 (1 do [7: 0], the control bus 4 2 (: strong 1 [4] .2Data [15: 0], 2Addr [7: 0] and 2Ctr I [4] also connected to the memory RAM2.

[0036] 9、DSP1与DSP2、DSP3之间通讯方式 [0036] 9, communication between DSP1 and DSP2, DSP3

[0037] 如图2所示,本发明的DSPl与DSP2、DSP3之间通讯方式主要有:同步串行通讯SPI,直接实现DSPl与DSP2、DSP3之间的快速通讯;通过ISC1、2SC1、3SCI信号和CPLD内部处理实现DSPl与DSP2、DSP3之间的异步串行通信SCI通讯;通过lCANbus、2CANbus、3CANbus信号和CPLD内部处理实现DSPl与DSP2、DSP3之间的控制器局域网总线CANbus通讯。 [0037] 2, DSPl the present invention and the DSP2, DSP3 communication between the main: synchronous serial communication SPI, direct communication between the fast and DSPL DSP2, DSP3; signal through ISC1,2SC1,3SCI and internal processing asynchronous serial communication CPLD SCI communication between DSPl and DSP2, DSP3; by lCANbus, 2CANbus, 3CANbus signal processing implementation and internal CPLD controller area network bus CANbus communication between DSPl and DSP2, DSP3. DSPl与DSP2之间亦可以通过10&七3[15:0]、1厶(1(^[7:0]和1(:让1[4]总线及203七3[15:0]、2厶(1(^[7:0]和2Ctrl[4]总线和FPGA内部处理实现DSPl与DSP2之间的并行通讯。 Between DSPl and DSP2 also by 10 & seven 3 [15: 0], a Si (1 (^ [7: 0] and 1 (: Let 1 [4] bus and 203 seven 3 [15: 0], 2 Si (1 (^ [7: 0] and 2Ctrl [4] and the FPGA internal bus for parallel processing and communication between DSPl DSP2.

[0038] 1、DSPI与DSP2、DSP3接收的模拟量信号 [0038] 1, DSPI and DSP2, DSP3 received analog signals

[0039]如图2所示,本发明的DSPl与DSP2、DSP3接收的模拟量信号分别为:16路1AD[16]、16路2AD[16]、16路3AD[16],均连接至运算放大器Al〜A18的输出,Al〜A18的输入连接至1口,可接收本电路外部的模拟量信号。 [0039] 2, DSPl the present invention and the DSP2, DSP3 received analog signals are: 16 1AD [16], 16 way 2AD [16], 16 way 3AD [16], is connected to the op Al~A18 the output of the amplifier, is connected to the input Al~A18 1, this external circuitry may receive analog signals.

Claims (4)

1.一种控制36个功率单元的核心控制板,主要包括:通用的现场可编程门阵列FPGA芯片、3片通用数字信号处理DSP芯片、通用复杂可编程逻辑器件CPLD芯片、通用运算放大器Al〜A18、通用的电源芯片ICl〜IC4、通用的检测温度湿度芯片IC5、用于保存参数的通用芯片EEPROM、脉冲宽度调制PffM口、输入输出1口,3片通用数字信号处理DSP芯片,其中核心控制算法的DSPl,其外部存储器为RAMl;可选的用于辅助计算的DSP2,其外部存储器为RAM2;用于本电路与外界协调控制的DSP3,其外部存储器为RAM3,其特征是:在器件布局上若以PWM口为上方,那么PWM 口的下方是FPGA,FPGA的下方是DSPl,DSPI的下方是DSP3,DSP3的下方是1口,DSP1的右方是DSP2,DSP2的上方是RAM2,DSP1的左上方是RAM1,DSP3的左方是CPLD,CPLD 的上方是RAM3,DSP3 的背部是EEPR0M,FPGA的左方是IC1、IC2、IC3、IC4,RAM1和RAM3之间的左侧是IC5 A central control panel 36 power unit, including: a common field programmable gate array FPGA chip, three general purpose digital signal processing DSP chip, a complex programmable logic device CPLD universal chip, Operational Amplifiers Al~ A18, universal power chip ICl~IC4, generic chip IC5 detected temperature and humidity, common chip EEPROM for storing parameters, a pulse width modulation PffM port, an input and output, three general purpose digital signal processing DSP chip, wherein the core control DSPl algorithm, which is an external memory Raml; optionally an auxiliary calculation DSP2, RAM 2 which is an external memory; DSP3 for coordinated control of the present circuit and the outside world, which is an external memory for the RAM 3, characterized in that: in the device layout in terms of the PWM port is upward, the PWM port is below the FPGA, the FPGA is DSPL below, is below the DSPI DSP3, DSP3 is below 1, the right DSP1 DSP2, RAM 2 is above the DSP2, the DSP1 upper left RAM1, DSP3 is CPLD the left, above the CPLD is RAM3, back DSP3 is EEPR0M, FPGA is left IC1, left between IC2, IC3, IC4, RAM1 and RAM3 are IC5 ,DSP2的下方是运算放大器Al〜A18,1 口在最下方;在电路原理上PWM 口与卩卩6六电信号连接,1^11与05?1电信号连接,1^12与05?2电信号连接,1^11、05?1、1^12、05?2分别与FPGA电信号连接,RAM3与DSP3电信号连接,DSP3分别与DSPl和DSP2电信号连接,CPLD分别与03?1、03?2、03?3、1^13、10口电信号连接,通用运算放大器41〜418分别与03?1、DSP2、DSP3、10口电信号连接,通用电源芯片ICl〜IC4与1口电信号连接,并为各器件提供不同电压的电源,通用芯片IC5与DSP3、EEPR0M、10口电信号连接。 , DSP2 is below the lower most of the operational amplifier Al~A18,1 port; Jie Jie the PWM port 6 is connected to the six electrical schematic circuit, 11 ^ 1 and 051 electrical connector, 12 ^ 1 and 05 2?? electrical connection, 1 ^ 11,05? 1,1 ^ 12.05? 2 are connected to the FPGA electrical signal, RAM3 connected DSP3 electrical signal, DSP3 are connected to the electrical DSPl and DSP2, CPLD respectively 03? 1, 03? 2,03? 3,1 ^ electrical connection port 13, 10, respectively 41~418 common operational amplifier 03? 1, DSP2, DSP3,10 electrical connection port, universal power supply chip with an electrically ICl~IC4 signal connections, and provide a different power supply voltages for the device, and the universal chip IC5 DSP3, EEPR0M, 10 port electrical connector.
2.根据权利要求1所述的一种控制36个功率单元的核心控制板,其特征在于所述的FPGA采用的芯片是EP3C16240C8N型。 A core according to a control panel of the power unit 36, wherein the FPGA chip is used according to claim EP3C16240C8N type.
3.根据权利要求1所述的一种控制36个功率单元的核心控制板,其特征在于所述的DSP1、DSP2、DSP3采用TI公司的TMS320x28x系列器件。 According to one of the claims 1 to control the core board 36 of the power unit, characterized in that said DSP1, DSP2, DSP3 TMS320x28x TI's family of devices.
4.根据权利要求1所述的一种控制36个功率单元的核心控制板,其特征在于所述的CPLD采用的芯片是EPM1270T144C5型。 According to one of the claim 1, the core board 36 power control unit, wherein said chip CPLD uses EPM1270T144C5 type.
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