CN101859145A - Quick analog quantity and switching value record test device and test method thereof - Google Patents
Quick analog quantity and switching value record test device and test method thereof Download PDFInfo
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Abstract
The invention discloses a quick analog quantity and switching value record test device and test method thereof. The device comprises a core control module, a communication synchronous distribution module, a switching value output module and a power supply module providing power supply for the modules. Wherein, the test device further comprises an analog quantity output module. The core control module is connected with an upper computer through an Ethernet network and is connected with the communication synchronous distribution module through a PCI bus. The communication synchronous distribution module is connected with the analog quantity output module and the switching value output module through a high speed I/O bus and a synchronous control wire and is connected with a GPS receiving device through a coaxial cable. The communication synchronous distribution module and the upper computer realize time reference synchronization through the GPS receiving device. The invention realizes the synchronous output control of the switching value and the analog quantity and improves the expansion configuration capability of system output type.
Description
Technical field
The present invention relates to a kind of proving installation and method of testing thereof of system log (SYSLOG) performance, relate in particular to the proving installation and the method for testing thereof of a kind of sequence of events recording (SOE) system log (SYSLOG) performance.
Background technology
Along with the digitizer control nuclear power station of new generation use progressively deeply, will be not limited to journal for the requirement of sequence of events recording ability after the accident for the switching value trigger event, also need carry out fast recording for analog quantity.Event sequence recording system is the instrument control subsystem that is used for the anomalous event record in the nuclear power instrument control system, the time interval of the Time To Event of its record, first incident and chain generation incident is the most important foundation of the system failure and anomaly analysis after the accident in proper order, therefore whether qualified the performance index safe operations for nuclear power station such as the accuracy of event sequence recording system and accuracy are most important, adopts testing tool (equipment) that the performance index such as accuracy of event sequence recording system record are tested with verification and be very important.
In the proving installation of existing journal system, can only produce the cycle switch amount signal of particular order, and the time interval of test signal configuration is limited, can only dispose the signal in certain special time period.For the configuration of long-time segment signal, can only realize by the signal repeated trigger of short time period.In addition, in the analysis after the accident of modern nuclear power generator, often need the time of certain change point of comparison analog quantity and the relation between certain group switching value signal.But the proving installation of existing switching value event sequence recording system can only be realized the signal output of the switching value passage of specific interval, can't realize the work information of Simulation of Complex.
The application number that Beijing state gloomy control technology of electricity intelligence company limited submitted in 2008 is 200810239664.8 patent application " a kind of sequence of events recording measuring signal generator and method of testing thereof "; The patent No. that Electric Power Research Institute, Yunnan Power Test ﹠ Research Institute (Group) Co., Ltd. was authorized in 2009 is 200820199874.4 utility model patent " grid equipment SOE high speed resolution test signal generator "; The proving installation that above-mentioned patent documentation is announced does not all relate to the test function that has for event sequence recording system record analog quantity performance, and, can't realize characteristics for large-scale event sequence recording system distributing record for the extendability underaction of system; And the related method of testing of such patent of invention can only can't realize any configuration for the output signal trigger sequence for certain or a plurality of particular sequence in the simulation of certain time period internal trigger.
In addition, in above-mentioned two patents and the described implementation of existing SOE proving installation product, all do not consider following 3 technical matterss:
(1) data interaction of two-forty;
Because original SOE proving installation is primarily aimed at the test of switching value signal, and the data of switching value signal are fairly simple, 1 byte just can be represented the state of 8 passages, the data communication amount is more limited, does not consider that in technical scheme data interactive mode is to SOE proving installation Effect on Performance.And for analog quantity output signals, the model value output signal that precision is 16bit needs to adopt 2 byte representations.The analog output unit spare of 8 passages needs 16 byte representations.And analog signals is different from the switching value output signal, the switching value output signal is output signal discontinuous, burst substantially, and analog quantity output signals need produce the real-time continuous variable signal, so for the SOE proving installation that has the analog quantity output signals test function, data interaction in enormous quantities and the accurate output control method of data sync are key point and the difficult points that realizes this function.
(2) amphicheirality of data interaction;
Because original SOE proving installation all is that the output of signal is controlled, data transmission is an one-way transmission, the flow direction is transmission (host computer-control module-output module) from top to bottom, so the guarantee of original SOE proving installation output accuracy can only be by improving the synchronous clock precision and exporting the real effectiveness that control accuracy guarantee output signal.
(3) modular construction;
The output of existing SOE proving installation at the switching value signal, adopted single system architecture, general only remove to control each output port or by simple expansion module output signal by a block controller, there is not special-purpose data interaction formal definition, single switching value output signal can only be exported, other type output signal can't be expanded.
In sum, existing SOE proving installation fails to realize analog quantity test output function by simple expansion, fails the real-time judge output signal whether to satisfy the requirement of output control.
Summary of the invention
Technical matters to be solved by this invention provides a kind of quick analog quantity and switching value record test device and method of testing thereof, and realization switching value and analog quantity are exported control synchronously, and improves the expandability of system's output type.
The present invention solves the problems of the technologies described above the technical scheme that adopts to provide a kind of quick analog quantity and switching value record test device, comprise core control module, the synchronous distribution module of communication, switching value output module and the power supply module that power supply is provided for above-mentioned module, wherein, described proving installation also comprises the analog quantity output module, described core control module is connected with host computer by Ethernet, and is connected with the synchronous distribution module of described communication by pci bus; The synchronous distribution module of described communication is connected to described analog quantity output module and described switching value output module by High Speed I/O bus and train line, and be connected to the GPS receiving trap by concentric cable, synchronous distribution module of described communication and described host computer are realized the synchronous of time reference by described GPS receiving trap.
Above-mentioned quick analog quantity and switching value record test device, wherein, the synchronous distribution module of described communication comprises fpga core processor, DC/DC circuit, power supply stabilization circuit, 485 circuit, high precision crystal oscillating circuit, optical coupling isolation circuit, FLASH and the SRAM that links to each other by the inner high speed bus, described fpga core processor is configured to synchronous distribution module and communication control module, described communication processing module connects FLASH and SRAM by external bus, expand its data storage areas, described synchronous distribution module directly adopts the hardware description language configuration to form.
Above-mentioned quick analog quantity and switching value record test device, wherein, described analog quantity output module comprises that analog signals output fastener and analog quantity output back pass fastener, both are connected with described communication backboard module by back panel connector, both lay respectively at communication backboard module both sides, and are vertical with communication backboard module.
Above-mentioned quick analog quantity and switching value record test device, wherein, described analog signals output fastener comprises that analog signals output fastener comprises a DSP microprocessor, the 2nd DSP microprocessor, first dual port RAM, second dual port RAM, a SRAM and the 2nd SRAM; A described DSP microprocessor links to each other with described first dual port RAM, second dual port RAM by first internal bus; Described the 2nd DSP microprocessor links to each other with described first dual port RAM, second dual port RAM by second internal bus; A described DSP microprocessor is connected the expansion that is used for the output control circuit data storage by first internal bus with a SRAM, and through optical coupling isolation circuit link to each other with the train line output and the collection of synchro control analog signals; Described the 2nd DSP microprocessor is connected the expansion that is used for the output control circuit data storage by second internal bus with the 2nd SRAM, and links to each other with High Speed I/O bus by 485 circuit and to finish communication receiving/transmission.
Above-mentioned quick analog quantity and switching value record test device, wherein, described switching value output module comprises that switching value signal output fastener and switching value output back pass fastener, and described switching value signal output fastener comprises the little processing of a MEGA8, the little processing of the 2nd MEGA8, first dual port RAM and second dual port RAM; The little processing of a described MEGA8 links to each other with described first dual port RAM, second dual port RAM by first internal bus; The little processing of described the 2nd MEGA8 links to each other with described first dual port RAM, second dual port RAM by second internal bus; The little processing of a described MEGA8 is through optical coupling isolation circuit link to each other with train line synchronous control switch amount defeated output and collection; The little processing of described the 2nd MEGA8 links to each other with High Speed I/O bus by 485 circuit and finishes communication receiving/transmission.
The present invention may further comprise the steps for solving the problems of the technologies described above the method for testing that a kind of above-mentioned quick analog quantity and switching value record test device also is provided: (a) by host computer configuration testing output data; (b) host computer by core control module, the synchronous distribution module of communication and analog quantity output module, that the switching value output module is carried out real time data is mutual, analog quantity output module, switching value output module output configuration, and upload the departure of output signal and original SOE proving installation configuration output data; (c) tested SOE system log (SYSLOG) output signal; (d) host computer obtains deviation data, corrects the configuration testing output data, generates actual test output data; (e) tested SOE system log (SYSLOG) data compare with actual test output data, judge whether tested SOE system satisfies test request.
In the above-mentioned quick analog quantity and switching value record method of testing, real time data may further comprise the steps alternately in the described step (b): (A) described host computer is by Ethernet and the core control module all period interval interaction data information with 1 second; (B) described core control module is by pci bus and the synchronous distribution module of the communication all period interval interaction data information with 100 milliseconds; (C) described communication distribute synchronously fastener by High Speed I/O bus respectively with analog quantity output module and switching value output module polling cycle interaction data information with millisecond.
In the above-mentioned quick analog quantity and switching value record method of testing, fastener is distributed in the middle communication of described step (C) synchronously and analog quantity output module data exchange process is as follows: described the 2nd DSP microprocessor disposes output data by the following cycle that 485 circuit obtain on High Speed I/O bus, and control first dual port RAM by second internal bus, and issue configuration data to the first dual port RAM of following cycle; After to be sent the finishing, the 2nd DSP microprocessor obtains the analog signals deviation data in last cycle by second internal bus from first dual port RAM, and is uploaded to communication by 485 circuit and distributes fastener synchronously; Meanwhile, a DSP microprocessor is controlled second dual port RAM by first internal bus, and exports from the configuration that second dual port RAM obtains this cycle by first internal bus, carries out analog signals output; And a DSP microprocessor is gathered output signal in real time, and is uploaded to second dual port RAM by first internal bus; A described DSP microprocessor, the 2nd DSP microprocessor will by the said process cycle alternately to first dual port RAM, second dual port RAM carries out read-write operation.
In the above-mentioned quick analog quantity and switching value record method of testing, the departure implementation method of uploading output signal and original SOE proving installation configuration output data in the described step (C) is as follows: be provided with the input Acquisition Circuit in described analog quantity output module and the switching value output module, default each the analog quantity maximum deviation of described proving installation and each switching value upset maximum deviation period, when real-time acquisition parameter exceeds this analog quantity maximum deviation or this switching value upset maximum deviation during the period, by the synchronous distribution module of communication, the core control module is uploaded real-time acquisition parameter to described host computer and is corrected output parameter.
The present invention contrasts prior art following beneficial effect: quick analog quantity and switching value record test device provided by the invention and method of testing thereof, increased the analog quantity output module, and realize that by the synchronous distribution module of described communication switching value and analog quantity export control synchronously, thereby the expandability of raising system output type.In addition, quick analog quantity and switching value record test device provided by the invention and method of testing thereof, analog quantity output module and switching value output module adopt two CPU and two dual port RAMs, not only can realize the real-time output control of data, also can realize the real-time collection feedback of output data.
Description of drawings
Fig. 1 is that quick analog quantity and switching value record test device of the present invention is formed structural drawing;
Fig. 2 is that the synchronous distribution module of communication is formed structural drawing among Fig. 1;
Fig. 3 is that the analog quantity output module is formed structural drawing among Fig. 1;
Fig. 4 is that the switching value output module is formed structural drawing among Fig. 1;
Fig. 5 is a quick analog quantity and switching value record test macro implementation process flow diagram of the present invention;
Fig. 6 is quick analog quantity and switching value record test macro data interaction communication process figure of the present invention;
Fig. 7 is that the multizone quick analog quantity and switching value record test macro of the embodiment of the invention is formed structural drawing;
Fig. 8 is the detailed maps of data interaction part in the analog quantity output module in the embodiment of the invention.
Among the figure:
1 host computer, 2 Ethernets, 3 Ethernet switches
4 quick analog quantity and switching value record test devices, 5 GPS receiving traps
The synchronous distribution module of 6 SOE register system 7 core control modules, 8 communications
9 analog quantity output modules, 10 switching value output modules, 11 communication backboard modules
12 power supply modules, 13 accessory power supply modules, 14 pci buss
15 High Speed I/O bus 16 train lines 17 concentric cable
904 first dual port RAMs, 905 second dual port RAMs, 906 common crystals circuit
907 485 circuit, 908 optical coupling isolation circuits, 909 DC/DC circuit
910 power supply stabilization circuits, 911 ADC sample circuits, 912 high precision reference source circuits
913 DAC output circuits, 914 spi bus, 915 first internal buss
916 second internal buss 917 the 2nd SRAM
Little processing 1,003 first dual port RAMs of little processing 1002 the 2nd MEGA8 of 1001 the one MEGA8
1,004 second dual port RAMs, 1005 common crystals circuit, 1006 power supply stabilization circuits
1007 DC/DC circuit, 1008 optical coupling isolation circuits, 1,009 485 circuit
1010 switching value input circuits, 1011 switching value output circuits, 1012 IO interfaces
1,013 first internal buss, 1,014 second internal buss
1101 fpga core processors, 1102 synchronous distribution module 1103 communication control modules
1104 FLASH, 1105 SRAM, 1,106 485 circuit
1107 power supply stabilization circuits, 1108 DC/DC circuit, 1109 optical coupling isolation circuits
1110 high precision crystal oscillating circuits, 1111 inner high speed buses, 1112 external buss
Embodiment
The invention will be further described below in conjunction with drawings and Examples.
Fig. 1 is that quick analog quantity and switching value record test device of the present invention is formed structural drawing.
See also Fig. 1, quick analog quantity and switching value record test device of the present invention comprises core control module 7, the synchronous distribution module 8 of communication, switching value output module 10 and the power supply module 12 that power supply is provided for above-mentioned module, wherein, described proving installation also comprises analog quantity output module 9, described core control module 7 is connected with host computer 1 by Ethernet 2, and is connected with the synchronous distribution module 8 of described communication by pci bus 14; The synchronous distribution module 8 of described communication is connected to described analog quantity output module 9 and described switching value output module 10 by High Speed I/O bus 15 and train line 16, and be connected to GPS receiving trap 5 by concentric cable 17, the synchronous distribution module 8 of described communication is realized the synchronous of time reference with described host computer 1 by described GPS receiving trap 5.
Adopt above-mentioned hardware configuration, analog quantity output module 9 is all passed through High Speed I/O bus 15 with switching value output module 10 and is connected with the synchronous distribution module of communication, the I/O bus standard is unique, and, make dissimilar output fasteners unify control by the synchronous distribution module of communication by adopting with a kind of data format definition mode.
The mode that above-mentioned core control module 7, the synchronous distribution module 8 of communication, analog quantity output module 9, switching value output module 10 are all passed through the backboard connector links to each other with communication backboard module 11.Each module has been realized being connected of signal by pci bus 14, High Speed I/O bus 15 with train line 16 indirectly, and these electric connecting modes that connect signals are realized by communication backboard module 11, and communication backboard module 11 has also been realized power supply power supply for above each module by integrated power supply module 12.
Core control module 7 receives the real-time configuration data and the control command of host computers 1 by Ethernet 2, and deviate data and output module status information of transmission back in real time.Core control module 7 passes through pci bus 14 transmitting data in real time to the synchronous distribution module 8 of communication, and receives in real time from the data of synchronous distribution module 8 passbacks of communication.
The synchronous distribution module 8 of communication is distributed the data transmitted by core control module 7 periodically to each output module, and collects the real time data and the module information of each output module, the unified core control module 7 that is back to.The synchronous distribution module 8 of communication also receives the synchronizing signal that GPS receiving trap 5 issues, this example adopts concentric cable 17, coded system adopts the IRIG-B sign indicating number method of synchronization, by each output module of train line 16 cycle synchronisation, this synchronous implementation belongs to hardware synchronization, and adopts the software synchronization mode for core control module 7.In addition, the GPS receiving trap also carries out Absolute Time Synchronization by 2 pairs of host computers of Ethernet 1, and implementation adopts Network Time Protocol.
Analog quantity output module 9, switching value output module 10 receive the data by synchronous distribution module 8 distributions of communication, and control the synchronous output of each module by train line 16; Meanwhile, analog quantity output module 9, switching value output module 10 be the output information of each module of synchronous acquisition also, surpasses the deviation time that fastener output allows as occurring, and will be uploaded to the synchronous distribution module 8 of communication in real time, so that correct output report.In addition.When module breaks down situation, also will be uploaded to the synchronous distribution module 8 of communication in real time, so that the user finds mistake.
Then the instantiation for the main module in the quick analog quantity and switching value proving installation 4 provided by the invention is described further.
Fig. 2 is that the synchronous distribution module of communication is formed structural drawing among Fig. 1.
See also Fig. 2, the synchronous distribution module 8 of communication in the proving installation of the present invention comprises that mainly the fpga core processor 1101, DC/DC circuit 1108, power supply stabilization circuit 1107,485 circuit 1106, high precision crystal oscillating circuit 1110, optical coupling isolation circuit 1109, FLASH 1104 and the SRAM1105 that link to each other by inner high speed bus 1111 constitute, and wherein the fpga core processor is configured to two parts: synchronous distribution module 1102 and communication control module 1103.
Fpga core processor 1101 adopts the A3P600 of the ProASIC3 FPGA series of ACTEL company, by adopting the soft nuclear technology of IP, CortexM1 key control unit and relevant peripheral hardware resource (pci controller have been disposed, timer, interruptable controller, asynchronous serial controller, storage management controller and input and output IO controller etc.) constituted communication processing module 1103, and, expanded the data storage areas of communication processing module 1103 by external bus 1112 realization connection FLASH 1104 and SRAM 1105.And directly adopt hardware description language to realize for synchronous distribution module 1102.Communication control module 1103 is responsible for carrying out data interaction with pci bus 14, and parallel data is converted to the inner high speed bus to synchronous distribution module 1102, and vice versa.Distribution module 1102 is responsible for the serial data that distribution is transmitted by communication processing module 1103 synchronously, and is distributed to each output module by High Speed I/O bus 15, and distribution module 1102 is connected with High Speed I/O bus 15 by 485 circuit 1106 synchronously.In addition, distribution module 1102 receives the synchronizing signal that GPS receiving trap 5 is issued by concentric cable 17 synchronously, and synchronizing signal is abideed by IRIG-B sign indicating number form, and this method of synchronization is so that 1 second time issued the absolute synchronization coding at interval.Distribution module 1102 adopts high precision crystal oscillating circuit 1110 as the internal system timing synchronously, and every 10ms output synchronizing pulse, by train line 16 to each output module, and GPS receiving trap 5 every 1 second system clock to synchronous distribution module 1102 carry out to the time, correct clock jitter.And the synchronous triggering pulse of distribution module 1102 should be carried out electrical isolation through optical coupling isolation circuit 1109 synchronously.
Power supply stabilization circuit 1107 is responsible for the power supply of the synchronous distribution modules 8 of communication and is supplied with, and DC/DC circuit 1108 is realized for the isolation of powering of optical coupling isolation circuit 1109 and 485 circuit 1106, has improved the reliability of module.
Because distribution module is high for clock request synchronously, can strengthen the precision and the reliability of clock synchronization by the synchronous distribution module that adopts the hardware description language configuration to form.Because the real-time of data communication is had relatively high expectations in the present invention, and the data communication amount is big, by monolithic fpga core processor is configured to synchronous distribution module and communication control module two parts, realized separating of clock synchronization and data interaction, two parts function is not disturbed mutually, thereby satisfied functional requirement of the present invention.
Fig. 3 is that the analog quantity output module is formed structural drawing among Fig. 1.
See also Fig. 3, the analog quantity output module mainly is made of analog signals output fastener and analog quantity output back biography fastener among Fig. 1.Both connect through communication backboard module 11 by back panel connector, and both lay respectively at communication backboard module 11 both sides, and are vertical with communication backboard module 11.
Analog signals output fastener comprises a DSP microprocessor 901, the 2nd DSP microprocessor 902, first dual port RAM 904, second dual port RAM 905, a SRAM 903 and the 2nd SRAM 917; A described DSP microprocessor 901 links to each other with described first dual port RAM 904, second dual port RAM 905 by first internal bus 915; Described the 2nd DSP microprocessor 902 links to each other with described first dual port RAM 904, second dual port RAM 905 by second internal bus 916; A described DSP microprocessor 901 is connected the expansion that is used for the output control circuit data storage by first internal bus 915 with a SRAM 903, and through optical coupling isolation circuit 908 link to each other with train line 16 output and the collection of synchro control analog signals; Described the 2nd DSP microprocessor 902 is connected the expansion that is used for the output control circuit data storage by second internal bus 915 with the 2nd SRAM 917, and links to each other with High Speed I/O bus 15 by 485 circuit 907 and to finish communication receiving/transmission.
Power supply stabilization circuit 910 is responsible for the power supply of analog quantity output modules 9 and is supplied with, and DC/DC circuit 909 is realized for the isolation of powering of optical coupling isolation circuit 908 and 485 circuit 907, has improved the reliability of module.
Analog quantity output back passes fastener and mainly comprises ADC sample circuit 911, high precision reference source circuit 912, DAC output circuit 913.High precision reference source circuit 912 is mainly ADC sample circuit 911 and DAC output circuit 913 provides high-precision reference source.The 911 main real-time collections of being responsible for analog output signal of ADC sample circuit, the 913 main real-time outputs that realize simulating signal of DAC output circuit.ADC sample circuit 911 is connected with output control circuit by spi bus 914 with DAC output circuit 913, by the unified control of output control circuit.
Above-mentioned analog signals output fastener adopts two CPU and two dual port RAMs, realizes the staggered control of data communication and signal output.Because the data communication amount among the present invention is bigger, local output fastener can't both carry out data communication in same control cycle, export control again simultaneously.Described the 2nd DSP microprocessor 902 is responsible for carrying out data interaction with dual port RAM wherein; When next cycle, a described DSP microprocessor 901 can obtain the data in this piece dual port RAM; At this moment, described the 2nd DSP microprocessor 902 is responsible for carrying out data interaction with an other block RAM; By this pattern, communication transceiving circuit and output control circuit will alternately carry out data interaction with two dual port RAMs, are controlled at temporal the conflict thereby solved data communication with output.
Fig. 4 is that the switching value output module is formed structural drawing among Fig. 1.
See also Fig. 4, switching value output module 10 mainly is made of switching value signal output fastener and switching value output back biography fastener among Fig. 1.Both connect through communication backboard module 11 by back panel connector, and both lay respectively at communication backboard module 11 both sides, and are vertical with communication backboard module 11.
Switching value signal output fastener comprises the little processing 1001 of a MEGA8, the little processing 1002 of the 2nd MEGA8, first dual port RAM 1003 and second dual port RAM 1004; The little processing 1001 of a described MEGA8 links to each other with described first dual port RAM 1003, second dual port RAM 1004 by first internal bus 1013; The little processing 1002 of described the 2nd MEGA8 links to each other with described first dual port RAM 1003, second dual port RAM 1004 by second internal bus 1014; The little processing 1001 of a described MEGA8 is through optical coupling isolation circuit 1008 link to each other with train line 16 synchronous control switch amount defeated output and collection; The little processing 1002 of described the 2nd MEGA8 links to each other with High Speed I/O bus 15 by 485 circuit 1009 and finishes communication receiving/transmission.
Power supply stabilization circuit 1006 is responsible for the power supply of switching value output modules 10 and is supplied with, and DC/DC circuit 1007 is realized for the isolation of powering of optical coupling isolation circuit 1008 and 485 circuit 1009, has improved the reliability of module.
Switching value output back passes fastener and mainly comprises switching value input circuit 1010, switching value output circuit 1011.The 1010 main real-time collections of being responsible for the switching value output signal of switching value input circuit, the 1011 main real-time outputs that realize the switching value signal of switching value output circuit.Switching value input circuit 1010 is connected with output control circuit by IO interface 1012 with switching value output circuit 1011, by the unified control of output control circuit.
Fig. 5 is a quick analog quantity and switching value record test system and test process flow diagram flow chart of the present invention.
Please refer to Fig. 5, the present invention also provides a kind of method of testing of above-mentioned quick analog quantity and switching value record test device, and concrete test process is as follows:
Step S1: the test macro wiring connects: a) connect host computer 1 by netting twine, GPS receiving trap 5 is to Ethernet switch 3; B) connect the input end of quick analog quantity and switching value record test device 4 output terminals to system under test (SUT); If system under test (SUT) is dispersed in zones of different, link to each other by Ethernet switch; C) power supply of connection quick analog quantity and switching value proving installation 4 and system under test (SUT); Enter step S2 then;
Step S2: system testing parameter configuration:
The systematic parameter configuration can realize by three kinds of configuration modes: adopt specific test parameter configuration (according to the testing requirement of routine, providing some configuration parameters commonly used, so that the user calls rapidly); Adopt test parameter configuration (, providing parameter configuration function arbitrarily) freely according to special testing requirement; Adopt original storage test parameter configuration (the parameter configuration hold function is provided, so as the user for some fc-specific test FC demand repeat call).
The systematic parameter layoutprocedure is as follows:
A) start configuration software; B) read module information in real time, reach the quantity and the type of affiliated module so that the user confirms the quantity of the quick analog quantity and switching value proving installation of current test macro; C), dispose the test data of each passage arbitrarily according to testing requirement; D) generate data sheet and graphical information, so that check configuration data intuitively; E) preserve test data to database, so that the user calls next time; Enter step S3 then;
Step S3: issue (renewal) configuration data and module output initiation command:
A) upgrade the configuration data that issues; B) issue the output initiation command; Enter step S4 then;
Step S4: each output module is carried out signal output; Each output module is carried out signal output synchronously in real time according to the software arrangements parameter; Enter step S5 then;
Step S5: generate data sheet and graphical information in real time; Gather the information of the affiliated module output channel of quick analog quantity and switching value record test device in real time, real-time update data sheet and graphical information; Enter step S6 then;
Step S6: compare with the SOE record data; According to the data sheet and the graphical information of real-time update,, confirm the performance index of SOE register system with the contrast of SOE register system record data; Enter step S7 then;
Step S7: need to judge whether corrigendum in real time and add the configuration output data, jump to step S2 in this way, otherwise enter step S8;
The user is provided change and configuration feature in real time, the user can be under the situation of not suspending test run, dispose in real time for output parameter, the user jumps to step S2, reenter configuration parameter (the actual output of quick analog quantity and switching value proving installation will still be by original configuration data output, up to execution in step S3).
Step S8: judge whether to stop output, detect host computer in real time and stop output command, judge whether need to continue to carry out, in this way, jump to step S9, as not being to jump to step S4;
Step S9: stop output, finish test, and wait for the output initiation command;
The present invention owing to increased real-time data acquisition and this link of feedback, is different from existing SOE proving installation in whole SOE system testing process.
The method of testing of existing SOE proving installation is generally as follows:
(a) configuration testing output data; (b) the SOE proving installation is exported corresponding signal according to configuration data; (c) tested SOE system log (SYSLOG) output signal; (d) tested SOE system log (SYSLOG) data and configuration testing output data compare, and judge whether tested SOE system satisfies test request.
And as follows for the method for testing of SOE proving installation of the present invention:
(a) configuration testing output data; (b) the SOE proving installation is exported corresponding signal according to configuration data; (c) tested SOE system log (SYSLOG) output signal; (d) gather SOE proving installation output signal in real time, and upload the departure of output signal and original SOE proving installation configuration output data; (e) correct the configuration testing output data, generate actual test output data; (f) tested SOE system log (SYSLOG) data compare with actual test output data, judge whether tested SOE system satisfies test request.
In original method of testing, the data of tested SOE system log (SYSLOG) are to compare with the configuration testing data, and the data by judging tested SOE system log (SYSLOG) and the consistent degree of configuration testing data judge whether tested SOE system satisfies tested requirement.The test configurations data should equal actual output data in theory, but in actual moving process, the influence of uncertain factor because the device signal transmission delay is conflicted with data communication etc., and the output data of reality not necessarily is equal to the configuration testing output data.So, as adopting original method of testing, the credibility of its test result, authenticity and accuracy can't be ensured completely.
Compare with original SOE method of testing, the present invention has increased the collection for real output signal, and feedback and correction SOE configuration testing output data, generates SOE system actual test output data.Tested SOE system log (SYSLOG) data compare with actual test output data, and the data by judging tested SOE system log (SYSLOG) and the consistent degree of actual test output data judge whether tested SOE system satisfies tested requirement.The invention solves the deficiency of original method of testing, make credibility, authenticity and the accuracy of whole test result obtain full guarantee.
Fig. 6 is quick analog quantity and switching value record test macro data interaction communication process figure of the present invention.
Please refer to Fig. 6, the present invention adopts quick analog quantity and switching value record test device 4 to test data communication reciprocal process in the test process of SOE record performances:
A) host computer 1 is by Ethernet 2 and all period interval interaction data information of core control module 7 with 1 second; Data message is divided into two flow directions:
(i) host computer 1 to the data message of core control module 7 is: the configuration parameter of next cycle quick analog quantity and switching value record test device output channel;
(ii) core control module 7 to the data message of host computer 1 is: the actual deviation output parameter of last cycle quick analog quantity and switching value record test device output channel (as in permissible error, will not uploading);
Wherein, should open up configuration and the interactive space of the data space of 0x0000～0xffff as data for the data interaction of core control module 7 with host computer 1.This data space will be mapped to the physical storage data zone of core control module, and this mapping process will be different and different according to controller type, not do tired stating at this, and concrete data space can be allocated as follows:
Every fastener will distribute the data logical space of 0x1000; So the offset address of every fastener is 0x0000～0x0fff; The base address of fastener is by the most significant digit decision of 16 bit address, and the base address of fastener configuration data is from 0x0000, and the specific address of fastener is the base address that offset address adds this fastener; Represent fastener No. 1 as 0x0000～0x0fff, and No. 1 fastener is corresponding to the 3rd slot of communication backboard; Represent fastener No. 2 as 0x1000～0x1fff, and No. 2 fasteners are corresponding to the 4th slot of communication backboard; And the like, configurable altogether 16 output fasteners.Final output fastener number of types is also relevant with the cabinet size, does not do tired stating at this.
0x0000～0x005f is as the attribute area of this fastener in every fastener offset address, and to being divided into two parts by attribute area: 0x0000～0x002f is the down distributing configuration data district, and 0x0030～0x005f is for uploading the status data district;
For the down distributing configuration data district:
Wherein address 0x0000 is fastener type (will mate with the 0x30 actual type):
0x01 represents that on-off output card spare, 0x02 represent that analog output unit spare, 0x03～0xff reserve as other type;
Address 0x0001 is a fastener configuration parameter size, shows total how many bar configuration datas;
For analog output unit spare:
Address 0x0003 is an analog quantity output range type;
Address 0x0004～0x0005 is the first data output of analog quantity output signals of a following cycle time scale information;
Address 0x0006～0x002f is for keeping variable (being used for expansion);
For on-off output card spare:
Address 0x0003 is a switching value output range type;
Address 0x0004～0x0005 is the switching value output switching activity number of times of following cycle;
Address 0x0006～0x002f is for keeping variable (being used for expansion);
For uploading the status data district:
Wherein address 0x0030 is the fastener actual type:
0x01 represents that on-off output card spare, 0x02 represent that analog output unit spare, 0x03～0xff reserve as other type;
Address 0x0031 is a fastener status data size, shows total how many bar state data;
For analog output unit spare:
Address 0x0032 is an analog quantity output actual range type;
Address 0x0033～0x0034 is the first data time scale information of the actual output of analog quantity output signals output of last cycle;
Address 0x0035～0x004f is an analog output unit spare warning message;
Address 0x0050～0x005f is for keeping variable (being used for expansion);
For on-off output card spare:
Address 0x0032 is a switching value output actual range type;
Address 0x0033～0x0034 is the actual upset of switching value output of a last cycle deviation number of times;
Address 0x0035～0x004f is an on-off output card spare warning message;
Address 0x0050～0x005f is for keeping variable (being used for expansion);
For 0x0060～0x0fff in the every fastener offset address is the data field of this fastener, and to should being divided into two parts: 0x0060～0x082f again for issuing the data field in the data field, 0x830～0x0fff is for uploading the deviation data district;
For issuing data:
Wherein the switching value output data is by certain upset of 3 byte representations switching value output state constantly: first byte representation 8 channel switch output states, and every by channel status of 0 and 1 expression: 1 expression is closed, and 0 represents to open; Latter two byte is the upset moment;
And two byte representations are arranged for the analog quantity output data, these two bytes are only represented the analog quantity output signals amplitude, determine (, only needing first data time scale information to get final product) for analog quantity output data time scale information by first data output of this cycle in configuration parameter time scale information because the analog quantity output data in each cycle is all pressed fixed frequency output.
For uploading deviation data:
Wherein the switching value output data by the upset of certain channel errors of 5 byte representations constantly: 80 of first byte represent respectively with 1 data which passage output has deviation in 8 passages, and 1 expression has deviation, and 0 represents bias free; The the 2nd, the 3 this passage of byte representation is provided with upset constantly, and the actual upset of the 4th, the 5 this passage of byte representation constantly.
For analog quantity output data deviation by two byte representations, these two bytes are only represented the amplitude of certain analog quantity output signals constantly, for analog quantity output data time scale information by should first data of cycle in the configuration parameter actual output time scale information decision (, only need first data time scale information getting final product) because the analog quantity output data in each cycle all press the fixed frequency collection.
B) core control module 7 is by pci bus 14 and all period interval interaction data information of the synchronous distribution module of communication with 100 milliseconds; Data message is divided into two flow directions:
(i) core control module 7 to the data message of the synchronous distribution module 8 of communication is: the configuration parameter of next cycle quick analog quantity and switching value record test device output channel;
(ii) the synchronous distribution module 8 of communication to the data message of core control module 7 is: the actual deviation output parameter of last cycle quick analog quantity and switching value record test device output channel (as in permissible error, will not uploading);
C) communication distribute synchronously fastener 8 by High Speed I/O bus 15 respectively with the polling cycle interaction data information of each output module with 10 milliseconds; Data message is divided into two flow directions:
(i) the synchronous distribution module 8 of communication to the data message of each output module is: the configuration parameter of this output module passage of next cycle;
(ii) each output module to the data message of the synchronous distribution module 8 of communication is: last week this output module passage output channel actual deviation output parameter (, will not uploading) as in permissible error.
Output is divided into two types for actual deviation: switching value output bias and analog quantity output bias;
The switching value output bias:
On-off output card spare will be gathered the status information of switching value passage in real time, record upset constantly, and with last cycle output signal ratio, determine deviation constantly, when deviation constantly greater than setting deviation constantly, on-off output card spare will be uploaded deviation information.By the decision of system testing resolving accuracy, for this embodiment, the measuring resolution that proposes meter is 1ms to deviation constantly, is 0.5ms constantly so deviation is set in the output of design switching value.
The analog quantity output bias:
This moment analog quantity channel output signal amplitude will be gathered and write down to analog output unit spare in real time, and set the output signal amplitude relatively, determine the deviation size, when deviation greater than setting deviation, analog output unit spare will be uploaded deviation information.Set deviation by the decision of system simulation amount output accuracy, for this embodiment, the realistic simulation output accuracy that proposes meter is 0.1%, is 0.05% so deviation is set in design simulation output.
Fig. 7 is that the multizone quick analog quantity and switching value record test macro of the embodiment of the invention is formed structural drawing.
Testing system platform example for the SOE system log (SYSLOG) system testing of zones of different constitutes referring to Fig. 7: this quick analog quantity and switching value record test macro comprises host computer 1, Ethernet switch 3, quick analog quantity and switching value record test device 4 and GPS receiving trap 5.Quick analog quantity and switching value record test device 4 and GPS receiving trap 5 are connected to Ethernet switch 3 by Ethernet 2, are connected to host computer 1 by Ethernet 2 again.Synchronous recording performance test for the SOE register system 6 of zones of different can realize synchronism detections by a plurality of quick analog quantity and switching value record test devices 4 of Ethernet 2 expansions.
Fig. 8 is the detailed schematic diagram of data interaction part in the analog quantity output module in the embodiment of the invention.
Seeing also among Fig. 3 analog quantity output module data interaction part is made of a DSP2407, the 2nd DSP2407, first dual port RAM, second dual port RAM.Wherein a DSP2407 is connected with second dual port RAM with first dual port RAM by first internal bus; The 2nd DSP2407 is connected with second dual port RAM with first dual port RAM by second internal bus.Fig. 8 has provided data interaction part first internal bus, the main signal type of second internal bus and connected mode, and has provided the dual port RAM specific embodiment.Dual port RAM adopts CY7C056V:CY7C056V-A to be expressed as first dual port RAM in the present embodiment, and CY7C056V-B is expressed as second dual port RAM.First internal bus comprises: the first interrupt line L, the first busy condition line L, the first semaphore enable line L, the first chip enable line L1, the first chip enable line L2, the first output enable line L, data bus L, address bus L, control bus L, the second interrupt line L, the second busy condition line L, the second chip enable line L1, the second chip enable line L2, the second output enable line L, secondary signal amount enable line L.Second internal bus comprises: the first interrupt line R, the first busy condition line R, the first chip enable line R1, the first chip enable line R2, the first output enable line R, the first semaphore enable line R, data bus R, address bus R, control bus R, the second interrupt line R, the second busy condition line R, the second chip enable line R1, the second chip enable line R2, the second output enable line R, secondary signal amount enable line R.The one DSP2407 is DSP2407-A, and the 2nd DSP2407 is DSP2407-B.
Wherein the I/O-A output pin of DSP2407-A passes through the first output enable line L respectively, the first chip enable line L2, the first chip enable line L1, the OEL-A of first semaphore enable line L control CY7C056V-A, CE1L-A, CE0L-A, SEML-A.By the first interrupt line L, the first busy condition line L exports the I/O-A input pin of DSP2407-A to respectively for the INTL-A of CY7C056V-A, BUSYL-A.The I/O-A output pin of DSP2407-A passes through the second output enable line L again respectively, the second chip enable line L2, the second chip enable line L1, the OEL-B of secondary signal amount enable line L control CY7C056V-B, CE1L-B, CE0L-B, SEML-B.By the second interrupt line L, the second busy condition line L exports the I/O-A input pin of DSP2407-A to respectively for the INTL-B of CY7C056V-B, BUSYL-B.D0～D16-A of DSP2407-A, A0～A13-A, I/O-A are respectively by data bus L, address bus L, I/00L～I/07L-A of control bus L and CY7C056V-A, I/09L～I/16L-A, A0L～A13L-A, R/WL-A, B0～B4-A, I/00L～I/07L-B of CY7C056V-B, I/09L～I/16L-B, A0L～A13L-B, R/WL-B, B0～B4-B links to each other.
Wherein the I/O-B output pin of DSP2407-B passes through the first output enable line R respectively, the first chip enable line R2, the first chip enable line R1, the OER-A of first semaphore enable line R control CY7C056V-A, CE1R-A, CE0R-A, SEMR-A.By the first interrupt line R, the first busy condition line R exports the I/O-B input pin of DSP2407-B to respectively for the INTR-A of CY7C056V-A, BUSYR-A.The I/O-B output pin of DSP2407-B passes through the second output enable line R again respectively, the second chip enable line R2, the second chip enable line R1, the OER-B of secondary signal amount enable line R control CY7C056V-B, CE1R-B, CEOR-B, SEMR-B.By the second interrupt line R, the second busy condition line R exports the I/O-B input pin of DSP2407-B to respectively for the INTR-B of CY7C056V-B, BUSYR-B.D0～D16-B of DSP2407-B, A0～A13-B, I/O-B pass through data bus R, address bus R, I/00R～I/07R-A of control bus R and CY7C056V-A respectively, I/09R～I/16R-A, A0R～A13R-A, R/WR-A, BM-A, SIZE-A, WA-A, BA-A, I/00R～I/07R-B of CY7C056V-B, I/09R～I/16R-B, A0R～A13R-B, R/WR-B, BM-B, SIZE-B, WA-B, BA-B links to each other.
DSP2407-A, DSP2407-B, CY7C056V-A, CY7C056V-B reciprocal process is cycle reciprocal process, one of them cycle reciprocal process is as follows:
DSP2407-A is by the first chip enable line L2, the first chip enable line L1 controls CY7C056V-A, enable CY7C056V-A semaphore read-write capability by the first semaphore enable line L, and by writing 0 to I/00L-A, obtain the control of CY7C056V-A, close CY7C056V-A semaphore read-write capability by the first semaphore enable line L subsequently.DSP2407-A is by data bus L, and address bus L, control bus L write from real time data that High Speed I/O bus interface is received to CY7C056V-A, and read the real-time feedback deviation data that one-period DSP2407-B writes.Meanwhile, DSP2407-B is by the second chip enable line R2, the second chip enable line R1 controls CY7C056V-B, R enables CY7C056V-B semaphore read-write capability by secondary signal amount enable line, and by writing 0 to I/00R-B, obtain the control of CY7C056V-B, close CY7C056V-B semaphore read-write capability by secondary signal amount enable line R subsequently.DSP2407-B passes through data bus R, address bus R, and control bus R reads the real time data that DSP2407-A of last one-period writes among the CY7C056V-B, exports in real time, and writes the deviation data that one-period collects.
After treating that said process finishes, DSP2407-A enables CY7C056V-A semaphore read-write capability by the first semaphore enable line L, and, discharge the control of CY7C056V-A by writing 1 to I/00L-A, close CY7C056V-A semaphore read-write capability by the first semaphore enable line L subsequently.DSP2407-A is by the first chip enable line L2 subsequently, and the first chip enable line L1 abandons controlling CY7C056V-A.Meanwhile, DSP2407-B enables CY7C056V-B semaphore read-write capability by secondary signal amount enable line R, and, discharge the control of CY7C056V-B by writing 1 to I/00R-B, close CY7C056V-B semaphore read-write capability by secondary signal amount enable line R subsequently.DSP2407-B is by the second chip enable line R2 subsequently, and the second chip enable line R1 abandons controlling CY7C056V-B.
Then DSP2407-A will carry out aforesaid operations to CY7C056V-B by above process, and DSP2407-B will carry out aforesaid operations to CY7C056V-A by above process.
DSP2407-A, DSP2407-B will by the said process cycle alternately to CY7C056V-A, CY7C056V-B carries out read-write operation, thereby solves the real-time output of data and the contradiction between the data high-speed communication, also uploads the communication load that is produced in real time for deviation data solution is provided.
Data exchange process is " host computer → synchronous distribution module of core control module → communication → each output module " and " the synchronous distribution module of each output module → communication → core control module → host computer " bidirectional data interaction among the present invention.And the memory data output for each module will reduce successively along with the direction from the host computer-synchronous distribution module of core control module-communication-each output module, so the mutual cycle of data also will reduce successively.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little modification and perfect, so protection scope of the present invention is when with being as the criterion that claims were defined.
Claims (9)
1. quick analog quantity and switching value record test device, comprise core control module (7), the synchronous distribution module of communication (8), switching value output module (10) and the power supply module (12) that power supply is provided for above-mentioned module, it is characterized in that, described proving installation also comprises analog quantity output module (9), described core control module (7) is connected with host computer (1) by Ethernet (2), and is connected with the synchronous distribution module of described communication (8) by pci bus (14); The synchronous distribution module of described communication (8) is connected to described analog quantity output module (9) and described switching value output module (10) by High Speed I/O bus (15) and train line (16), and be connected to GPS receiving trap (5) by concentric cable (17), the synchronous distribution module of described communication (8) is realized the synchronous of time reference with described host computer (1) by described GPS receiving trap (5).
2. quick analog quantity and switching value record test device as claimed in claim 1, it is characterized in that, the synchronous distribution module of described communication (8) comprises the fpga core processor (1101) that links to each other by inner high speed bus (1111), DC/DC circuit (1108), power supply stabilization circuit (1107), 485 circuit (1106), high precision crystal oscillating circuit (1110), optical coupling isolation circuit (1109), FLASH (1104) and SRAM (1105), described fpga core processor (1101) is configured to synchronous distribution module (1102) and communication control module (1103), described communication control module (1103) connects FLASH (1104) and SRAM (1105) by external bus (1112), expand its data storage areas, described synchronous distribution module (1102) directly adopts the hardware description language configuration to form.
3. quick analog quantity and switching value record test device as claimed in claim 1, it is characterized in that, described analog quantity output module (9) comprises that analog signals output fastener and analog quantity output back pass fastener, both are connected with described communication backboard module (11) by back panel connector, both lay respectively at communication backboard module (11) both sides, and are vertical with communication backboard module (11).
4. quick analog quantity and switching value record test device as claimed in claim 3, it is characterized in that, described analog signals output fastener comprises a DSP microprocessor (901), the 2nd DSP microprocessor (902), first dual port RAM (904), second dual port RAM (905) and a SRAM (903), the 2nd SRAM (917); A described DSP microprocessor (901) links to each other with described first dual port RAM (904), second dual port RAM (905) by first internal bus (915); Described the 2nd DSP microprocessor (902) links to each other with described first dual port RAM (904), second dual port RAM (905) by second internal bus (916); A described DSP microprocessor (901) is connected the expansion that is used for the output control circuit data storage by first internal bus (915) with a SRAM (903), and through optical coupling isolation circuit (908) link to each other with train line (16) output and the collection of synchro control analog signals; Described the 2nd DSP microprocessor (902) is connected the expansion that is used for the output control circuit data storage by second internal bus (915) with the 2nd SRAM (917), and links to each other and finish communication receiving/transmission with High Speed I/O bus (15) by 485 circuit (907).
5. quick analog quantity and switching value record test device as claimed in claim 1, it is characterized in that, described switching value output module (10) comprises that switching value signal output fastener and switching value output back pass fastener, and described switching value signal output fastener comprises the little processing of a MEGA8 (1001), the little processing of the 2nd MEGA8 (1002), first dual port RAM (1003) and second dual port RAM (1004); The little processing of a described MEGA8 (1001) links to each other with described first dual port RAM (1003), second dual port RAM (1004) by first internal bus (1013); The little processing of described the 2nd MEGA8 (1002) links to each other with described first dual port RAM (1003), second dual port RAM (1004) by second internal bus (1014); The little processing of a described MEGA8 (1001) is through optical coupling isolation circuit (1008) link to each other with train line (16) synchronous control switch amount defeated output and collection; The little processing of described the 2nd MEGA8 (1002) links to each other and finishes communication receiving/transmission with High Speed I/O bus (15) by 485 circuit (1009).
6. a quick analog quantity and switching value record method of testing adopts the described quick analog quantity and switching value record test device of claim 4 to test, and it is characterized in that, said method comprising the steps of:
(a) by host computer (1) configuration testing output data;
(b) host computer (1) by core control module (7), the synchronous distribution module of communication (8) and analog quantity output module (9), that switching value output module (10) is carried out real time data is mutual, analog quantity output module (9), switching value output module (10) output configuration, and upload the departure of output signal and original SOE proving installation configuration output data;
(c) tested SOE system log (SYSLOG) output signal;
(d) host computer (1) obtains deviation data, corrects the configuration testing output data, generates actual test output data;
(e) tested SOE system log (SYSLOG) data compare with actual test output data, judge whether tested SOE system satisfies test request.
7. one kind as quick analog quantity and switching value record method of testing as described in the claim 6, it is characterized in that real time data may further comprise the steps alternately in the described step (b):
(A) described host computer (1) is by Ethernet (2) and all period interval interaction data information of core control module (7) with 1 second;
(B) described core control module (7) is by pci bus (14) and all period interval interaction data information of the synchronous distribution module of communication (8) with 100 milliseconds;
(C) described communication distribute synchronously fastener (8) by High Speed I/O bus (15) respectively with analog quantity output module (9) and switching value output module (10) polling cycle interaction data information with 10 milliseconds.
8. a quick analog quantity and switching value record method of testing as claimed in claim 7 is characterized in that, fastener (8) is distributed in the middle communication of described step (C) synchronously and analog quantity output module (9) data exchange process is as follows:
Described the 2nd DSP microprocessor (902) disposes output data by the following cycle that 485 circuit (907) obtain on High Speed I/O bus (15), and, and issue configuration data to the first dual port RAM of following cycle (904) by second internal bus (915) control, first dual port RAM (904); After to be sent the finishing, the 2nd DSP microprocessor (902) obtains the analog signals deviation data in last cycle by second internal bus (915) from first dual port RAM (904), and is uploaded to communication by 485 circuit (907) and distributes fastener (8) synchronously; Meanwhile, the one DSP microprocessor (901) is by first internal bus (915) control, second dual port RAM (905), and export from the configuration that second dual port RAM (905) obtains this cycle by first internal bus (915), carry out analog signals output; And a DSP microprocessor (901) is gathered output signal in real time, and is uploaded to second dual port RAM (905) by first internal bus (915);
A described DSP microprocessor (901), the 2nd DSP microprocessor (902) will by the said process cycle alternately to first dual port RAM (904), second dual port RAM (905) carries out read-write operation.
9. quick analog quantity and switching value record method of testing as claimed in claim 7, it is characterized in that, the departure implementation method of uploading output signal and original SOE proving installation configuration output data in the described step (C) is as follows: be provided with the input Acquisition Circuit in described analog quantity output module (9) and the switching value output module (10), default each the analog quantity maximum deviation of described proving installation and each switching value upset maximum deviation period, when real-time acquisition parameter exceeds this analog quantity maximum deviation or this switching value upset maximum deviation during the period, by the synchronous distribution module of communication (8), core control module (7) is uploaded real-time acquisition parameter to described host computer (1) and is corrected output parameter.
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Address after: No.428, Jiangchuan East Road, Minhang District, Shanghai, 200241 Patentee after: STATE NUCLEAR POWER AUTOMATION SYSTEM ENGINEERING Co.,Ltd. Address before: 200233, No. 41 Rainbow Road, Shanghai, Xuhui District Patentee before: STATE NUCLEAR POWER AUTOMATION SYSTEM ENGINEERING Co.,Ltd. |