CN103064790A - Testing method for main control computer - Google Patents

Testing method for main control computer Download PDF

Info

Publication number
CN103064790A
CN103064790A CN2013100133418A CN201310013341A CN103064790A CN 103064790 A CN103064790 A CN 103064790A CN 2013100133418 A CN2013100133418 A CN 2013100133418A CN 201310013341 A CN201310013341 A CN 201310013341A CN 103064790 A CN103064790 A CN 103064790A
Authority
CN
China
Prior art keywords
main control
control computer
test
testing
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2013100133418A
Other languages
Chinese (zh)
Other versions
CN103064790B (en
Inventor
刘劲松
蒋宏斌
王明志
张光淼
董长友
岳立国
李慧
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Harbin Jiancheng Group Co Ltd
Original Assignee
Harbin Jiancheng Group Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Harbin Jiancheng Group Co Ltd filed Critical Harbin Jiancheng Group Co Ltd
Priority to CN201310013341.8A priority Critical patent/CN103064790B/en
Publication of CN103064790A publication Critical patent/CN103064790A/en
Application granted granted Critical
Publication of CN103064790B publication Critical patent/CN103064790B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Abstract

The invention discloses a testing method for a main control computer, and relates to a testing method. The testing method aims to meet testing requirements of main control computers. The testing method includes respectively performing a 1553B bus test, an RT (remote terminal) address test, a DA (digital-to-analog) channel test, an AD (analog-to-digital) channel test, a switch value input test, a switch value output test, a height-pulse receiving test and an RS422/485 serial bus test for the main control computer by test equipment. The testing method has the advantages that the quality of the main control computer can be effectively tested, a working state of the main control computer can be acquired, and the testing cost is saved; the testing requirements of the main control computer can be sufficiently met; and the testing method is applicable to tests for main control computers.

Description

Method of testing to main control computer
Technical field
The present invention relates to a kind of method of testing.
Background technology
The main control computer testing software is mainly finished by testing apparatus, realizes that the test instruction data send, the Data Collection collection analysis is processed and report generation, is the core of testing apparatus; Another part need to be cooperated by main control computer, PXI bus system resource to be realized, namely according to the test instruction of testing apparatus, enter corresponding test procedure, and test result is repaid testing apparatus, testing apparatus also detects the main control computer state simultaneously, judges the duty of system.Main control computer software need to be worked out the needs test module according to test request equally, with cooperating equipment main control computer is carried out full test.
Main communication interface is the 1553B bus interface between main control computer testing apparatus and the main control computer, and testing apparatus is as the BC (total line traffic control) of 1553B bus, and main control computer is as RT (subset).Checkout equipment leaves the monitoring mouth and is used for system state monitoring as communication port.The hardware resources such as the 1553B card of testing apparatus simulation carrier aircraft fire control system by device interior, DI/DO card, A/D-D/A card are finished the sequential control work such as test instruction transmission, power supply control, pumping signal transmission, data acquisition, system state monitoring during test.
Summary of the invention
The present invention is in order to adapt in the digitizing guided weapon system the testing requirement of main control computer, to provide a kind of method of testing to main control computer from face.
Method of testing to main control computer, this method of testing is tested 1553B bus, RT address, DA passage, AD passage, switching value input, switching value output, height reception of impulse and the RS422/485 universal serial bus of main control computer respectively, and detailed process is:
Method of testing to the 1553B bus of main control computer is realized by following steps:
Steps A 1, testing apparatus send 1553 bus test orders by two passages to main control computer respectively by the 1553B bus;
Steps A 2, main control computer are after receiving 1553 bus test orders, and reading information and executing state are back to testing apparatus by two passages respectively;
Steps A 3, testing apparatus judge whether reading information and the executing state received meet respectively default reading information standard and executing state standard, if judged result is yes, and the 1553B bus performance qualified of main control computer then; Finish the 1553B bus test of main control computer;
If the determination result is NO, then the 1553B bus performance index of main control computer is defective; Finish the 1553B bus test of main control computer;
RT address method of testing to main control computer is realized by following steps:
Step B1, under 1553 communications protocol, testing apparatus sends the RT address date to main control computer;
Step B2, main control computer receive that this group RT address date back testing equipment returns the RT address date;
The RT address date that main control computer returns among step B3, the testing apparatus receiving step B2, and judge that this group RT address date is whether consistent with the RT address date that sends among the step B1; If judged result is yes, the RT address date qualified of main control computer then; Finish the RT address date test of main control computer;
If the determination result is NO, then the RT address date index of main control computer is defective; Finish the RT address date test of main control computer;
DA lane testing method to main control computer is realized by following steps:
Step C1, testing apparatus send DA test command and DA test number by the 1553B bus to main control computer;
After step C2, main control computer receive the DA test command, read the DA test number, and pass through the DA passage of main control computer to the AD passage transmission test value of testing apparatus;
The test value that main control computer sends among step C3, the testing apparatus receiving step C2, and judge whether this test value meets default DA performance index, if judged result is yes, the DA channel performance qualified of main control computer then; Finish the DA channel performance test of main control computer;
If the determination result is NO, then the DA channel performance index of main control computer is defective; Finish the DA channel performance test of main control computer;
The AD lane testing method of main control computer is realized by following steps:
Step D1, testing apparatus are by the AD test channel transmission simulating signal of multidiameter delay module to main control computer; Then send the AD test command by the 1553B bus to main control computer;
After step D2, main control computer are received order, read the data-signal in the AD test channel, and this data-signal and executing state are sent to testing apparatus;
Whether main control computer sends among step D3, the testing apparatus receiving step D2 data-signal and executing state meet default AD performance index, if judged result is yes, and the AD channel performance qualified of main control computer then; Finish the AD channel performance test of main control computer;
If the determination result is NO, then the AD channel performance index of main control computer is defective; Finish the AD channel performance test of main control computer;
Switching value input test method to main control computer is realized by following steps:
Step e 1, testing apparatus are by the switching value signal input channel transmit button amount signal of DO module to main control computer; Then pass through the 1553B bus to main control computer transmit button amount input test order;
Step e 2, main control computer are received switching value input test order, the switching value signal in the read switch amount signal input channel, and this switching value signal and executing state sent to testing apparatus;
Whether the switching value signal that main control computer sends among step e 3, the testing apparatus receiving step E2 and executing state meet default switching value input performance index, if judged result is yes, then the switching value of main control computer is inputted the performance qualified; Finish the switching value input performance test of main control computer;
If the determination result is NO, then the switching value of main control computer input performance index are defective; Finish the switching value input performance test of main control computer;
Switching value output testing method to main control computer is realized by following steps:
Step F 1, testing apparatus are exported test command by the 1553B bus to main control computer transmit button amount;
Step F 2, main control computer are received switching value output test command, to testing apparatus DI passage transmit button amount signal, and execution information are sent to testing apparatus by the switching value signal output channels;
Step F 3, testing apparatus read switching value signal and the execution information in the DI passage, and judge whether this switching value signal and execution information meet default switching value output performance index, if judged result is yes, the switching value output performance qualified of main control computer then; Finish the switching value output performance test of main control computer;
If the determination result is NO, then the switching value output performance index of main control computer is defective; Finish the switching value output performance test of main control computer;
Height reception of impulse method of testing to main control computer is realized by following steps:
Then step G1, testing apparatus pass through the 1553B bus to the order of main control computer transmitted signal testing by reception of impulse passage transmission simulated altitude table height pulse signal, count signal and the height indicator status signal of the pulse signal generator on the serial ports test card to main control computer;
Step G2, main control computer return pulse signal test command, receive simulated altitude table height pulse signal, count signal and height indicator state by the reception of impulse passage, and simulated altitude table height pulse signal, count signal, height indicator state and executing state signal are sent to testing apparatus;
Main control computer sends among step G3, the testing apparatus read step G2 simulated altitude table height pulse signal, count signal, height indicator state and execution state information, and judge whether this simulated altitude table height pulse signal, count signal, height indicator state and execution state information meet default height pulse performance index, if judged result is yes, the height pulse performance qualified of main control computer then; Finish the height pulse performance test of main control computer;
If the determination result is NO, then the height pulse performance index of main control computer are defective; Finish the height pulse performance test of main control computer;
RS422/485 serial bus testing method to main control computer is realized by following steps:
Then step H1, testing apparatus send the serial ports test command by the 1553B bus to main control computer by the serial communication interface transmission data of serial ports test card to main control computer;
Step H2, main control computer receive the serial ports test command, read serial data, and this serial data and executing state are sent to testing apparatus;
The execution state information that main control computer sends among step H3, the testing apparatus receiving step H2, and judge whether this executing state is normal, if the determination result is NO, then re-start test; If judged result is yes, then read the serial data that main control computer sends, and judge this serial data whether with step H1 in the serial data that sends whether identical, if judged result is yes, then the RS422/485 universal serial bus performance index of main control computer are qualified; Finish the RS422/485 universal serial bus performance test of main control computer;
If the determination result is NO, then the RS422/485 universal serial bus performance index of main control computer are defective; Finish the RS422/485 universal serial bus performance test of main control computer.
This method can Validity Test digitizing guided weapon system in the quality of main control computer, know duty, save testing cost.Fully adapted to the testing requirement to main control computer.
Description of drawings
Fig. 1 is test index and the power supply state principle schematic to the main control computer method of testing among the present invention; Fig. 2 is the test process schematic diagram.
Embodiment
Embodiment one, to the method for testing of main control computer, this method of testing is tested 1553B bus, RT address, DA passage, AD passage, switching value input, switching value output, height reception of impulse and the RS422/485 universal serial bus of main control computer respectively, and detailed process is:
Method of testing to the 1553B bus of main control computer is realized by following steps:
Steps A 1, testing apparatus send 1553 bus test orders by two passages to main control computer respectively by the 1553B bus;
Steps A 2, main control computer are after receiving 1553 bus test orders, and reading information and executing state are back to testing apparatus by two passages respectively;
Steps A 3, testing apparatus judge whether reading information and the executing state received meet respectively default reading information standard and executing state standard, if judged result is yes, and the 1553B bus performance qualified of main control computer then; Finish the 1553B bus test of main control computer;
If the determination result is NO, then the 1553B bus performance index of main control computer is defective; Finish the 1553B bus test of main control computer;
RT address method of testing to main control computer is realized by following steps:
Step B1, under 1553 communications protocol, testing apparatus sends the RT address date to main control computer;
Step B2, main control computer receive that this group RT address date back testing equipment returns the RT address date;
The RT address date that main control computer returns among step B3, the testing apparatus receiving step B2, and judge that this group RT address date is whether consistent with the RT address date that sends among the step B1; If judged result is yes, the RT address date qualified of main control computer then; Finish the RT address date test of main control computer;
If the determination result is NO, then the RT address date index of main control computer is defective; Finish the RT address date test of main control computer;
DA lane testing method to main control computer is realized by following steps:
Step C1, testing apparatus send DA test command and DA test number by the 1553B bus to main control computer;
After step C2, main control computer receive the DA test command, read the DA test number, and pass through the DA passage of main control computer to the AD passage transmission test value of testing apparatus;
The test value that main control computer sends among step C3, the testing apparatus receiving step C2, and judge whether this test value meets default DA performance index, if judged result is yes, the DA channel performance qualified of main control computer then; Finish the DA channel performance test of main control computer;
If the determination result is NO, then the DA channel performance index of main control computer is defective; Finish the DA channel performance test of main control computer;
The AD lane testing method of main control computer is realized by following steps:
Step D1, testing apparatus are by the AD test channel transmission simulating signal of multidiameter delay module to main control computer; Then send the AD test command by the 1553B bus to main control computer;
After step D2, main control computer are received order, read the data-signal in the AD test channel, and this data-signal and executing state are sent to testing apparatus;
Whether main control computer sends among step D3, the testing apparatus receiving step D2 data-signal and executing state meet default AD performance index, if judged result is yes, and the AD channel performance qualified of main control computer then; Finish the AD channel performance test of main control computer;
If the determination result is NO, then the AD channel performance index of main control computer is defective; Finish the AD channel performance test of main control computer;
Switching value input test method to main control computer is realized by following steps:
Step e 1, testing apparatus are by the switching value signal input channel transmit button amount signal of DO module to main control computer; Then pass through the 1553B bus to main control computer transmit button amount input test order;
Step e 2, main control computer are received switching value input test order, the switching value signal in the read switch amount signal input channel, and this switching value signal and executing state sent to testing apparatus;
Whether the switching value signal that main control computer sends among step e 3, the testing apparatus receiving step E2 and executing state meet default switching value input performance index, if judged result is yes, then the switching value of main control computer is inputted the performance qualified; Finish the switching value input performance test of main control computer;
If the determination result is NO, then the switching value of main control computer input performance index are defective; Finish the switching value input performance test of main control computer;
Switching value output testing method to main control computer is realized by following steps:
Step F 1, testing apparatus are exported test command by the 1553B bus to main control computer transmit button amount;
Step F 2, main control computer are received switching value output test command, to testing apparatus DI passage transmit button amount signal, and execution information are sent to testing apparatus by the switching value signal output channels;
Step F 3, testing apparatus read switching value signal and the execution information in the DI passage, and judge whether this switching value signal and execution information meet default switching value output performance index, if judged result is yes, the switching value output performance qualified of main control computer then; Finish the switching value output performance test of main control computer;
If the determination result is NO, then the switching value output performance index of main control computer is defective; Finish the switching value output performance test of main control computer;
Height reception of impulse method of testing to main control computer is realized by following steps:
Then step G1, testing apparatus pass through the 1553B bus to the order of main control computer transmitted signal testing by reception of impulse passage transmission simulated altitude table height pulse signal, count signal and the height indicator status signal of the pulse signal generator on the serial ports test card to main control computer;
Step G2, main control computer return pulse signal test command, receive simulated altitude table height pulse signal, count signal and height indicator state by the reception of impulse passage, and simulated altitude table height pulse signal, count signal, height indicator state and executing state signal are sent to testing apparatus;
Main control computer sends among step G3, the testing apparatus read step G2 simulated altitude table height pulse signal, count signal, height indicator state and execution state information, and judge whether this simulated altitude table height pulse signal, count signal, height indicator state and execution state information meet default height pulse performance index, if judged result is yes, the height pulse performance qualified of main control computer then; Finish the height pulse performance test of main control computer;
If the determination result is NO, then the height pulse performance index of main control computer are defective; Finish the height pulse performance test of main control computer;
RS422/485 serial bus testing method to main control computer is realized by following steps:
Then step H1, testing apparatus send the serial ports test command by the 1553B bus to main control computer by the serial communication interface transmission data of serial ports test card to main control computer;
Step H2, main control computer receive the serial ports test command, read serial data, and this serial data and executing state are sent to testing apparatus;
The execution state information that main control computer sends among step H3, the testing apparatus receiving step H2, and judge whether this executing state is normal, if the determination result is NO, then re-start test; If judged result is yes, then read the serial data that main control computer sends, and judge this serial data whether with step H1 in the serial data that sends whether identical, if judged result is yes, then the RS422/485 universal serial bus performance index of main control computer are qualified; Finish the RS422/485 universal serial bus performance test of main control computer;
If the determination result is NO, then the RS422/485 universal serial bus performance index of main control computer are defective; Finish the RS422/485 universal serial bus performance test of main control computer.
In the RS422/485 serial bus testing method to main control computer, the universal serial bus performance of test is inertial navigation RS422 universal serial bus, remote measurement RS422 universal serial bus or submunition RS485 universal serial bus.
Main control computer test is divided into 1553B bus test, multidiameter delay DA test, multidiameter delay AD test, the input test of switching value signal, switching value signal exports test, serial test bus, highly pulse test, test function can localization of fault in the integrated circuit board level.
Test event as shown in Figure 1, test process as shown in Figure 2:
Step starts the testing software interface, fills in the information such as test product numbering, tester and reviewer, clicks product for eletric button;
Step 2 is clicked product for behind the eletric button, main control computer after receiving the checkout equipment order, wait for that the 30s System self-test is good after, the START button on the hit testing master interface;
Step 3, when beginning to test, below, interface test mode Information shows the information such as current test event and current RT address state.Program is tested successively by interface display " test event " order.Test result is qualified to give a green light, and mistake sends out a warning and " error count " adds 1.
Step 4 shows after the START button click to become " stopping " that click " stopping " testing software continues to finish and stops to test after time test loop.As not clicking " stopping ", finish after time test loop and continue next time test loop.
Step 5, after test finished, the demonstration of " stopping " button became " beginning " again, can click this button such as need continuation test and again test.Click " withdrawing from " button, return startup interface.Clicking startup interface " product outage " button stops to provide working power to test product.Click " withdrawing from " button and stop test procedure.
Step 6, record test data was to be used for generating test report after test event was finished; As preferably, assign described each test instruction to main control computer by 1553 buses.
Test pattern mainly is that the correctness for the transmission of the performance of verifying each integrated circuit board and certificate parameter designs.When carrying out the complete machine environmental test, mainly test with test pattern.
Test pattern comprises sub-1553B bus test, multidiameter delay DA test, multidiameter delay AD test, the input test of switching value signal, switching value signal output test, serial test bus, height pulse test etc.
After entering test interface, fill in after product information arranges, click product for eletric button, enter the main interface of test, test event title, testing time, errors number on test interface, after pressing START button, checkout equipment will be passed to main control computer by 1553 buses under " test instruction ", constantly receive simultaneously " test instruction " that main control computer is uploaded, on test interface, can see that each item argument back pilot lamp turns green successively, and record testing time and errors number.
Each indication test method is specially:
The 1553B bus test:
Testing software sends 1553 bus test test commands by the 1553B bus to main control computer, selects respectively A, B passage to test.After main control computer is received order, carry out bus test, information and the executing state that reads returned to testing software, carry out qualification determination by testing software.If the judged result mistake, then error count adds 1.Testing software need carry out twice test loop and finish A, B lane testing.
The test of RT address:
According to 1553 communications protocol, the RT address date that BC end sends to RT on bus is corresponding with the RT address that hardware is sent, and bus just can be carried out communication normally.This test is that the address interpretation is tested to main control computer hardware RT.Testing software RT address of per twice test loop change, the information hurdle shows current RT address information in real time.Testing software need carry out 60 test loop and finish a RT full address (1~30) test.
The DA lane testing:
Test procedure sends DA test command and DA test number by the 1553B bus to main control computer.After main control computer is received order, read DA numerical value, send a signal to the AD test channel of testing apparatus by main control computer DA passage, testing software reads the AD data and carries out qualification determination.If the judged result mistake, then error count adds 1.
This has comprised the test that steering wheel control 1, steering wheel control 2, steering wheel control 3 and steering wheel are controlled 4 four paths.
The AD lane testing:
Testing software sends simulating signal by multidiameter delay DA module to main control computer AD test channel, then sends the AD test command by the 1553B bus to main control computer; After main control computer is received order, read AD passage numerical value, and this numerical value and executing state are returned to testing software, carry out qualification determination by testing software.If the judged result mistake, then error count adds 1.
This test has comprised the test of steering wheel feedback 1, steering wheel feedback 2, steering wheel feedback 3, steering wheel feedback 4, steering wheel+15V and six passages of steering wheel-15V.
The switching value input test;
Testing software passes through the interior signal output apparatus of DO module controls measurement and control unit to main control computer switching value signal input channel transmit button amount signal, then pass through the 1553B bus to main control computer transmit button amount input test order, after main control computer is received order, read switch amount status information, and this information and executing state returned testing software, carry out qualification determination by testing software.If the judged result mistake, then error count adds 1.
This has comprised the test of judging thermobattery 1, judgement thermobattery 2, the separation of machine bullet, the locking of machine bullet and five passages of input permission.
Switching value output test:
Testing software exports test command by the 1553B bus to main control computer transmit button amount, after main control computer is received order, main control computer passes through the switching value signal output channels to testing apparatus DI module transmit button amount signal, and execution information sent to testing software, testing software reads DI information and carries out qualification determination.If the judged result mistake, then error count adds 1.
This has comprised activation heat battery I-1, activation heat battery I-2, activation heat battery II-1, activation heat battery II-2, height indicator penetrate that inspection instruction, control chord 1, control chord 2, control open the cabin 1, control is opened the cabin 2, control sheds 1,2......, 11,12, fuse solution protect 1 and the fuse solution protect the test of 2 two ten three passages.
Height reception of impulse test:
Testing software sends simulated altitude table height pulse signal, count signal and height indicator status signal by the pulse signal generator on the serial ports test card to main control computer reception of impulse passage, then pass through the 1553B bus to the order of main control computer transmitted signal testing, after main control computer is received order, read height step-by-step counting and state, and with this information and and executing state return to testing software, carry out qualification determination by testing software.If the judged result mistake, then error count adds 1.
RS422,485 serial test bus:
Testing software sends data by the serial ports test card to the main control computer serial communication interface, then sends corresponding serial ports test command by the 1553B bus to main control computer; After main control computer is received order, read the data of corresponding serial ports, and this data communication device is crossed corresponding serial ports send to testing software, by bus executing state is returned to testing software.After testing software judges that executing state is normal, read corresponding serial data and carry out data relatively; If inconsistent with the data that send, then error count adds 1.
This test has comprised the test of inertial navigation RS422, remote measurement RS422 and three groups of serial bus channels of submunition RS485.
Above-described specific descriptions; purpose, technical scheme to invention further describe; institute is understood that; the above only is specific embodiments of the invention; the protection domain that is not intended to limit the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (2)

1. to the method for testing of main control computer, it is characterized in that, this method of testing is tested 1553B bus, RT address, DA passage, AD passage, switching value input, switching value output, height reception of impulse and the RS422/485 universal serial bus of main control computer respectively, and detailed process is:
Method of testing to the 1553B bus of main control computer is realized by following steps:
Steps A 1, testing apparatus send 1553 bus test orders by two passages to main control computer respectively by the 1553B bus;
Steps A 2, main control computer are after receiving 1553 bus test orders, and reading information and executing state are back to testing apparatus by two passages respectively;
Steps A 3, testing apparatus judge whether reading information and the executing state received meet respectively default reading information standard and executing state standard, if judged result is yes, and the 1553B bus performance qualified of main control computer then; Finish the 1553B bus test of main control computer;
If the determination result is NO, then the 1553B bus performance index of main control computer is defective; Finish the 1553B bus test of main control computer;
RT address method of testing to main control computer is realized by following steps:
Step B1, under 1553 communications protocol, testing apparatus sends the RT address date to main control computer;
Step B2, main control computer receive that this group RT address date back testing equipment returns the RT address date;
The RT address date that main control computer returns among step B3, the testing apparatus receiving step B2, and judge that this group RT address date is whether consistent with the RT address date that sends among the step B1; If judged result is yes, the RT address date qualified of main control computer then; Finish the RT address date test of main control computer;
If the determination result is NO, then the RT address date index of main control computer is defective; Finish the RT address date test of main control computer;
DA lane testing method to main control computer is realized by following steps:
Step C1, testing apparatus send DA test command and DA test number by the 1553B bus to main control computer;
After step C2, main control computer receive the DA test command, read the DA test number, and pass through the DA passage of main control computer to the AD passage transmission test value of testing apparatus;
The test value that main control computer sends among step C3, the testing apparatus receiving step C2, and judge whether this test value meets default DA performance index, if judged result is yes, the DA channel performance qualified of main control computer then; Finish the DA channel performance test of main control computer;
If the determination result is NO, then the DA channel performance index of main control computer is defective; Finish the DA channel performance test of main control computer;
The AD lane testing method of main control computer is realized by following steps:
Step D1, testing apparatus are by the AD test channel transmission simulating signal of multidiameter delay module to main control computer; Then send the AD test command by the 1553B bus to main control computer;
After step D2, main control computer are received order, read the data-signal in the AD test channel, and this data-signal and executing state are sent to testing apparatus;
Whether main control computer sends among step D3, the testing apparatus receiving step D2 data-signal and executing state meet default AD performance index, if judged result is yes, and the AD channel performance qualified of main control computer then; Finish the AD channel performance test of main control computer;
If the determination result is NO, then the AD channel performance index of main control computer is defective; Finish the AD channel performance test of main control computer;
Switching value input test method to main control computer is realized by following steps:
Step e 1, testing apparatus are by the switching value signal input channel transmit button amount signal of DO module to main control computer; Then pass through the 1553B bus to main control computer transmit button amount input test order;
Step e 2, main control computer are received switching value input test order, the switching value signal in the read switch amount signal input channel, and this switching value signal and executing state sent to testing apparatus;
Whether the switching value signal that main control computer sends among step e 3, the testing apparatus receiving step E2 and executing state meet default switching value input performance index, if judged result is yes, then the switching value of main control computer is inputted the performance qualified; Finish the switching value input performance test of main control computer;
If the determination result is NO, then the switching value of main control computer input performance index are defective; Finish the switching value input performance test of main control computer;
Switching value output testing method to main control computer is realized by following steps:
Step F 1, testing apparatus are exported test command by the 1553B bus to main control computer transmit button amount;
Step F 2, main control computer are received switching value output test command, to testing apparatus D1 passage transmit button amount signal, and execution information are sent to testing apparatus by the switching value signal output channels;
Step F 3, testing apparatus read switching value signal and the execution information in the DI passage, and judge whether this switching value signal and execution information meet default switching value output performance index, if judged result is yes, the switching value output performance qualified of main control computer then; Finish the switching value output performance test of main control computer;
If the determination result is NO, then the switching value output performance index of main control computer is defective; Finish the switching value output performance test of main control computer;
Height reception of impulse method of testing to main control computer is realized by following steps:
Then step G1, testing apparatus pass through the 1553B bus to the order of main control computer transmitted signal testing by reception of impulse passage transmission simulated altitude table height pulse signal, count signal and the height indicator status signal of the pulse signal generator on the serial ports test card to main control computer;
Step G2, main control computer return pulse signal test command, receive simulated altitude table height pulse signal, count signal and height indicator state by the reception of impulse passage, and simulated altitude table height pulse signal, count signal, height indicator state and executing state signal are sent to testing apparatus;
Main control computer sends among step G3, the testing apparatus read step G2 simulated altitude table height pulse signal, count signal, height indicator state and execution state information, and judge whether this simulated altitude table height pulse signal, count signal, height indicator state and execution state information meet default height pulse performance index, if judged result is yes, the height pulse performance qualified of main control computer then; Finish the height pulse performance test of main control computer;
If the determination result is NO, then the height pulse performance index of main control computer are defective; Finish the height pulse performance test of main control computer;
RS422/485 serial bus testing method to main control computer is realized by following steps:
Then step H1, testing apparatus send the serial ports test command by the 1553B bus to main control computer by the serial communication interface transmission data of serial ports test card to main control computer;
Step H2, main control computer receive the serial ports test command, read serial data, and this serial data and executing state are sent to testing apparatus;
The execution state information that main control computer sends among step H3, the testing apparatus receiving step H2, and judge whether this executing state is normal, if the determination result is NO, then re-start test; If judged result is yes, then read the serial data that main control computer sends, and judge this serial data whether with step H1 in the serial data that sends whether identical, if judged result is yes, then the RS422/485 universal serial bus performance index of main control computer are qualified; Finish the RS422/485 universal serial bus performance test of main control computer;
If the determination result is NO, then the RS422/485 universal serial bus performance index of main control computer are defective; Finish the RS422/485 universal serial bus performance test of main control computer.
2. the method for testing to main control computer according to claim 1, it is characterized in that in the RS422/485 serial bus testing method of main control computer, the universal serial bus performance of test is inertial navigation RS422 universal serial bus, remote measurement RS422 universal serial bus or submunition RS485 universal serial bus.
CN201310013341.8A 2013-01-15 2013-01-15 To the method for testing of main control computer Active CN103064790B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201310013341.8A CN103064790B (en) 2013-01-15 2013-01-15 To the method for testing of main control computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310013341.8A CN103064790B (en) 2013-01-15 2013-01-15 To the method for testing of main control computer

Publications (2)

Publication Number Publication Date
CN103064790A true CN103064790A (en) 2013-04-24
CN103064790B CN103064790B (en) 2016-03-02

Family

ID=48107423

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310013341.8A Active CN103064790B (en) 2013-01-15 2013-01-15 To the method for testing of main control computer

Country Status (1)

Country Link
CN (1) CN103064790B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103542865A (en) * 2013-08-23 2014-01-29 航天科工惯性技术有限公司 Testing and controlling method and device
CN104866400A (en) * 2015-05-20 2015-08-26 中国空间技术研究院 Method for verifying protocol control function of 1553B bus controller
CN108089952A (en) * 2016-11-22 2018-05-29 北京计算机技术及应用研究所 A kind of automated test device
CN110943894A (en) * 2019-12-31 2020-03-31 潍柴动力股份有限公司 Message testing method and device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1484147A (en) * 2002-09-20 2004-03-24 联想(北京)有限公司 System and method for realizing automatic on/off test of computer
US20090128173A1 (en) * 2007-11-16 2009-05-21 Hong Fu Jin Precision Industry(Shenzhen) Co., Ltd. Testing system and method
CN202282781U (en) * 2011-11-01 2012-06-20 南京鑫轩电子系统工程有限公司 TR assembly automatic test system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1484147A (en) * 2002-09-20 2004-03-24 联想(北京)有限公司 System and method for realizing automatic on/off test of computer
US20090128173A1 (en) * 2007-11-16 2009-05-21 Hong Fu Jin Precision Industry(Shenzhen) Co., Ltd. Testing system and method
CN202282781U (en) * 2011-11-01 2012-06-20 南京鑫轩电子系统工程有限公司 TR assembly automatic test system

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103542865A (en) * 2013-08-23 2014-01-29 航天科工惯性技术有限公司 Testing and controlling method and device
CN103542865B (en) * 2013-08-23 2016-09-07 航天科工惯性技术有限公司 Investigating method and device
CN104866400A (en) * 2015-05-20 2015-08-26 中国空间技术研究院 Method for verifying protocol control function of 1553B bus controller
CN104866400B (en) * 2015-05-20 2018-03-09 中国空间技术研究院 A kind of verification method of 1553B bus control units protocol integrated test system function
CN108089952A (en) * 2016-11-22 2018-05-29 北京计算机技术及应用研究所 A kind of automated test device
CN108089952B (en) * 2016-11-22 2021-11-16 北京计算机技术及应用研究所 Automatic change test equipment
CN110943894A (en) * 2019-12-31 2020-03-31 潍柴动力股份有限公司 Message testing method and device

Also Published As

Publication number Publication date
CN103064790B (en) 2016-03-02

Similar Documents

Publication Publication Date Title
CN102092477B (en) Device and method for automatic test and fault diagnosis of plane audio integrated system
CN201757767U (en) General comprehensive automatic test system of airplane electronic part
CN101788945B (en) Diagnostic test system and method for electronic system with multiple circuit boards or multiple modules
CN103150239B (en) Automatic test system of main control computer
CN102030111B (en) Aircraft CFDS (Centralized Fault Display System) data analyzer and implementation method thereof
CN102520715A (en) Universal satellite ground overall control test system
CN103064790B (en) To the method for testing of main control computer
CN104198868A (en) Intelligent tool capable of being flexibly expanded and dynamically configured
CN102184749A (en) Method for automatically testing DCS (Digital Control System) control cabinet
CN104656632A (en) Integrated interface test system and detection method for aircraft semi-physical simulation tests
CN201072597Y (en) Automatic detection instrument for aviation electronic flight instrument
CN101342946A (en) Automatic testing equipment and method for audio frequency management assembly of airbus aircrafts
CN107515370A (en) A kind of PCBA detection means and detection method
CN106941434A (en) The detecting system and method for a kind of communication message
CN106291329A (en) A kind of have the automatic test system detecting and joining the distant function of a terminal three
CN106205755A (en) Reactor protection system Channel Response Time Intelligentized test system and method
CN106200623B (en) The semi-physical simulation test device of reactor core measuring system logic module
CN203054825U (en) Automatic test system of main control computer
CN106681313A (en) Function testing method of dynamic stability control system and dynamic stability control system
CN208421628U (en) Multiplexing automatic testing stand based on virtual instrument
CN209264906U (en) CVC-200T hardware intelligent test system
CN108803564B (en) Automatic testing system and method for communication control equipment
CN208796101U (en) Automobile audio entertainment systems automaticdiagnosis test macro
CN106814728A (en) A kind of assembly detection apparatus based on product power supply interface sequential logic
CN104965133A (en) 1553B data bus network test system

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant