CN101841240B - Power supply converter and error amplifier - Google Patents
Power supply converter and error amplifier Download PDFInfo
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- CN101841240B CN101841240B CN2010101445216A CN201010144521A CN101841240B CN 101841240 B CN101841240 B CN 101841240B CN 2010101445216 A CN2010101445216 A CN 2010101445216A CN 201010144521 A CN201010144521 A CN 201010144521A CN 101841240 B CN101841240 B CN 101841240B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
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Abstract
The invention discloses a power supply converter which comprises an output circuit with a power switch, a voltage feedback circuit, an error amplifier and a pulse width modulating comparator, wherein the output circuit is used for modulating an input voltage into an output voltage under the on-off control of the power switch; the voltage feedback circuit is used for sampling the output voltage to obtain a feedback voltage; the error amplifier clamps an output error amplifying signal and is used for carrying out error amplification on a reference voltage and the feedback voltage to obtain an error amplifying voltage; the pulse width modulating comparator is used for comparing the error amplifying voltage with a triangular wave signal to generate a pulse width modulating signal; and the pulse width modulating signal is used for controlling the on-off of the power switch. The power supply converter effectively improves the load response by introduction of the error amplifier which can clamp the output error amplifying signal.
Description
[technical field]
The present invention relates to circuit field, particularly relate to a kind of power supply changeover device and error amplifier.
[background technology]
Power supply changeover device is widely used in the various portable electric appts, and the DC/DC transducer that boosts (boostDC/DC converter) is wherein a kind of.
Fig. 1 is a kind of circuit diagram of the DC/DC transducer that boosts.Please refer to shown in Figure 1ly, the said DC/DC of boosting transducer 100 includes the output circuit 110 that boosts, voltage feedback circuit 120, error amplifier 130, pulse-width modulation comparator 140 and logic control circuit 150.
The said output circuit 110 that boosts comprises inductance L, diode D, nmos pass transistor MN1 and capacitor C out; One end of inductance L connects input voltage vin; The other end links to each other with the anode of diode D; The negative electrode of diode D links to each other with the end of capacitor C out; The intermediate node voltage of diode D and capacitor C out is as output voltage V out, and the grid of said nmos pass transistor MN1 is as the pulse-width signal of the control end RL control circuit 150 of the output circuit 110 that boosts, and the drain electrode of said NMOS pipe MN1 links to each other with the intermediate node of inductance L and diode; The source electrode of said NMOS pipe MN1 and the other end of capacitor C link to each other with ground, and said transistor MN1 is a power switch pipe.Said voltage feedback circuit 120 comprises resistance R 1 and the R2 that is connected between output voltage and the ground, and said resistance R 1 has been formed a bleeder circuit with R2, thereby the said output voltage V out that samples is to obtain feedback voltage Vfb.Said error amplifier 130 is used for reference voltage Vref and feedback voltage Vfb are carried out the error amplification with output error amplifying signal EAO.Said pulse-width modulation comparator 140 is used for error amplification signal EAO and triangular signal Ramp are compared to generate pulse-width signal PWMO.Said logic control circuit 150 is used for pulse-width signal PWMO is carried out logic control; And go to control conducting and the shutoff of said power switch MN1 with the pulse-width signal NPWM after the logic control, said logic control comprises control logics such as maximum duty cycle and minimum duty cycle are set.
After setting reference voltage Vref and exporting feedback resistance R1 and R2, system's loop will make output voltage reach set point through error amplifier 130 and the pulse-width signal that PWM comparator 140 produces certain duty ratios (Duty cycle):
In practical application, the DC/DC transducer that boosts must can be under multiple different loads condition equal operate as normal, and when the different loads transient state is switched, also to keep fixing output voltage basically.Load response is meant that the operating state when converter switches to another load rapidly when (as switching to heavy duty from underloading) from some loads, the amplitude of variation of output voltage V out and stabilized speed.Because we need constant output voltage V out, therefore when load was switched fast, the amplitude of variation of output voltage V out was more little, and stabilized speed is fast more, and performance is good more.
The change curve sketch map of each circuit parameter when Fig. 2 shows the DC/DC transducer that boosts among Fig. 1 and switches to heavy duty by underload.Please referring to shown in Figure 2, (A) stage among the figure is the underload stage, and (B) stage among the figure is the response phase when just having switched to heavy duty.In (A) stage, Iout=1mA, the expression load is very light, and output voltage V out is constant, and feedback voltage Vfb is constant, and error amplification signal EAO is near 0 value.At (B) during the stage, load switches to heavily on the lenient side, and promptly Iout jumps to the 400mA from 1mA; Cause that output voltage V out descends at once; Feedback voltage Vfb also descends simultaneously thereupon and causes error amplification signal EAO to begin to rise, because EAO has connected building-out capacitor, makes EAO rise slowly.In addition; In the prior art, the high certain amplitude of ratio no-voltage that the valley point voltage of triangular wave Ramp is provided with usually is such as 0.5V or 1V; The valley point voltage of Ramp among Fig. 1 is 1V, and the PWM comparator only just can produce the pulse-width signal of effective duty ratio more than valley point voltage like this.Therefore; Rise at error amplification signal EAO before the valley of triangular wave Ramp signal, the power switch pipe MN1 of system still can only be operated in minimum ON time, and the energy that is transferred to load just can not satisfy the requirement of load at all; Thereby output voltage V out can continue to descend; Be raised to enough height up to EAO, produce the pulse-width signal of suitable duty ratio, output voltage V out just begins to transfer rising to from decline.
The usual method of improving load response in the prior art is: the closed loop characteristic that the first, improves whole system; Because the DC/DC transducer that boosts is a degeneration factor, thereby the amplitude of variation of the bandwidth and the loop response speed that improve loop output voltage when all helping reducing load response; The second, increase the appearance value of output capacitance Cout, also help to improve load response.But above-mentioned two kinds of methods all have its limitation: the response speed and the bandwidth that at first merely improve loop bring difficulty can for the frequency compensation of feedback control loop, make feedback control loop unstable; Secondly, increase the compensation that output capacitance also can influence feedback control loop, and the electric capacity of Da Rong value has huger volume and the cost of Geng Gao.
It should be noted that; Be that example has been introduced ubiquitous load response problem in the power-switching circuit with the DC/DC change-over circuit that boosts only, other power-switching circuits that include pulse-width modulation comparator and error amplifier equally also have such load response problem here.
Therefore being necessary to propose a kind of improved technical scheme overcomes the problems referred to above.
[summary of the invention]
One of the object of the invention is to provide a kind of error amplifier, and its output is through the error amplification signal of clamper.
Two of the object of the invention is to provide a kind of power supply changeover device, and it has the load response of improvement.
According to an aspect of the present invention, this law is bright to provide a kind of error amplifier, and it comprises error amplifying circuit and output regulation circuit, wherein
Said error amplifying circuit is used for that two input voltages are carried out error and amplifies to obtain output voltage; It includes the output branch road that is connected between first power supply and the second source; Node on the said output branch road is as the output of the said output voltage of output, and wherein first power source voltage is lower than second source; With
Said output regulation circuit comprises first comparator, is connected on first switch between the said output and first power supply; Wherein said first comparator is used for the said output voltage and first reference voltage are compared; Said output voltage during less than said first reference voltage output break off control signal and remove to break off said first switch, said output voltage during more than or equal to said first reference voltage output conducting control signal remove said first switch of conducting.
Further; Said output regulation circuit also includes second comparator and is connected on the second switch between said output and the second source; Wherein second comparator is used for the said output voltage and second reference voltage are compared; Said output voltage greater than second reference voltage time output break off control signal and remove to break off said second switch; Output conducting control signal is removed the said second switch of conducting when said output voltage is less than or equal to said second reference voltage, and wherein said first reference voltage is less than said second reference voltage.
According to an aspect of the present invention, this law is bright to provide another kind of error amplifier, and it comprises error amplifying circuit and output regulation circuit, wherein
Said error amplifying circuit is used for that two input voltages are carried out error and amplifies to obtain output voltage; It includes the output branch road that is connected between first power supply and the second source; Node on the said output branch road is as the output of the said output voltage of output, and wherein first power source voltage is lower than second source; With
Output regulation circuit comprises decision circuitry, selector, comparator, is connected on first switch between the said output and first power supply and is connected on the second switch between said output and the second source; First input of wherein said selector connects first reference voltage; Second input connects second reference voltage; First input of said comparator connects said output voltage, and second input connects the output of said selector
Said decision circuitry is used to judge whether pulse-width signal is minimum duty cycle and maximum duty cycle; And control said selector during for maximum duty cycle at pulse-width signal and select second reference voltage for its output or control said selector at pulse-width signal during for minimum duty cycle and select first reference voltage to be its output
First input at comparator is broken off said second switch during for maximum duty cycle greater than second input and pulse-width signal; First input at comparator is broken off said first switch less than second input and pulse-width signal during for minimum duty cycle, and wherein said first reference voltage is less than said second reference voltage.
Further,, pulse-width signal starts said comparator when being maximum duty cycle or minimum duty cycle.
Further, said output regulation circuit also comprise with the door and NAND gate,
The said output that is connected said comparator with an input of door; Whether the expression pulse-width signal of another input connection judgment circuit is the output of maximum duty cycle; Said output with door is connected the control end of said second switch; The output of said comparator is through inserting an input of said NAND gate after the anti-phase; Whether the expression pulse-width signal of another input connection judgment circuit of said NAND gate is the output of minimum duty cycle, and the output of said NAND gate connects the control end of said first switch.
Further, first switch and second switch are MOS transistor.
In accordance with a further aspect of the present invention, this law is bright to provide a kind of power supply changeover device, and the output circuit that it includes power switch is used for turn-offing under the control input voltage being modulated to an output voltage in the conducting of power switch; Voltage feedback circuit is used for sampling and outputting voltage and obtains a feedback voltage; Can error amplification signal be carried out the error amplifier of clamper, be used for reference voltage and feedback voltage are carried out the error amplification to obtain the error amplifying voltage; The pulse-width modulation comparator is used for error amplifying voltage and triangular signal are compared to generate pulse-width signal, and said module modulation signal is used for controlling the conducting and the shutoff of said power switch.
Compared with prior art; Through output regulation circuit the output voltage of error amplifier is carried out clamper in the present invention; Make the output voltage of error amplifier to be in the preset range in the short period of time, and then can improve the load response of power supply changeover device.
[description of drawings]
In order to be illustrated more clearly in the technical scheme of the embodiment of the invention; The accompanying drawing of required use is done to introduce simply in will describing embodiment below; Obviously, the accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work property, can also obtain other accompanying drawing according to these accompanying drawings.Wherein:
Fig. 1 is a kind of system block diagram of the DC/DC transducer that boosts;
The change curve sketch map of each circuit parameter when Fig. 2 becomes heavy duty for the DC/DC transducer that boosts among Fig. 1 by underloading;
Fig. 3 is the circuit diagram of error amplifier in first embodiment among the present invention;
Fig. 4 is the error amplifier circuit diagram in a second embodiment among the present invention;
Fig. 5 is the circuit diagram of error amplifier in the 3rd embodiment among the present invention;
Fig. 6 is the circuit diagram of error amplifier in the 4th embodiment among the present invention;
Fig. 7 is the circuit diagram of error amplifier in the 5th embodiment among the present invention;
Fig. 8 is the circuit diagram of error amplifier in the 6th embodiment among the present invention; With
Fig. 9 is the change curve sketch map of each circuit parameter when having adopted the DC/DC transducer that boosts behind the error amplifier among the present invention to become heavy duty by underloading.
[embodiment]
To combine the accompanying drawing in the embodiment of the invention below, the technical scheme in the embodiment of the invention will be carried out clear, intactly description.Obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, all other embodiment that those of ordinary skills are obtained under the situation that does not break away from the present invention's essence and spirit belong to the scope that the present invention is open and protect.
Different local " in one embodiment " that occur possibly not be to refer to same embodiment in this specification, neither with repel each other separate of other embodiment or embodiment optionally.In addition, in the order of flow chart or diagram module, the sequence number and revocable that perhaps is used for describing one or more embodiment of the present invention refers to any specific order, also is not construed as limiting the invention.
In order to improve the load response of the DC/DC transducer that boosts; Need carry out clamper to the error amplification signal EAO of error amplifier output in the present invention; So that error amplification signal EAO can get in the amplitude range of triangular signal Ramp fast; This also just can accelerate the speed of load response, also can reduce the amplitude of variation of output voltage V out simultaneously.Therefore; The present invention also proposes the DC/DC transducer 100 that boosts as shown in Figure 1; Concrete structure sees also the associated description of background technology to the DC/DC transducer 100 that boosts; Difference from prior art is, has increased the output regulation circuit that the error amplification signal EAO of its output is carried out clamper in the error amplifier among the present invention.
Fig. 3 is the circuit diagram of error amplifier in first embodiment 300 among the present invention, and said error amplifier 300 can be as the error amplifier 130 in the DC/DC transducer 100 that boosts shown in Fig. 1, with the boost load response of DC/DC transducer of improvement.See also shown in Figure 3ly, said error amplifier 300 has normal phase input end INPUT1, inverting input INPUT2 and output EAO, and it comprises error amplifying circuit and output regulation circuit 310.
Said error amplifying circuit is used for the input signal INPUT1 of two inputs and INPUT2 are carried out the error amplification to obtain error amplification signal EAO at output, and it can be any one existing error amplifier.For the ease of understanding, only schematically show an output branch road from power vd D GND of error amplifying circuit among Fig. 3 to ground, a node on the said output branch road is as the output EAO of error amplifier 300.Said output regulation circuit 310 comprises switching transistor K31 and comparator C MP31; Said switching transistor K31 is series between output EAO and the ground GND; The input of said comparator C MP31 connects a reference voltage V 31; Another input connects output EAO, and the output of said comparator C MP31 is connected to the control end of said switching transistor K31.
It should be noted that between said switching transistor K31 and power vd D and circuit that said switching transistor K31 and ground dot respectively between the GND in possibly also comprise other element, like transistor etc., just be not described in detail here.
When the error amplification signal on output EAO is greater than or equal to said reference voltage V 31; Said comparator C MP31 controls said switching transistor K31 conducting; The output branch road of error amplifying circuit is also as operate as normal in the past; When the error amplification signal on output EAO is lower than said reference voltage V 31; Said comparator C MP31 controls said switching transistor K31 and turn-offs, and has so just closed the downward path of output EAO, thereby makes the error amplification signal of voltage rising on output EAO on the output EAO be greater than or equal to said reference voltage V 31.Like this, said output regulation circuit 310 just can with the error amplification signal EAO clamper of error amplifying circuit output reference voltage V 31 or more than.
When said error amplifier 300 is applied in the DC/DC transducer 100 that boosts shown in Fig. 1; Can reference voltage V 31 be set to the valley point voltage of triangular wave Ramp; The error amplification signal EAO of said like this error amplifier 300 outputs with regard to clamper valley point voltage or more than, thereby improve the load response of the DC/DC transducer that boosts.The change curve sketch map of each circuit parameter when having adopted the DC/DC transducer that boosts behind the error amplifier 300 among the present invention to become heavy duty by underloading can be with reference to shown in Figure 9.See also Fig. 9, (the A ') stage among the figure is the underload stage, (A ') stage; Iout=1mA, the expression load is very light, and output voltage V out is constant; Feedback voltage Vfb is constant; Error amplification signal EAO is clamped at through said error amplifier 300 near the valley of Ramp, switches on the lenient side heavily with back loading, and promptly Iout jumps to the 400mA from 1mA; Cause that output voltage V out descends at once; Feedback voltage Vfb also descends simultaneously thereupon and causes error amplification signal EAO to begin to rise, and error amplification signal EAO need not pass through the B stage among Fig. 2 and the amplitude range that directly just can get into triangular wave Ramp, has dwindled the unnecessary stroke of load response time error amplifying signal EAO so widely.
Fig. 4 is the circuit diagram of error amplifier in second embodiment 400 among the present invention; Said error amplifier 400 can serve as the error amplifier 130 in the DC/DC transducer 100 that boosts shown in Fig. 1, with the boost load response of DC/DC transducer of improvement.See also shown in Figure 4ly, similar with error amplifier 300, said error amplifier 400 also comprises error amplifying circuit and output regulation circuit 410, and error amplifying circuit can with Fig. 3 in identical, repeat no more here.
Said output regulation circuit 410 comprises the first switching transistor K41, second switch transistor K42, the first comparator C MP41 and the second comparator C MP42.The first switching transistor K41 is series between output EAO and the ground GND; The input of the first comparator C MP41 connects first reference voltage V 41; Another input connects the output EAO of error amplifying circuit, and its output is connected to the control end of the first switching transistor K41.Second switch transistor K42 is series between output EAO and the power vd D; The input of the second comparator C MP42 connects second reference voltage V 42; Another input connects the output EAO of error amplifying circuit; Its output is connected to the control end of second switch transistor K42, and wherein first reference voltage V 41 is lower than second reference voltage V 42.
It should be noted that; With similar among Fig. 3; Between said second switch transistor K42 and power vd D and in the circuit that dots between the GND of the said first switching transistor K41 and ground, possibly also comprise other element,, also be not described in detail here like transistor etc.
When the error amplification signal on output EAO is greater than or equal to first reference voltage V 41; Said comparator C MP41 controls the said first switching transistor K41 conducting; When the error amplification signal on output EAO is lower than said first reference voltage V 41; Said comparator C MP41 controls the said first switching transistor K41 and turn-offs; So just close the downward path of output EAO, thereby made the error amplification signal of voltage rising on output EAO on the output EAO be greater than or equal to said reference voltage V 41.When the error amplification signal on output EAO is less than or equal to said second reference voltage V 42; Said comparator C MP42 controls said second switch transistor K42 conducting; When the error amplification signal on output EAO is higher than said second reference voltage V 42; Said comparator C MP42 controls said second switch transistor K42 and turn-offs; So just close the path that output EAO makes progress, thereby made the error amplification signal of voltage reduction on output EAO on the output EAO be less than or equal to said second reference voltage V 42.Like this, said output regulation circuit 410 just can with error amplifying circuit in the error amplification signal clamper of output EAO output between second reference voltage V 42 and first reference voltage V 41.
By on can know; Error amplifier 400 shown in Fig. 4 is with the difference of the error amplifier 300 shown in Fig. 3: said error amplifier 400 has increased the second switch transistor K42 and the second comparator C MP42; Thereby can guarantee that error amplification signal is unlikely to too high, so just can be between first reference voltage V 41 and second reference voltage V 42 with the error amplification signal clamper of output EAO output.
When said error amplifier 400 is applied in the DC/DC transducer 100 that boosts shown in Fig. 1; Can first reference voltage V 41 be set to the valley point voltage of triangular wave Ramp; Second reference voltage V 42 is set to the crest voltage of triangular wave Ramp; The error amplification signal EAO of said like this error amplifier 400 outputs is clamped between valley point voltage and the crest voltage, thereby can further improve the load response of the DC/DC transducer that boosts.The change curve sketch map of each circuit parameter when having adopted the DC/DC transducer that boosts of error amplifier shown in Figure 4 to become heavy duty by underloading can be with reference to shown in Figure 9.
Fig. 5 is the circuit diagram of error amplifier in the 3rd embodiment 500 among the present invention; Said error amplifier 500 can be as in the error amplifier 130 in the DC/DC transducer 100 that boosts shown in Fig. 1, with the boost load response of DC/DC transducer of improvement.See also shown in Figure 5ly, similar with error amplifier 400 and error amplifier 300, said error amplifier 500 also comprises error amplifying circuit and output regulation circuit 510, and error amplifying circuit can with Fig. 4 and Fig. 3 in identical, repeat no more here.
Said output regulation circuit 510 comprise the first switching transistor K51, second switch transistor K52, decision circuitry D_LOGIC, selector SELECT, comparator C MP51, NAND gate NAND, with a door AND and a reverser NOT.The first switching transistor K51 is series between output EAO and the ground GND; Its control end links to each other with the output of NAND gate NAND; The input of NAND gate NAND is connected with the output of comparator C MP51 through reverser NOT, and another input is connected with the first output Min_on of decision circuitry D_LOGIC.Second switch transistor K52 is series between output EAO and the power vd D; Its control end is connected with output with door AND; Be connected with the output of comparator C MP51 with the input of door AND; Another input is connected with the second output Max_on of decision circuitry D_LOGIC; The 3rd output D_lim of decision circuitry D_LOGIC is connected to the control end of comparator C MP51, and the second output Max_on of decision circuitry D_LOGIC also is connected to the control end of selector SELECT simultaneously, and the input of selector SELECT is first reference voltage V 51; Another input is second reference voltage V 52, and wherein first reference voltage V 51 is lower than second reference voltage V 52.The input of said decision circuitry D_LOGIC is the pulse-width signal PWM output of PWM comparator or logic control circuit LOGIC output; Another input is the pulse-width signal of maximum duty cycle; Another input is the pulse-width signal of minimum duty cycle, and it is used to judge whether the actual duty cycle of pulse-width signal PWM is maximum duty cycle and minimum duty cycle.
It should be noted that; With similar among Fig. 3 and Fig. 4; Between said second switch transistor K52 and power vd D and in the circuit that dots respectively between the GND of the said first switching transistor K51 and ground, possibly also comprise other element,, also be not described in detail here like transistor etc.
When said decision circuitry D_LOGIC judges that pulse-width signal PWM is minimum duty cycle; The 3rd output signal D_lim of decision circuitry D_LOGIC starts comparator C MP51; Another output signal Max_on makes selector SELECT select first reference voltage V 51 to output to comparator C MP51; Comparator C MP51 compares with output voltage EAO first reference voltage V 51; When the error amplification signal on output EAO is greater than or equal to said first reference voltage V 51; The first output Min_on of the output of said comparator C MP51 and decision circuitry D_LOGIC controls the said first switching transistor K51 conducting through NAND gate NAND; Second of the output of said comparator C MP51 simultaneously and decision circuitry D_LOGIC exports Max_on through controlling said second switch transistor K52 conducting with door AND, and the output branch road of error amplifying circuit is also as operate as normal in the past; When the error amplification signal on output EAO is lower than said first reference voltage V 51; The first output Min_on of the output of said comparator C MP51 and decision circuitry D_LOGIC controls the said first switching transistor K51 through NAND gate NAND and turn-offs; Second of the output of said comparator C MP51 and decision circuitry D_LOGIC output Max_on is through controlling said second switch transistor K52 conducting with door AND simultaneously; So just close the downward path of output EAO, thereby made the error amplification signal of voltage rising on output EAO on the output EAO be greater than or equal to said second reference voltage V 51.
Said decision circuitry D_LOGIC judges when the actual duty cycle of pulse-width signal PWM is maximum duty cycle; The 3rd output signal D_lim of decision circuitry D_LOGIC starts comparator C MP51; The second output signal Max_on makes selector SELECT select second reference voltage V 52 to output to comparator C MP51; Comparator C MP51 compares with output voltage EAO second reference voltage V 52; When the error amplification signal on output EAO is less than or equal to said second reference voltage V 52; The second output Max_on of the output of said comparator C MP51 and decision circuitry D_LOGIC is through controlling said second switch transistor K52 conducting with door AND; First of the output of said comparator C MP51 simultaneously and decision circuitry D_LOGIC exports Min_on and controls the said first switching transistor K51 conducting through NAND gate NAND, and the output branch road of error amplifying circuit is also as operate as normal in the past; When the error amplification signal on output EAO is higher than said second reference voltage V 52; The second output Max_on of the output of said comparator C MP51 and decision circuitry D_LOGIC closes through controlling said second switch transistor K52 with door AND; First of the output of said comparator C MP51 and the decision circuitry D_LOGIC output Min_on controls the said first switching transistor K51 conducting through NAND gate NAND simultaneously; So just closed the path to output EAO, thereby made the error amplification signal of voltage reduction on output EAO on the output EAO be less than or equal to said second reference voltage V 52 from power vd D.Like this, said output regulation circuit 510 just can with error amplifying circuit in the error amplification signal clamper of output EAO output between second reference voltage V 52 and first reference voltage V 51.
When said error amplifier 500 is applied in the DC/DC transducer 100 that boosts shown in Fig. 1; Can first reference voltage V 51 be set to the valley point voltage of triangular wave Ramp; Second reference voltage V 52 is set to the crest voltage of triangular wave Ramp; The error amplification signal EAO of said like this error amplifier 500 outputs with regard to clamper between valley point voltage and crest voltage, thereby improve the load response of the DC/DC transducer that boosts.The change curve sketch map of each circuit parameter when having adopted the DC/DC transducer that boosts of error amplifier shown in Figure 5 to become heavy duty by underloading can be with reference to shown in Figure 9.
Fig. 6 is the circuit diagram of error amplifier 600 in the 4th embodiment among the present invention.Be with the difference of error amplifier among Fig. 3, Fig. 4 and Fig. 5: the detailed error amplifying circuit that shows error amplifier 600 620 among Fig. 6; And only summary shows the output regulation circuit 610 of error amplifier 600, and wherein output regulation circuit 610 can be any scheme shown in Fig. 4 and Fig. 5.
See also shown in Figure 6ly, said error amplifying circuit 620 comprises:
PMOS pipe MP11, PMOS pipe MP21, resistance R 3, NMOS pipe MN32 and NMOS pipe MN34; Concrete connected mode is: power vd D links to each other with the source electrode of PMOS pipe MP11; The drain electrode of PMOS pipe MP11 links to each other with the source electrode of PMOS pipe MP21, and the drain electrode of PMOS pipe MP21 links to each other with an end of resistance R 3, and the other end of resistance R 3 links to each other with the drain electrode of NMOS pipe MN32; The source electrode of NMOS pipe MN32 links to each other with the drain electrode of NMOS pipe MN34, the source ground GND of NMOS pipe MN34;
PMOS pipe MP24, NMOS pipe MN36, PMOS pipe MP23, NMOS pipe MN35, current source I, concrete connected mode is: the source electrode of PMOS pipe MP24 links to each other with current source I, and its drain electrode links to each other with the drain electrode of NMOS pipe MN36; Its grid connects an input FB; The source ground GND of NMOS pipe MN36, the source electrode of PMOS pipe MP23 links to each other with current source I, and its drain electrode links to each other with the drain electrode of NMOS pipe MN35; Its grid connects an input REF, the source ground GND of NMOS pipe MN35;
PMOS pipe MP12, PMOS pipe MP22, output EAO, NMOS pipe MN31 and NMOS pipe MN33; Concrete connected mode is: power vd D links to each other with the source electrode of PMOS pipe MP12; The drain electrode of PMOS pipe MP12 links to each other with the source electrode of PMOS pipe MP22; The drain electrode of PMOS pipe MP22 links to each other with the second switch transistor K62 of said output regulation circuit 610, is output EAO between the first switching transistor K61 and the second switch transistor K62, and the source electrode of the first switching transistor K61 links to each other with the drain electrode of NMOS pipe MN31; The source electrode of NMOS pipe MN31 links to each other with the drain electrode of NMOS pipe MN33, the source ground GND of NMOS pipe MN33;
Wherein, The grid of PMOS pipe MP11 links to each other with the grid of PMOS pipe MP12, and the grid of PMOS pipe MP11 also is connected on the node between PMOS pipe MP21 and the resistance R 3, and the grid of PMOS pipe MP21 links to each other with the grid of PMOS pipe MP22; The grid of PMOS pipe MP21 also is connected on the node between resistance R 3 and the NMOS pipe MN32; The grid of NMOS pipe MN32 links to each other with the grid of NMOS pipe MN31, and the grid of NMOS pipe MN34 links to each other with the grid of NMOS pipe MN36, and the drain electrode of NMOS pipe MN36 links to each other with its grid; The grid of NMOS pipe MN33 links to each other with the grid of NMOS pipe MN35, and the drain electrode of NMOS pipe MN35 links to each other with its grid.
Wherein the PMOS of error amplifying circuit 620 pipe MP12, PMOS pipe MP22, output EAO, NMOS pipe MN31 and this branch road of NMOS pipe MN33 are exactly the output branch road of error amplifying circuit 620.
Fig. 7 is the circuit diagram of error amplifier 700 in the 5th embodiment among the present invention.Be with the difference of error amplifier among Fig. 3, Fig. 4 and Fig. 5: the also detailed error amplifying circuit that shows error amplifier 700 720 among Fig. 7; And only summary shows the output regulation circuit 710 of error amplifier 700, and wherein output regulation circuit 710 can be any scheme shown in Fig. 4 and Fig. 5.
See also shown in Figure 7ly, said error amplifying circuit 720 comprises:
PMOS pipe MP73 and NMOS pipe MN74, concrete connected mode is: the source electrode of PMOS pipe MP73 links to each other with power vd D, and its drain electrode links to each other with the drain electrode of NMOS pipe MN74, the source ground GND of NMOS pipe MN74;
Current source I71, PMOS pipe MP71, NMOS pipe MN71, PMOS pipe MP72 and NMOS pipe MN72, concrete connected mode is: the source electrode of PMOS pipe MP71 links to each other with current source I71, and its drain electrode links to each other with the drain electrode of NMOS pipe MN71; Its grid links to each other with reverse input end FB; The source ground GND of NMOS pipe MN71, the source electrode of PMOS pipe MP72 links to each other with current source I71, and its drain electrode links to each other with the drain electrode of NMOS pipe MN72; Its grid links to each other with positive input REF, the source ground GND of NMOS pipe MN72;
PMOS pipe MP74, output EAO and NMOS pipe MN73; Concrete connected mode is: the source electrode of PMOS pipe MP74 is connected with power vd D; Its drain electrode links to each other with the second switch transistor K72 of said output regulation circuit 710; Output EAO is connected on the node between the second switch transistor K72 and the first switching transistor K71, and the first switching transistor K71 links to each other with the drain electrode of NMOS pipe MN73, the source ground GND of NMOS pipe MN73;
Wherein, the grid of PMOS pipe MP73 links to each other with the grid of its drain electrode with PMOS pipe MP74 respectively, and the grid of NMOS pipe MN74 links to each other with the grid of NMOS pipe MN71, and the grid of NMOS pipe MN72 links to each other with the grid of NMOS pipe MN73.
Wherein the PMOS of error amplifying circuit 720 pipe MP74, output EAO and this branch road of NMOS pipe MN73 are exactly the output branch road of error amplifying circuit 720.
Fig. 8 is the circuit diagram of error amplifier 800 in the 6th embodiment among the present invention.Be with the difference of error amplifier among Fig. 3, Fig. 4 and Fig. 5: the detailed error amplifying circuit that shows error amplifier 800 820 among Fig. 8; And only summary shows the output regulation circuit 810 of error amplifier 800, and wherein output regulation circuit 810 can be any scheme shown in Fig. 4 and Fig. 5.
See also shown in Figure 8ly, said error amplifying circuit 820 comprises:
PMOS pipe MP81 and NMOS pipe MN84, concrete connected mode is: the source electrode of PMOS pipe MP81 links to each other with power vd D, and its drain electrode links to each other with the drain electrode of NMOS pipe MN84, the source ground GND of NMOS pipe MN84;
PMOS pipe MP82, PMOS pipe MP83, NMOS pipe MN81, NMOS pipe MN82 and current source I81; Concrete connected mode is: the source electrode of PMOS pipe MP82 links to each other with power vd D, and its grid links to each other with its drain electrode, and its drain electrode links to each other with the drain electrode of NMOS pipe MN81; The source electrode of NMOS pipe MN81 links to each other with the end of current source I81; Its grid links to each other with reverse input end FB, the other end ground connection GND of current source I81, and the source electrode of PMOS pipe MP83 links to each other with power vd D; Its grid links to each other with its drain electrode; Its drain electrode links to each other with the drain electrode of NMOS pipe MN82, and the source electrode of NMOS pipe MN82 links to each other with the node that NMOS manages between MN81 and the current source I81, and its grid links to each other with positive input REF;
PMOS pipe MP84 and NMOS pipe MN85, concrete connected mode is: the source electrode of PMOS pipe links to each other with power vd D, and its drain electrode links to each other with the drain electrode of NMOS pipe, the source ground GND of NMOS pipe MN85, its grid links to each other with its drain electrode;
PMOS manages MP85, output EAO and current source I82; Concrete connected mode is: the source electrode of PMOS pipe MP85 is connected with power vd D; Its drain electrode links to each other with the second switch transistor K82 of said output regulation circuit 810; Its grid is connected on the node between PMOS pipe MP81 and the NMOS pipe MN84; Output EAO is connected on the node between the second switch transistor K82 and the first switching transistor K81, and the first switching transistor K81 links to each other with the end of current source I82, the other end ground connection GND of current source I82;
Wherein, the grid of PMOS pipe MP81 links to each other with the grid of PMOS pipe MP82, and the grid of PMOS pipe MP83 links to each other with the grid of PMOS pipe MP84, and the grid of NMOS pipe MN84 links to each other with the grid of NMOS pipe MN85.
Wherein the PMOS of error amplifying circuit 820 pipe MP85, output EAO and this branch road of NMOS pipe MN86 are exactly the output branch road of error amplifying circuit 820.
Remove error amplifying circuit 620, error amplifying circuit 720 and the error amplifying circuit 820 shown in above Fig. 6, Fig. 7 and Fig. 8; The error amplifying circuit that also has other connected modes; Concrete structure is that the those of ordinary skill in affiliated field can both be realized, just details no longer one by one here.
What need indicate is; Above-described error amplifier not only is used in the DC/DC transducer; According to same principle; It can also be applied in a lot of other the power supply changeover devices that comprise error amplifier and pulse-width modulation comparator, and it all can effectively improve the load response in the power supply changeover device through the clamper to error amplification signal.
In sum, the present invention compared with prior art carries out clamper to the voltage of error amplifier output, has improved the load response of transient state effectively.
It should be noted that; Though in background technology, combined Fig. 2 that the defective of the load response of the DC/DC of boosting transducer of the prior art is analyzed; But these are analyzed all is that the inventor draws through scrutinizing and repeatedly practising, is not the content that the those of ordinary skill in the said field is all known.In other words, the inventor has not only found and has improved load response and get scheme, has also found the reason of load response difference, and the both belongs to offering altogether that the inventor makes.
It is understandable that, concerning those of ordinary skills, can be equal to replacement or change according to technical scheme of the present invention and inventive concept thereof, and all these changes or replacement all should belong to the protection range of the appended claim of the present invention.
Claims (5)
1. error amplifier, it comprises error amplifying circuit and output regulation circuit, it is characterized in that:
Said error amplifying circuit is used for that two input voltages are carried out error and amplifies to obtain output voltage; It includes the output branch road that is connected between first power supply and the second source; Node on the said output branch road is as the output of the said output voltage of output, and wherein first power source voltage is lower than second source; With
Output regulation circuit comprises decision circuitry, selector, comparator, is connected on first switch between the said output and first power supply and is connected on the second switch between said output and the second source; First input of wherein said selector connects first reference voltage; Second input connects second reference voltage; First input of said comparator connects said output voltage, and second input connects the output of said selector
Said decision circuitry is used to judge whether pulse-width signal is minimum duty cycle and maximum duty cycle; And control said selector during for maximum duty cycle at pulse-width signal and select second reference voltage for its output or control said selector at pulse-width signal during for minimum duty cycle and select first reference voltage to be its output
First input at comparator is broken off said second switch during for maximum duty cycle greater than second input and pulse-width signal; First input at comparator is broken off said first switch less than second input and pulse-width signal during for minimum duty cycle, and wherein said first reference voltage is less than said second reference voltage.
2. error amplifier as claimed in claim 1 is characterized in that: when pulse-width signal is maximum duty cycle or minimum duty cycle, start said comparator.
3. error amplifier as claimed in claim 1 is characterized in that: said output regulation circuit also comprise with the door and NAND gate,
The said output that is connected said comparator with an input of door, whether the expression pulse-width signal of another input connection judgment circuit is the output of maximum duty cycle, said output with door is connected the control end of said second switch,
The output of said comparator is through inserting an input of said NAND gate after the anti-phase; Whether the expression pulse-width signal of another input connection judgment circuit of said NAND gate is the output of minimum duty cycle, and the output of said NAND gate connects the control end of said first switch.
4. error amplifier as claimed in claim 1 is characterized in that: first switch and second switch are MOS transistor.
5. power supply changeover device, it comprises:
Include the output circuit of power switch, be used for turn-offing under the control input voltage being modulated to an output voltage in the conducting of power switch;
Voltage feedback circuit is used for sampling and outputting voltage and obtains a feedback voltage;
Like claim 1,2 or 3 described error amplifiers, be used for reference voltage and feedback voltage are carried out the error amplification to obtain error amplification signal;
The pulse-width modulation comparator is used for error amplification signal and triangular signal are compared to generate pulse-width signal, and said pulse-width signal is used for controlling the conducting and the shutoff of said power switch.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101445216A CN101841240B (en) | 2010-04-12 | 2010-04-12 | Power supply converter and error amplifier |
| PCT/CN2010/074200 WO2011127688A1 (en) | 2010-04-12 | 2010-06-22 | Power-switching device and error amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101445216A CN101841240B (en) | 2010-04-12 | 2010-04-12 | Power supply converter and error amplifier |
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| CN101841240A CN101841240A (en) | 2010-09-22 |
| CN101841240B true CN101841240B (en) | 2012-08-29 |
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| CN2010101445216A Active CN101841240B (en) | 2010-04-12 | 2010-04-12 | Power supply converter and error amplifier |
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| WO (1) | WO2011127688A1 (en) |
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| CN102290970B (en) * | 2011-08-08 | 2013-10-02 | 无锡中星微电子有限公司 | Mode selecting and controlling circuit in voltage converter |
| CN105407601A (en) * | 2015-11-20 | 2016-03-16 | 芜湖锐芯电子科技有限公司 | Switch power supply PWM circuit |
| JP6892357B2 (en) * | 2017-08-31 | 2021-06-23 | エイブリック株式会社 | Switching regulator |
| US10317921B1 (en) * | 2018-04-13 | 2019-06-11 | Nxp Usa, Inc. | Effective clamping in power supplies |
| CN110502054B (en) * | 2019-08-29 | 2024-08-23 | 乳源东阳光机械有限公司 | Electroplating power supply circuit for realizing stable output of arbitrary voltage waveform |
| CN112714535B (en) * | 2019-10-25 | 2023-02-28 | 立锜科技股份有限公司 | Light emitting element driving device, and dimming control circuit and dimming control method thereof |
| CN111865314A (en) * | 2020-07-03 | 2020-10-30 | 同济大学 | Analog front end circuit of analog-to-digital converter |
| CN113364248B (en) * | 2021-06-15 | 2022-04-22 | 电子科技大学 | Output clamping circuit of DC-DC error amplifier |
| CN114374311B (en) * | 2022-03-21 | 2022-07-15 | 深圳市芯茂微电子有限公司 | Load power characterization method, system and processing module |
| CN114690832B (en) * | 2022-04-13 | 2023-11-14 | 中国电子科技集团公司第二十四研究所 | Current generating circuit, logarithmic amplifier and logarithmic slope stability improving method thereof |
| CN114884477B (en) * | 2022-07-08 | 2022-10-14 | 深圳芯能半导体技术有限公司 | Error amplifier circuit and converter |
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| CN1447506A (en) * | 2002-03-26 | 2003-10-08 | 精工爱普生株式会社 | Power circuit and PVVM circuit |
| CN1534853A (en) * | 2003-03-28 | 2004-10-06 | 圆创科技股份有限公司 | Error amplifier and direct current voltage conversion circuit and its method |
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| US7054170B2 (en) * | 2004-01-05 | 2006-05-30 | System General Corp. | Power-mode controlled power converter |
| JP2005269838A (en) * | 2004-03-22 | 2005-09-29 | Matsushita Electric Ind Co Ltd | Dc-dc converter |
| US7518348B1 (en) * | 2005-04-20 | 2009-04-14 | National Semiconductor Corporation | Adaptive error amplifier clamp circuit to improve transient response of DC/DC converter with current mode control |
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- 2010-06-22 WO PCT/CN2010/074200 patent/WO2011127688A1/en active Application Filing
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| US5747976A (en) * | 1996-03-26 | 1998-05-05 | Raytheon Company | Constant on-time architecture for switching regulators |
| CN1447506A (en) * | 2002-03-26 | 2003-10-08 | 精工爱普生株式会社 | Power circuit and PVVM circuit |
| CN1534853A (en) * | 2003-03-28 | 2004-10-06 | 圆创科技股份有限公司 | Error amplifier and direct current voltage conversion circuit and its method |
| CN101330261A (en) * | 2007-06-18 | 2008-12-24 | 天钰信息科技（上海）有限公司 | Switch power circuit |
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| WO2011127688A1 (en) | 2011-10-20 |
| CN101841240A (en) | 2010-09-22 |
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