CN104052275B - System and method for the two-stage buck-boost converter with fast transient response - Google Patents
System and method for the two-stage buck-boost converter with fast transient response Download PDFInfo
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Abstract
The two poles of the earth DC/DC bust-boost converter that various embodiments of the present invention provide single-phase and two-phase charge pump, control with rapid line and load transient, without considering loading condition.In certain embodiments of the invention, this controls desired output voltage by using error amplifier to realize, which controls multiple hysteresis comparators.Two-phase charge pump configuration eliminates ripple current and mode conversion, and increases efficiency and separating total current between two paths.Some embodiments allow which significantly reduces handoff loss and to further increase efficiency using low voltage semiconductor equipment.
Description
The cross reference of related application
This application claims entitled " the System and Methods for submitted by Rui Liu on March 14th, 2013
The U.S. Provisional Application sequence of Two-Stage Buck Boost Converters with Fast Transient Response "
No.61/785,831 priority are arranged, which is all incorporated into herein by reference.
Background technique
A. technical field
The present invention relates to power supplys, and turn more particularly, to the voltage boosting-reducing for fast transient response and seamless transitions
The system, apparatus and method of parallel operation.
B. background of invention
Many hyundai electronics consumer products are needed from can maintain stringent voltage tune when by high-speed transients
The power through adjusting and accurate DC voltage source of section.D/C voltage is often necessary to be gradually risen by boost converter or be turned by decompression
Parallel operation is gradually lowered to another D/C voltage.When output voltage is allowed in lower and higher electric pressing operation, D/C voltage
Usually handled by more complicated buck-boost or voltage boosting-reducing converter.In some existing applications, there is H bridge topology
Conventional buck-boost converter be used to adjust desired output voltage to the value more high or low than given input voltage.H bridge is opened up
It flutters in the power management IC for being used for example in smart phone and plate computer battery.However, they meet with common to these schemes
By big die-size, poor efficiency, transient response unsatisfactory and high output voltage ripple.What is desired is that system designer
For overcoming the tool of above-mentioned limitation.
Summary of the invention
Various embodiments of the present invention, which provide, realizes that the stringent of desired output voltage adjusts and be substantially equivalent to be depressured
The two poles of the earth DC/DC bust-boost converter of rapid line and the load transient control of the control of converter, without considering input electricity
Pressure is above desired output voltage again below desired output voltage.
In certain embodiments of the present invention, bust-boost converter using buck converter in the first stage come by
Input voltage is converted into the first output voltage equal to the approximately half of value of desired output voltage.Buck converter is coupled to
The first output voltage of buck converter is set to double the unregulated charge pump to realize desired output voltage.This method
It eliminates being depressured to for prior art design and boosts or boost to decompression mode converting characteristic.Traditional buck-boost is turned
The limitation for being zero on the right side of the loop bandwidth of parallel operation is completely eliminated.
In certain embodiments of the present invention, bust-boost converter is come using simple buck converter control program
By the output voltage of second level feedback to allow the first order compensate the second level load impedance first order controller, and the first order
It keeps decoupling from desired output voltage.In some embodiments, it is desirable to output voltage controlled by hysteresis comparator, the lag
Comparator generates the lag window controlled by error amplifier.
One specific embodiment utilizes two-phase charge pump configuration, wherein each phase is switched over 50% duty ratio, each
It is mutually operated with 50% duty ratio, and the two are mutually all when driving constant DC load current relative to being mutually out of phase 180 degree
Operation.As a result, the additional advantage of two-phase charge pump is, essentially without the line that can produce EMI noise due to lacking current impulse
Wave electric current or di/dt induction ringing voltage exist.Alternatively, only DC load current flows to output.In addition, because flowing through each
The electric current of leg is using the only half of the electric current of the embodiment of single-phase charge pump, and efficiency increases.
It is relatively low specified also by semiconductor equipment to be sized to compared with conventional high voltage MOSFET application
The ability of voltage, to increase efficiency for any given silicon die area.This allows to be substantially reduced and inside MOSFET
The relevant switching electric current dependent loss of capacitor.In certain embodiments, charge pump is configured to operate in bypass mode, with
Gross efficiency is further increased in the case of input voltage is lower than desired output voltage.
Certain feature and advantage of the invention are generally described herein；However, being wanted in view of attached drawing, specification and its right
It asks, will will be apparent to those skilled in the art in additional feature, advantage and embodiment proposed in this paper.It will be understood, therefore, that
The scope of the present invention is not limited in the specific embodiment disclosed in the summary of the invention.
Detailed description of the invention
The embodiment of the present invention will be referred to, example can be shown in the accompanying drawings.These attached drawings are intended to illustrative rather than limit
Property.Although the present invention is usually described in the background of these embodiments, it should be understood, however, that it be not intended to will be of the invention
Scope limitation is to these specific embodiments.
Fig. 1 shows prior art bust-boost converter circuit.
Fig. 2 shows the bust-boost converter systems of various embodiments according to the present invention.
Fig. 3 is the illustrative two-stage bust-boost converter including single-phase charge pump of various embodiments according to the present invention
Schematic diagram.
Fig. 4 is the illustrative two-stage bust-boost converter including two-phase charge pump of various embodiments according to the present invention
Schematic diagram.
Fig. 5 shows the exemplary current and voltage waveform of the voltage doubler in Fig. 4.
Fig. 6 be according to the present invention various embodiments for input voltage to be converted into using bust-boost converter
The flow chart of the illustrative process of output voltage.
Fig. 7 shows the example implementations of the bust-boost converter system in Fig. 2.
Specific embodiment
It will be apparent, however, that elaborating specific details in order to provide the understanding of the present invention.
However it will be apparent to one skilled in the art that the present invention can be carried out in the case where without these details.Those skilled in the art
It will be recognized that following the embodiment of the present invention can be executed in various ways and using various devices.Those skilled in the art
, it will also be appreciated that additional modification, application and embodiment are within its scope, such as the present invention can provide the additional necks of practicability
Domain.Therefore, following embodiments illustrate the particular embodiment of the present invention, and are intended to avoid making indigestibility of the present invention.
In the specification to " an embodiment " or " an embodiment " refer to means about the specific of embodiment description
Feature, structure, characteristic or function are included at least one embodiment of the present invention.The phrase " in one embodiment ", " in reality
Apply in example " etc. the appearance of different places in the description be not necessarily all referring to the same embodiment.
In addition, the connection between the parts or between method and step is not limited to the connection being directly realized by the accompanying drawings.Phase
Instead, without departing from present invention teach that in the case where, in the accompanying drawings shown in connection between the parts or between method and step can
It is modified or is changed by the way that intermediate member or method and step are added to it in another manner.In this document, term " boosting
Converter " includes any equipment that high output voltage can be generated from relatively low input voltage.
Fig. 1 shows prior art bust-boost converter circuit.Bust-boost converter circuit 100 includes voltage source
102, input capacitor CIN104, output capacitor COUT106, inductor L1108 and mosfet transistor Q1110, Q2112,
Q3114 and Q4116.Voltage source 102(is usually battery) by voltage VINIt is applied to input capacitor 104.Capacitor 104 couples
To the tandem compound of transistor Q1110 and Q2112.The drain electrode of transistor Q1110 and the source level of transistor Q2112 are in node
It is coupled to a terminal of inductor 108 at LX1130.The another terminal of inductor 108 is coupled to crystal at node LX2140
The drain electrode of pipe Q4116 and the source level of transistor Q3114.Output capacitor COUT106 are coupled in the string of transistor Q3114 and Q4116
Connection combination both ends.
Bust-boost converter circuit 100 is designed to according to input voltage VIN102 and output voltage VOUT120 pass
System, switches between two different operation modes (decompression mode and boost mode).In detail, when the input terminal of power supply 102
Input voltage VINWhen more than output voltage 120, circuit 100 is used as buck converter operation.At this stage, decompression conversion
Device is formed by transistor Q1110 and Q2112, inductor 108 and output capacitor 106.Buck converter mentions power supply 102
The input voltage V of confessionINIt is gradually lowered to lower than VINOutput voltage 120.In this mode, transistor Q4116 must be kept
Conducting, in order to provide from node LX2140 to output capacitor 106 power path.
On the contrary, working as input voltage VINIt is reduced to output voltage VOUTWhen under 120, circuit 100 is transformed in boost operations mould
It is operated under formula.In this state, booster circuit is by inductor 108, transistor Q3114 and Q4116 and output capacitor
106 form.Input voltage is gradually increased to higher output voltage V by booster circuitOUT120.Note that in this mode, it is brilliant
Body pipe Q1110 must be held on, to provide from node LX1130 to input power 102 path.
Way circuit 100 can replace between both of which, and to operate as single inductor step-down booster circuit, and handling can
To be higher or lower than VOUT120 input voltage VIN。
However, the one leg of the asymmetric topology of circuit 100, which generally remains, not to be conditioned in the design of most of H bridges.Example
Such as, buck stages may operate under fixed duty cycle, and only voltage-boosting stage is conditioned.Input voltage and output voltage each other too
In the case where, much relative complex control algolithm is necessarily used for being existed according to the relationship between input voltage and output voltage
It is converted between both operation modes.This is usually realized by continuously converting between these two modes, because of the two moulds
Formula itself is unable to adjust output voltage 120.
One major defect of circuit 100 includes: that H bridge topology is not able to satisfy very strict route and load transient response
It is required that especially introducing distinctive " right side zero " control problem of boost converter and causing phase margin and stability problem
Boost operation pattern in.Transient response as relative mistake as a result, the bandwidth of control loop (not shown) is limited, thus
Slow down way circuit response.
Due to the inherent complexity of subsidiary control circuit, the buck-boost topology in circuit 100 is also required to relatively large
Die-size area.In addition, circuit 100 is by inefficient and high output voltage ripple, especially in boost mode operation,
The electric current for wherein flowing through Q4116 is the pulsating current with the average value equal with the output value of electric current.Depending on input with it is defeated
The ratio between voltage 120 out, the peak value for exporting electric current can be more many times larger than the average value of electric current.In order to illustrate, in 50% duty ratio,
That is, when turn-on and turn-off period equal ratio, exporting the peak value of electric current will be twice of average DC current value.
Further drawback common to all prior art decompressions, boosting and buck-boost design is following truth: even if brilliant
Body pipe Q2112 is turned off, it must also stand maximum input voltage identical with transistor Q1110.Similarly, even if in crystalline substance
When body pipe Q4116 is turned off, it must also stand maximum boost output voltage identical with Q3114.In other words, transistor
Q2112 and especially Q3114 cannot be using as low side transistors and must be designed to high voltage installation.
Fig. 2 shows the bust-boost converter systems of various embodiments according to the present invention.Bust-boost converter system
200 include power supply 202, buck converter 204, voltage multiplier 206, buck controller 208, voltage multiplier controller 210,
Voltage error amplifier 212 and load 220.Power supply 202 is coupled to buck converter 204 to provide input voltage VIN230。
Buck converter 204 represents the buck stages of bust-boost converter.Buck converter 204, which is coupled into, receives input voltage VIN230
And convert thereof into the first output voltage V controlled by buck controller 208OUT1232.The output electricity of buck converter 204
Press VOUT1232 are input into voltage multiplier 206, to generate desired output voltage VOUT2234。
In this example, output voltage VOUT2234 are fed back in voltage error amplifier 212.Voltage error amplifier 212
It is coupled into and receives output signal VOUT2234 believe with the reference voltage that can be generated by such as reference voltage signal generator (not shown)
Number VREF236, and error voltage signal V is provided to buck controller 208ERR238.In one embodiment, voltage error amplifies
Device 212 is further coupled to buck controller 208.
Buck converter 204 is can be by input voltage VIN230 are converted into low value output voltage VOUT1232 any circuit.
Buck converter 204 includes inductance and capacity cell and switching element.Switching element can be implemented as semiconductor equipment, such as
MOSFET equipment.
In one embodiment, the output of buck converter 204 includes one or more for can sharing with voltage multiplier 206
A element.For example, one or more output capacitors of buck converter 204 can be used as the input capacitance of voltage multiplier 206
Device.Voltage multiplier 206 is arranged to that input voltage is made to double to be converted into comparing input voltage by charge redistribution
The output voltage of big desired multiplication constant.Voltage multiplier 206 can be any voltage multiplier known in the art, such as
Voltage doubler or voltage tripler and fractional charge pump.
In operation, buck converter 204 receives input voltage VIN230 and convert thereof into lower output voltage
VOUT1232.In one embodiment, VOUT1232 are designed to desired output voltage VOUT2234 it is approximately half of.In this example,
Voltage multiplier 206 is to make the received output voltage V at input terminalOUT1232 double to generate voltage VOUT2234 electricity
Press doubler circuit.As a result, bust-boost converter system 200 buck converter 204 and voltage multiplier 206 combination with
Bust-boost converter is formed, the output voltage below and above the voltage inputted by power supply 202 can be generated.
In one embodiment, voltage multiplier 206 operates in open loop, that is, voltage multiplier 206 itself is without adjusting
Section, this is convenient for simplified realization.This is possible, because right side is zero problem and transformation with difference in the prior art
Problem is all not present, as that will will be illustrated next.Alternatively, output voltage VOUT2234 are conditioned via buck controller 208,
Buck controller 208 is designed to control buck converter 204.
In detail, because voltage multiplier 206 does not ideally only include inductance component comprising capacitive element, voltage multiplication
Device 206 does not interfere closed loop design.As a result, the problem of right side is zero disappears, and the bandwidth characteristic of the closed loop design of system 200
(it is only determined by buck converter 204 now) is than much higher in comparable buck-boost system.In fact, bandwidth
It is in close proximity to the bandwidth of conventional buck converter.This allows the output electricity more relatively smaller than prior art buck-boost system
Sense and capacitor, and essentially result in and the transient response of bust-boost converter system 200 is turned with for conventional single stage decompression
The transient response of parallel operation is identical.
In addition, because the output of buck converter 204 is generally adjusted in the output voltage than voltage multiplier 206
VOUT2234 relatively lower electric pressing operations, therefore the output V of buck converter 204OUT1232 usually less than VOUT2234, so that
System 200 does not need to be switched to another operation mode from a kind of operation mode.This eliminate decompression mode and boost mode it
Between passes when all obstacles for being generated in the prior art due to caused by inherent mode conversion.
In a particular embodiment, voltage multiplier 206 is to make the first output voltage VOUT1232 double to generate voltage
VOUT2234 two-phase voltage doubler circuit.Two-phase voltage doubler circuit includes the operation of out-phase 180 degree to prevent pulsating current
And eliminate the first and second phase charge pump (not shown) of ripple current.
It should be understood that circuit block can be realized in one single or can be shared to one or more elements in system 200.?
A feasible implementation of the system as lag step down voltage redulator system is shown in Fig. 7.
Fig. 3 is the illustrative two-stage buck-boost conversion including single-phase charge pump according to various embodiments of the present invention
The schematic diagram of device.Bust-boost converter circuit 300 includes voltage source VIN302, inductor L316, capacitor C2 320, C3
322 and C1 350 and switching element Q1-Q4 330-336,310 Q9 and Q10 312.Inductor 316 is inductance storage member
Part, and capacitor 320,322,350 is capacitive storage element.Note that can be implemented as can be for example by control logic tune for capacitor
Save the parallel variable capacitor device group of scheduled capacitance.Capacitor C2 320 and C3 322, capacitor C1 350 are together with switching
Element Q1-Q4 330-336 is formed together charge pump 390, switching capacitor 350 during the charging stage with capacitor C3
322 is in parallel and in parallel with capacitor C2 320 during charge transfer phase.Although note that switching element Q3 in this example
334, Q4 336 and Q9 310 is illustrated as depletion type p-channel mosfet transistor and Q1 330, Q2 332 and Q10 312 are illustrated as
Depletion type n-channel mosfet transistor, however it would be recognized by those skilled in the art that any switching element can be opened by any other
Off and on closes arrangement realization.In this example, switching element Q1-Q4 330-336,310 Q9 and Q10 312 are via gate drivers
It is controlled in response to representing the difference signal (not shown) of the difference between input voltage 303 and output voltage 326.
Voltage source 302 can be to the tandem compound of transistor Q9 310 and Q10 312 and provide voltage VIN303 electricity
Pond.It is coupled to a terminal of inductor 316 in the drain electrode of node LX1 314, transistor Q9 310 and Q10 312.The two
Transistor is formed together step-down controller circuit together with inductor L316 and capacitor C3 322.Represent the output of buck converter
Capacitor C2 320 and C3322 and charge pump circuit 390 it is shared.Charge pump 390 is voltage multiplier circuit, in this example
It is voltage doubler circuit.
As shown in figure 3, capacitor C2 320 is coupled between output node 326 and node LX2 318, and capacitor C3
320 are coupled between node LX2 318 and ground potential 328.Transistor Q1 330 and Q2 332 is coupled in 320 liang of capacitor C2
End.Transistor Q3 334 and Q4 336 is coupled in 322 both ends capacitor C3.Capacitor C3 322 represents the input of charge pump 390
Capacitor, and the tandem compound of capacitor C2 320 and C3 322 formed charge pump 390 as defined relative to ground potential 328
Equivalent output capacitance device.Capacitor C1 350 be coupled in transistor Q2 332 and Q3 334 tandem compound both ends fly across electricity
Container.
In operation, turned by the decompression that transistor Q9 310, Q10 310, inductor L316 and capacitor C3 322 are formed
Converter circuit is operated as conventional buck converter, in the node for the output node for representing the buck converter formed in this way
The first output voltage is generated at LX2 318.The output of buck converter includes forming divider at the output of charge pump 390
Capacitor C2 320 and C3 322.Divider depends on voltage of the loading condition foundation at 322 both ends capacitor C3, capacitor
C3 322 is generally configured to approximately half of operation at the node OUT326 of charge pump 390 with the second output voltage.As a result, low
Voltage MOSFET can be used for voltage doubler.Such as, if it is desired to output voltage be up to 5V, it is specified that 2.5V Vds may be used
MOSFET.This reduces given RDS_ONDie-size and handoff loss related with the capacitor inside MOSFET.
In one embodiment, charge pump 390 makes its received voltage doubles at its input voltage node LX2318, with
Output voltage V is generated at output node OUT326OUT.With difference in the prior art, inductor 316 does not need to execute liter
Function is pressed, and therefore can be sized smaller than prior art buck-boost circuit, this subtracts convenient for apparent size
It is small.In this example, the voltage at node LX2 318 is not conditioned.However, because charge pump 390 is usually to output impedance
Change sensitive resistive element, in order to avoid fluctuation, such as when the input current of charge pump 390 increases, in node OUT326
The voltage at place reduces, and in one embodiment, the output impedance of charge pump 390 is via buck converter control circuit (not shown)
By compensating to realize that stringent output voltage is adjusted.In other words, the output of buck converter passes through compensation charge pump circuit 390
Output impedance and adjusted indirectly.
In one embodiment, closed feedback loop is used for output voltage VOUTFrom node OUT326 feedback to being depressured
Voltage error amplifier in converter control circuit.VOUTIt can be coupled to the negative terminal of voltage error amplifier, voltage error is put
The output of big device is then compared with fixed reference potential, so that control loop can be determined whether to increase or decrease VOUT, to adjust
Actual output voltage value VOUT.In this way, VOUTIt can automatically and continuously compared with fixed voltage and be compensated.For example, working as
VINWhen 303 decline, the voltage at node LX2 318 also declines and makes the V of charge pump 390OUTDecline.In response, control electricity
Road increases output voltage of the buck converter at node LX2 318.Because node LC2 318 is the input to charge pump 390,
The input voltage of increase will make charge pump 390 generate higher output voltage V at node OUT326OUT, thus by VOUTRestore
To desired value.Therefore buck converter controller is strictly controlled by input voltage transient phenomena and output current transients phenomenon
The deviation of caused output voltage.
In one embodiment, the voltage at node LX2 318 can be used for generating ramp voltage, together with comparator
(not shown) and error voltage amplifier are collectively used for realizing simple buck converter controller.In one embodiment,
Current sensing circuit (not shown) can be used for determining load current.The information is subsequently used as feedback signal, with control decompression control
Device.It would be recognized by those skilled in the art that more complicated control program, such as VCM can be used equally.
In one embodiment, as output voltage VOUT326 than input voltage VIN1303 it is relatively much lower when, circuit 300 with
The bypass mode of prior art buck converter is imitated to operate.In bypass mode, such as by the way that transistor Q1 330 is connected
With Q2 332 and turn off transistor Q3 334 and Q4 336 to disable charge pump 390 and inductor 316 is directly connected to output
Node 326, to close the charge pump 390 of circuit 300 to save energy.The ability operated in bypass mode further increases electricity
The gross efficiency on road 300.
Fig. 4 is the illustrative two-stage buck-boost conversion including two-phase charge pump according to various embodiments of the present invention
The schematic diagram of device.Circuit 400 includes voltage source VIN302, switching element Q9 310 and Q10 312, inductor L316, the first phase
Charge pump 390 and the second phase charge pump 494.First phase charge pump 390 is similar to the charge pump 390 in Fig. 3.Second phase charge pump
494 include transistor Q5-Q8 438-444 and flying capacitor C4 470.Component and its function in charge pump 390 and 494 are
Similar, and do not repeating here for simplicity purposes.
Charge pump 390 and 494 is operated in tandem so that received input voltage doubles at node LX2 318.?
In one embodiment, the first phase charge pump 390 and the second phase charge pump 494 are each with 50% duty cycle operation, pass through every
The electric current of a leg is the only half of the electric current of single-phase charge pump shown in Fig. 3.Which increase efficiency, and are not apparent from increase silicone tube
Core size.
In one embodiment, out-phase 180 degree is grasped relative to each other for the first phase charge pump 390 and the second phase charge pump 494
Make, the electric current for passing through node OUT326, LX2 318 and GND328 is DC electric current.As a result, one of circuit 400 is main excellent
Point is that have the pulsating current of peak value due to lacking, and is felt essentially without the ripple current or di/dt that can produce EMI noise
Ringing voltage is answered to exist.Alternatively, DC load current flows to load.
Fig. 5 shows the exemplary current and voltage waveform of the voltage doubler in Fig. 4.As shown in figure 5, in time t1
510, transistor Q2, Q4, Q5 and Q7 are turned off, and transistor Q1, Q3, Q6 and Q8 are held off.Flow through Q1, Q3, Q6 and Q8
Electric current and electric current I_C1 and I_C4 become zero 530 in t1 510.At this point, the voltage at the both ends transistor Q2, Q4, Q5 and Q7 is kept
It is 0 540, therefore, handoff loss does not occur.The loss uniquely obviously occurred is the grid in transistor Q1, Q3, Q6 and Q8
Capacitor discharge loss.
During cross-conduction loss mainly appears on MOSFET turn off process.Above description is closed as Q1, Q3, Q5 and Q7
It is kept when disconnected 550 t3 514.
(560) are connected in time t2512, transistor Q1, Q3, Q6 and Q8.Their drain-to-source tension discharge, and
The drain-to-source voltage of Q2, Q4, Q5 and Q7 increase.Drain-to-source voltage of the process in transistor Q2, Q4, Q5 and Q7 reaches
To output voltage half when terminate.At this moment, transistor Q1, Q3, Q5 and Q7 is fully on.
Capacitor C1 discharges into output, and capacitor C4 is charged during period [t2, t3] 512-514 by input.It removes
Capacitor C4 discharge into output and capacitor C1 by input charging other than, this description is kept during the period [t4, t5].It passes
It leads during loss appears in period [t2, t3] 512-514 and [t4, t5] 516-518.
Because capacitor C1 and C4 are alternately by energy during period [t2, t3] 512-514 and [t4, t5] 516-518
It is transported to output and stops conveying, output ripple electric current during switching transformation [t1, t2] 510-512 and [t3, t4] 514-516
It is essentially zero, so as to cause output ripple voltage very small under the conditions of all input voltages.
Fig. 6 is according to various embodiments of the present invention for being converted input voltage using bust-boost converter
At the flow chart of the illustrative process of output voltage.
When bust-boost converter receives input signal, start in step 602 conversion process.Input signal is applied
To the first order of bust-boost converter.The first order can be buck converter.
In step 604, the first order converts input signals into the first output signal.
In step 606, the first output signal is applied to voltage multiplier circuit, can be score voltage multiplier.
In step 608, the first output signal is converted into the second output signal by voltage multiplier circuit.
In step 610, the second output signal is fed back to the controller of the first order.
It would be recognized by those skilled in the art that less or additional step can merge with step illustrated herein, without inclined
From the scope of the present invention.Particular order is not implied that in flow chart or the arrangement that interior block is described herein.
Fig. 7 shows the bust-boost converter system in Fig. 2 as the lag decompression for being suitable for the application of two-stage buck-boost
The exemplary realization of adjuster.Lag step down voltage redulator system 700 includes power supply 702, respectively includes 714 and of gate buffer
716 transistor 704 and 706, inductor 710, capacitor 712,750, reference voltage 760, voltage multiplier 720, voltage miss
Poor amplifier 726, load 770, resistor 742-748, comparator 722,724 and latch 730.Transistor 704,706, grid
Buffer 714,716, inductor 710 and output capacitor 712 form buck converter, and it is defeated to receive to be coupled to power supply 702
Enter voltage VINAnd it is converted into intermediate voltage output VOUT1718.The voltage is input into voltage multiplier 720, generates the phase
Hope output voltage VOUT2740。
Output voltage VOUT2740 via compensation network ZF1746 are fed to the negative terminal of voltage error amplifier 726.Anode
Son is coupled to ground 788 via reference voltage 760.Compensation feedback network ZF2752 are coupling in the input of voltage error amplifier 726
Between output.Voltage error amplifier 726 generates the error electricity for the negative input terminal for being forwarded to the first hysteresis comparator 722
Press signal 728.The positive input terminal of first hysteresis comparator 722 is via resistor RT1744 and forward direction capacitor CT750 parallel connection
Ground 788 is coupled in combination.Note that with the difference in general single-stage, decompression capacitor CT750 are not directly connected to output electricity
Pressure.The input coupling of second hysteresis comparator 724 to the first hysteresis comparator 722 opposite polarity input.First and second
The output of hysteresis comparator 722,724 is input into the latch 730 for being coupled to gate buffer 714,716.
In operation, voltage error amplifier 726 compares the output of voltage multiplier 720 with reference voltage 760, with
Generate error voltage signal 728.Error voltage signal 728 arrives transistor 704,706 via the feedback of gate buffer 714,716,
To control output voltage 718.Compensation circuit including network 746,752 ensures the stable operation of voltage error amplifier 726,
To prevent for example undesirable oscillation.Compensation feedback network 746,752 may include resistor and capacitor (not shown).?
In one embodiment, comparator 722,724 is by allowing error voltage signal 728 compared with unequal two threshold values of value
Compared with the Delay control of Lai Shixian voltage multiplier 720, so that the crystal of the decompression when control bust-boost converter system 700
Error voltage signal 728 can be maintained in lag window when pipe Q1 704 and Q2 706.
In one embodiment, comparator 1 722 is for adjusting upper threshold value, and comparator 2 724 adjusts lower threshold value.Knot
Fruit, the width of window, that is, upper and lower bound is fixed by the interior design of comparator 1 722 and comparator 2 724.Via error electricity
Press signal 728 by based on output voltage 740 by window it is mobile the higher or lower position come automatic control lag window.
Signal 708 usually has pulsating volage waveform, has the peak value equal to input voltage 702.When signal 708 is by electricity
Hinder device RT1744 and capacitor CTWhen 750 parallel combination receives, which, which generates, allows comparator 722,724 by error voltage
Voltage ramp of the signal 728 compared with two threshold values.Position based on window, voltage ramp determine lag step down voltage redulator system
700 switching frequency and duty ratio.
Latch 730 by based on the output signal of comparator 1 722 and comparator 2 724 determine which transistor 704,
706 will be connected via gate buffer 714,716 at any given time.For example, when latch 730 output response in
When being converted to logically high by the signal of comparator 1 722, the conducting of transistor Q1 704 and the shutdown of transistor Q2 706, because
As indicated, buffer 716 is inverter buffer.On the contrary, when the signal of latch 730 return to low value when, Q1 704 shutdown and
Q2 706 is connected.In this way, latch 730 ensures from the received noise of the output of comparator 1 722 and comparator 2 724
Signal (such as shake) will not result in the decision of mistake.
It will be recognized that the example and embodiment of front are exemplary, and the purpose in order to be aware and understood, rather than limit
The scope of the present invention processed.It is intended that when reading specification and research attached drawing, its apparent to those skilled in the art all is set
It changes, enhance, is equivalent, combination and improvement are included within the scope of the disclosure.It is intended that claim includes falling in this hair
All such modifications, displacement and equivalents in bright true spirit and range.
Claims (19)
1. a kind of switching regulaor that input voltage is converted into output voltage, the switching regulaor include:
It is coupled to the first stage of switches of the first output voltage node, first stage of switches receives the first input voltage, by it
It is converted into being relatively lower than the first output voltage of first input voltage；
It is coupled to the second stage of switches of first output voltage node, second stage of switches receives first output voltage
And first output voltage is converted into the second output voltage in the second output voltage node, the second output voltage phase
To higher than first output voltage；
It forms the first Electricity storage device for being coupled to the divider of first output voltage node and the second charge storage is set
It is standby；And
First flying capacitor, first flying capacitor are in parallel with first Electricity storage device during the charging stage
Coupling, and during charge transfer phase with the second Electricity storage device parallel coupled.
2. switching regulaor according to claim 1, wherein second stage of switches includes being configured to out-phase relative to each other
The the first phase voltage multiplier and the second phase voltage multiplier of operation.
3. switching regulaor according to claim 1, wherein first Electricity storage device and second charge are deposited
It stores up equipment and forms divider, first Electricity storage device is used as the output capacitor of first stage of switches.
4. switching regulaor according to claim 1, wherein second stage of switches is voltage doubler, voltage tripler
One of with score voltage multiplier.
5. switching regulaor according to claim 1 further includes that second be coupled in second stage of switches flies across electricity
Container, first flying capacitor and second flying capacitor are alternately charged and discharged defeated to generate described second
Voltage out.
6. switching regulaor according to claim 1, wherein second stage of switches includes being configured to out-phase relative to each other
The the first phase voltage multiplier and the second phase voltage multiplier of 180 degree operation.
7. switching regulaor according to claim 6 further includes the multiple switchings for being coupled to first flying capacitor
Element.
8. switching regulaor according to claim 7, wherein one or more switching elements are responded by gate drivers
In difference signal come the mosfet transistor that controls.
9. switching regulaor according to claim 1 further includes the voltage multiplier for controlling second stage of switches
Controller.
10. a kind of method of Operation switch adjuster, which comprises
Input voltage is applied to the first order of the switching regulaor；
The input voltage is converted into the first output voltage；
Out-phase operates at least two voltage multipliers relative to each other；
First output voltage is applied to the second level including voltage multiplier of the switching regulaor；And
By by the first flying capacitor and the first capacitor device of the switching regulaor and the second capacitor alternately coupling in parallel
It closes and first output voltage is converted into the second output voltage.
11. according to the method described in claim 10, wherein second output voltage is higher than first output voltage.
12. according to the method described in claim 10, further including by first output voltage operation in the second output electricity
That presses is approximately half of.
13. according to the method described in claim 10, further including being applied to second output voltage to be configured to described in control
The controller of the first order.
14. according to the method described in claim 10, further including that voltage error signal is applied to buck converter controller.
15. according to the method for claim 14, further including compensating the voltage times via the buck converter controller
Increase the output impedance of device.
16. according to the method described in claim 10, further include make during the charging stage first order output capacitor and fly across
Capacitor parallel coupled.
17. a kind of switching regulaor system, comprising:
First stage of switches is coupled into and receives the first input voltage, and is converted into being relatively lower than first input voltage
The first output voltage；
Second stage of switches is coupled into and receives first output voltage, and is converted into being relatively higher than the second input voltage
The second output voltage；
First hysteresis comparator and the second hysteresis comparator define the corresponding upper threshold value of lag window and lower threshold value；And
Error amplifier is coupled in the feedback configuration between the second output voltage node and first stage of switches, described
Error amplifier generates error signal to adjust the position of the lag window, so that converter controller is based on the error signal
To control second output voltage；
It is coupled to the first Electricity storage device and the second Electricity storage device of first output voltage node；And
First flying capacitor, first flying capacitor are in parallel with first Electricity storage device during the charging stage
Coupling, and during charge transfer phase with the second Electricity storage device parallel coupled.
18. system according to claim 17 further includes the forward direction for being connected to first hysteresis comparator and ground potential
Capacitor.
19. system according to claim 17 further includes the electric current sense for generating the output signal for indicating load current
Slowdown monitoring circuit, the output signal are fed back to the error amplifier to control or generate the error signal.
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| US201361785831P | 2013-03-14 | 2013-03-14 | |
| US61/785,831 | 2013-03-14 | ||
| US13/858,740 US9136756B2 (en) | 2013-03-14 | 2013-04-08 | System and methods for two-stage buck boost converters with fast transient response |
| US13/858,740 | 2013-04-08 |
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| CN105226945B (en) * | 2015-10-16 | 2017-09-12 | 深圳宝砾微电子有限公司 | Boost chip |
| US9595871B1 (en) * | 2015-12-21 | 2017-03-14 | Texas Instruments Deutschland Gmbh | High efficiency inductive capacitive DC-DC converter |
| US10140916B2 (en) * | 2017-02-03 | 2018-11-27 | Dazzo Technology Corporation | Charge pump and operating method thereof |
| US11095222B2 (en) * | 2017-09-21 | 2021-08-17 | Mediatek Inc. | High efficiency converter |
| CN108183611B (en) * | 2017-12-26 | 2019-12-06 | 成都芯源系统有限公司 | control device and method of bidirectional switch circuit |
| US10992221B2 (en) * | 2018-04-09 | 2021-04-27 | Semiconductor Components Industries, Llc | Efficient buck-boost charge pump and method therefor |
| KR102382987B1 (en) * | 2020-11-12 | 2022-04-05 | 주식회사 실리콘마이터스 | Power supply circuit |
| CN112787504B (en) * | 2021-01-28 | 2022-08-23 | 维沃移动通信有限公司 | Charge pump step-down IC and electronic device |
| CN116191879A (en) * | 2023-01-04 | 2023-05-30 | 重庆平创半导体研究院有限责任公司 | Step-down power converter and control method thereof |
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