CN104052275A - System and Methods for Two-Stage Buck Boost Converters with Fast Transient Response - Google Patents
System and Methods for Two-Stage Buck Boost Converters with Fast Transient Response Download PDFInfo
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Abstract
Various embodiments of the invention provide for single and dual phase charge pump, two stage DC/DC buck-boost converters having fast line and load transient control irrespective of load conditions. In certain embodiments of the invention, this is accomplished by controlling a desired output voltage with an error amplifier that controls a plurality of hysteresis comparators. A dual phase charge pump architecture eliminates ripple currents and mode transitions and increases efficiency by splitting the total current between two paths. Certain embodiments allow to use low voltage semiconductor devices, which significantly reduces switching losses and further increases efficiency.
Description
The cross reference of related application
The application requires the name of being submitted on March 14th, 2013 by Rui Liu to be called the U.S. Provisional Application sequence No.61/785 of " System and Methods for Two-Stage Buck Boost Converters with Fast Transient Response ", 831 priority, this provisional application is all incorporated to herein by reference.
Background technology
a. technical field
The present invention relates to power supply, and more specifically, relate to system, equipment and method for the voltage boosting-reducing transducer of fast transient response and seamless conversion.
b. background of invention
A lot of hyundai electronics consumer products need to from can in the time being subject to high-speed transients, maintain strict voltage-regulation through regulating and the power in DC voltage source accurately.DC voltage usually must be raise gradually or is reduced to gradually another DC voltage by step-down controller by boost converter.In the time that output voltage must operate under lower and higher voltage, DC voltage is processed by more complicated buck-boost or voltage boosting-reducing transducer conventionally.In some existing application, there is the conventional bust-boost converter of H bridge topology for the output voltage of expectation is adjusted to the value more high or low than given input voltage.H bridge topology is for example used in the power management IC of smart phone and dull and stereotyped computer battery.But these schemes are common, they suffer large die-size, poor efficiency, transient response unsatisfactory and high output voltage ripple.Needed is that system designer is for overcoming the instrument of above-mentioned restriction.
Summary of the invention
Various embodiment of the present invention provides the rapid line of the control that realizes the strict adjusting of desired output voltage and be equivalent in fact step-down controller and the two poles of the earth DC/DC bust-boost converter of load transient control, and does not consider that input voltage is higher than desired output voltage or lower than desired output voltage.
In certain embodiments of the present invention, bust-boost converter uses the step-down controller in the first order that input voltage is converted to and has the first output voltage that equals the only about half of value of desired output voltage.Step-down controller is coupled to the unregulated charge pump that makes the first output voltage of step-down controller double the output voltage of realizing expectation.This method has been eliminated being depressured to of prior art design and is boosted or boost to decompression mode converting characteristic.The restriction that is zero for the right side of the loop bandwidth of traditional bust-boost converter has been completely eliminated.
In certain embodiments of the present invention, bust-boost converter feeds back to the output voltage of the second level by simple step-down controller control program the first order controller of the load impedance that allows the first order compensation second level, and the first order keeps the output voltage decoupling from expecting.In certain embodiments, the output voltage of expectation is by hysteresis comparator control, and this hysteresis comparator produces the lag window by error amplifier control.
A specific embodiment utilizes two-phase charge pump construction, wherein eachly switches with 50% duty ratio, eachly operate with 50% duty ratio, and all relative to each other out-phase 180 degree operations in the time driving constant DC load current of these two phases.As a result, owing to lacking current impulse, the additional advantage of two-phase charge pump is there is no in fact to produce ripple current or the di/dt induction ringing voltage of EMI noise.Alternatively, only have DC load current to flow to output.In addition,, because the electric current of each leg of flowing through is the only half that uses the electric current of the embodiment of single-phase charge pump, efficiency increases.
Compare with conventional high voltage MOSFET application, also by semiconductor equipment is manufactured to the ability of relatively low rated voltage according to size, carried out for any given silicon die area change efficiency.This allows obviously to reduce the switch current dependent loss relevant to electric capacity in MOSFET inside.In certain embodiments, charge pump is configured to operate in bypass mode, with when input voltage lower than desired output voltage time in the situation that further improve gross efficiency.
Some feature and advantage of the present invention have here been described conventionally; But, in view of accompanying drawing, specification and claim thereof, will be obvious to those skilled in the art at extra feature in this paper, advantage and embodiment.Therefore, should be understood that scope of the present invention is not limited by disclosed specific embodiment in this summary of the invention.
Brief description of the drawings
With reference to embodiments of the invention, its example can be shown in the drawings.These accompanying drawings are intended to illustrative and nonrestrictive.Although the present invention is described conventionally in the background of these embodiment, but should be understood that it is not intended to limit the scope of the invention to these specific embodiment.
Fig. 1 illustrates prior art bust-boost converter circuit.
Fig. 2 illustrates the bust-boost converter system according to various embodiments of the invention.
Fig. 3 is according to the schematic diagram of the illustrative two-stage bust-boost converter that comprises single-phase charge pump of various embodiments of the invention.
Fig. 4 is according to the schematic diagram of the illustrative two-stage bust-boost converter that comprises two-phase charge pump of various embodiments of the invention.
Fig. 5 illustrates exemplary current and the voltage waveform of the voltage doubler in Fig. 4.
Fig. 6 be according to various embodiments of the invention for input voltage being converted with bust-boost converter to the flow chart of the illustrative process of output voltage.
Fig. 7 illustrates the exemplary implementation of the bust-boost converter system in Fig. 2.
Embodiment
In the following description, for illustrative purposes, set forth specific details to the understanding of the present invention is provided.But it will be apparent to one skilled in the art that the present invention can be implemented in the situation that there is no these details.Those skilled in the art will recognize that, can also carry out following embodiments of the invention with various devices in every way.Those of skill in the art also will appreciate that, extra amendment, application and embodiment is all within the scope of it, as the present invention can provide the extra field of practicality.Therefore, following embodiment illustrates specific embodiment of the present invention, and is intended to avoid making indigestibility of the present invention.
In specification, mentioning of " embodiment " or " embodiment " meaned to special characteristic, structure, characteristic or the function described about this embodiment comprise at least one embodiment of the present invention.The appearance in the difference places in specification such as phrase " in one embodiment ", " in an embodiment " might not all refer to same embodiment.
In addition, be not limited in the connection between parts or between method step the connection directly realizing in the accompanying drawings.On the contrary, do not departing from the present invention's instruction in the situation that can be modified or change in other mode by adding intermediate member or method step to it in the connection between parts or between method step shown in the accompanying drawings.In presents, term " boost converter " comprises any equipment that can produce from relatively low input voltage high output voltage.
Fig. 1 illustrates prior art bust-boost converter circuit.Bust-boost converter circuit 100 comprises voltage source 102, input capacitor C
iN104, output capacitor C
oUT106, inductor L1108 and mosfet transistor Q1110, Q2112, Q3114 and Q4116.Normally battery of voltage source 102() by voltage V
iNbe applied to input capacitor 104.Capacitor 104 is coupled to the tandem compound of transistor Q1110 and Q2112.The source class of the drain electrode of transistor Q1110 and transistor Q2112 is coupled to a terminal of inductor 108 at node LX1130 place.The another terminal of inductor 108 is coupled to the drain electrode of transistor Q4116 and the source class of transistor Q3114 at node LX2140 place.Output capacitor C
oUT106 are coupling in the tandem compound two ends of transistor Q3114 and Q4116.
Bust-boost converter circuit 100 is designed to according to input voltage V
iN102 and output voltage V
oUT120 relation is switched between two kinds of different operator schemes (decompression mode and boost mode).At length, as the input voltage V of the input of power supply 102
iNwhile exceeding output voltage 120, circuit 100 operates as step-down controller.In this stage, step-down controller is formed by transistor Q1110 and Q2112, inductor 108 and output capacitor 106.The input voltage V that step-down controller provides power supply 102
iNbe reduced to gradually lower than V
iNoutput voltage 120.In this pattern, transistor Q4116 must keep conducting, to the power path from node LX2140 to output capacitor 106 is provided.
On the contrary, as input voltage V
iNbe reduced to output voltage V
oUTunder 120 time, circuit 100 transforms under boost operations pattern and operates.In this state, booster circuit is formed by inductor 108, transistor Q3114 and Q4116 and output capacitor 106.Input voltage is elevated to gradually higher output voltage V by booster circuit
oUT120.Note, in this pattern, transistor Q1110 must keep conducting, so that the path from node LX1130 to input power 102 to be provided.
Way circuit 100 can replace between two kinds of patterns, and using as single inductor buck-boost circuit operation, and process can be higher or lower than V
oUT120 input voltage V
iN.
But in most of H bridge designs, the common maintenance of one leg of the symmetry topology of circuit 100 is not conditioned.For example, buck stages may operate under fixed duty cycle, and only has voltage-boosting stage to be conditioned.In the situation that input voltage and output voltage approach very much each other, relative complex many control algolithms must be used for tying up between these two kinds of operator schemes and converting according to the pass between input voltage and output voltage.This is conventionally by converting and realize between these two kinds of patterns continuously, because these two patterns self all can not regulation output voltage 120.
A major defect of circuit 100 comprises: H bridge topology can not meet very strict circuit and load transient response requirement, particularly introduce distinctive " right side the is zero " control problem of boost converter and cause phase margin and the boost operations pattern of stability problem in.As the result of the transient response of relative mistake, the bandwidth of control loop (not shown) is limited, thereby slows down way circuit response.
Due to the inherent complexity of subsidiary control circuit, the buck-boost topology in circuit 100 also needs relatively large die-size area.In addition, circuit 100 suffers inefficient and high output voltage ripple, and particularly, in boost mode operation, the electric current of the Q4116 that wherein flows through is the pulsating current with the mean value equating with the value of output current.Depend on the ratio of inputting with output voltage 120, the peak value of output current can be than much larger times of the mean value of electric current.In order to illustrate, in 50% duty ratio, that is, the turn-on and turn-off period, the peak value of output current was by the twice that is average DC current value when equal ratio.
All prior art step-downs, boost and buck-boost to design another common shortcoming be following truth: even if transistor Q2112 is turned off, it also must stand the maximum input voltage identical with transistor Q1110.Similarly, even in the time that transistor Q4116 turn-offs, it also must stand the maximum identical with the Q3114 output voltage that boosts.In other words, transistor Q2112 and particularly Q3114 can not utilize as low side transistors and must be designed to high voltage installation.
Fig. 2 illustrates the bust-boost converter system according to various embodiments of the invention.Bust-boost converter system 200 comprises power supply 202, step-down controller 204, voltage multiplier 206, buck controller 208, voltage multiplier controller 210, voltage error amplifier 212 and load 220.Power supply 202 is coupled to step-down controller 204 so that input voltage V to be provided
iN230.Step-down controller 204 represents the buck stages of bust-boost converter.Step-down controller 204 is coupled into and receives input voltage V
iN230 and convert thereof into and be subject to the first output voltage V that buck controller 208 is controlled
oUT1232.The output voltage V of step-down controller 204
oUT1232 are imported into voltage multiplier 206, to produce the output voltage V of expectation
oUT2234.
In this example, output voltage V
oUT2234 are fed back in voltage error amplifier 212.Voltage error amplifier 212 is coupled into and receives output signal V
oUT2234 and the reference voltage signal V that can be produced by reference voltage signal generator (not shown) for example
rEF236, and provide error voltage signal V to buck controller 208
eRR238.In one embodiment, voltage error amplifier 212 is further coupled to buck controller 208.
Step-down controller 204 is can be by input voltage V
iN230 convert low value output voltage V to
oUT1any circuit of 232.Step-down controller 204 comprises inductance and capacity cell and switching device.Switching device can be implemented as semiconductor equipment, for example MOSFET equipment.
In one embodiment, the output of step-down controller 204 comprises the one or more elements that can share with voltage multiplier 206.For example, one or more output capacitors of step-down controller 204 can be used as the input capacitor of voltage multiplier 206.Voltage multiplier 206 is to be configured to make input voltage to double to be redistributed it is converted to than the output voltage of the multiplication constant of the large expectation of input voltage by electric charge.Voltage multiplier 206 can be any voltage multiplier known in the art, for example voltage doubler or voltage tripler and fractional charge pump.
In the time of operation, step-down controller 204 receives input voltage V
iN230 and convert thereof into lower output voltage V
oUT1232.In one embodiment, V
oUT1232 are designed to desired output voltage V
oUT2234 only about half of.In this example, voltage multiplier 206 is the output voltage V that make in the reception of input terminal place
oUT1232 double to produce voltage V
oUT2234 voltage doubler circuit.As a result, step-down controller 204 and the voltage multiplier 206 of bust-boost converter system 200 combine to form bust-boost converter, its can produce lower than with the output voltage of the voltage higher than being inputted by power supply 202.
In one embodiment, voltage multiplier 206 operates in open loop, that is, voltage multiplier 206 self is unregulated, and this is convenient to the realization of simplifying.This is possible, because different from the prior art, right side is that zero problem and transformation problem do not exist, as by next explanation.Alternatively, output voltage V
oUT2234 are conditioned via buck controller 208, and buck controller 208 is designed to controlled hypotension transducer 204.
At length, do not comprise inductance component because voltage multiplier 206 only comprises capacitive element ideally, voltage multiplier 206 does not disturb closed loop design.As a result, the problem that right side is zero has disappeared, and much higher than in comparable buck-boost system of the bandwidth characteristic of the closed loop design of system 200 (its now only determined by step-down controller 204).In fact, bandwidth is in close proximity to the bandwidth of conventional step-down controller.This allows than prior art buck-boost system less outputting inductance and electric capacity relatively, and causes in fact for the transient response of bust-boost converter system 200 with identical for the transient response of conventional single-stage buck transducer.
In addition, because the output of step-down controller 204 is generally conditioned with than the output voltage V of voltage multiplier 206
oUT2under 234 relative lower voltages, operate the therefore output V of step-down controller 204
oUT1232 are usually less than V
oUT2234, make system 200 need to not be switched to another operator scheme from a kind of operator scheme.This has eliminated while operation back and forth between decompression mode and boost mode due to interior all obstacles that produce in the prior art that cause in mode conversion.
In a particular embodiment, voltage multiplier 206 is to make the first output voltage V
oUT1232 double to produce voltage V
oUT2234 two-phase voltage doubler circuit.Two-phase voltage doubler circuit comprises that the operation of out-phase 180 degree is to prevent pulsating current and to eliminate the first and second phase charge pump (not shown) of ripple current.
Should be understood that one or more elements in system 200 can be realized in individual equipment maybe can share circuit block.Figure 7 illustrates the feasible implementation of system as hysteresis step down voltage redulator system.
Fig. 3 is the schematic diagram of the illustrative two-stage bust-boost converter that comprises single-phase charge pump according to various embodiments of the present invention.Bust-boost converter circuit 300 comprises voltage source V
iN302, inductor L316, capacitor C2 320, C3 322 and C1 350 and switching device Q1-Q4 330-336, Q9 310 and Q10 312.Inductor 316 is inductance memory elements, and capacitor the 320,322, the 350th, capacitance stores element.Note, capacitor can be implemented as the parallel variable capacitor device group that can be for example adjusted to predetermined capacitance by control logic.Capacitor C2 320 forms charge pump 390 with C3 322, capacitor C1 350 together with switching device Q1-Q4 330-336, and its switch capacitor 350 is in parallel and in parallel with capacitor C2 320 during charge transfer phase with capacitor C3 322 during the charging stage.Note, although switching device Q3 334, Q4 336 and Q9 310 are illustrated as depletion type p channel mosfet transistor and Q1 330, Q2 332 and Q10 312 and are illustrated as depletion type n channel mosfet transistor in this example, but those skilled in the art will recognize that, any switching device can be realized by any other switch or switch arrangement.In this example, switching device Q1-Q4 330-336, Q9 310 and Q10 312 control in response to the difference signal (not shown) that represents the difference between input voltage 303 and output voltage 326 via gate drivers.
Voltage source 302 can be to provide voltage V to the tandem compound of transistor Q9 310 and Q10 312
iN303 battery.At node LX1 314, the drain coupled of transistor Q9 310 and Q10 312 is to a terminal of inductor 316.These two transistors form step-down controller circuit together with inductor L316 and capacitor C3 322.Represent that the capacitor C2 320 of output of step-down controller and C3322 and charge pump circuit 390 share.Charge pump 390 is voltage multiplier circuits, and it is voltage doubler circuit in this example.
As shown in Figure 3, capacitor C2 320 is coupling between output node 326 and node LX2 318, and capacitor C3 320 is coupling between node LX2 318 and earth potential 328.Transistor Q1 330 and Q2 332 are coupling in capacitor C2 320 two ends.Transistor Q3 334 and Q4 336 are coupling in capacitor C3 322 two ends.Capacitor C3 322 represents the input capacitor of charge pump 390, and the tandem compound of capacitor C2 320 and C3 322 form charge pump 390 as the equivalent output capacitance device defining with respect to earth potential 328.Capacitor C1 350 is the striding capacitance devices that are coupling in the tandem compound two ends of transistor Q2 332 and Q3 334.
In the time of operation, the step-down controller circuit being formed by transistor Q9 310, Q10 310, inductor L316 and capacitor C3 322 operates as conventional step-down controller, to produce the first output voltage in node LX2 318 places of the output node of the step-down controller of formation like this in representative.The output of step-down controller is included in capacitor C2 320 and the C3 322 of the output formation voltage divider of charge pump 390.Voltage divider depends on that loading condition is based upon the voltage at capacitor C3 322 two ends, and the node OUT326 that capacitor C3 322 is generally designed at charge pump 390 sentences the only about half of operation of the second output voltage.As a result, low-voltage MOSFET can be used for voltage doubler.For example, if the output voltage of expecting is up to 5V, can use the specified MOSFET of 2.5V Vds.This reduces given R
dS_ONdie-size and the handoff loss relevant with electric capacity in MOSFET inside.
In one embodiment, the voltage that charge pump 390 makes it receive at its input voltage node LX2318 place doubles, to produce output voltage V at output node OUT326 place
oUT.Different from the prior art, inductor 316 does not need to carry out boost function, and therefore can be manufactured littlely than prior art buck-boost circuit according to size, and this is convenient to obvious size reduction.In this example, be not conditioned at the voltage at node LX2 318 places.But, because charge pump 390 is the resistive element to output impedance sensitive normally, for fear of fluctuation, for example, in the time that the input current of charge pump 390 increases, at the lower voltage at node OUT326 place, in one embodiment, the output impedance of charge pump 390 is compensated to realize strict output voltage via step-down controller control circuit (not shown) and is regulated.In other words, the output impedance of the output of step-down controller by compensation charge pump circuit 390 and by indirect regulation.
In one embodiment, closed feedback loop is used for output voltage V
oUTfeed back to the voltage error amplifier in step-down controller control circuit from node OUT326.V
oUTcan be coupled to the negative terminal of voltage error amplifier, the output of voltage error amplifier then with fixed reference potential comparison, make control loop can determine whether increase or reduce V
oUT, to regulate actual output voltage value V
oUT.By this way, V
oUTcan be automatically and continuously with fixed voltage relatively and compensated.For example, work as V
iN303 when decline, also declines and make the V of charge pump 390 at the voltage at node LX2 318 places
oUTdecline.As response, control circuit increases the output voltage of step-down controller at node LX2 318 places.Because node LC2 318 is the inputs to charge pump 390, the input voltage of increase will make charge pump 390 produce higher output voltage V at node OUT326 place
oUTthereby, by V
oUTreturn to desired value.Therefore step-down controller controller strictly controls the deviation of the output voltage being caused by input voltage transient phenomena and output current transient phenomena.
In one embodiment, can be used for producing ramp voltage at the voltage at node LX2 318 places, it can be used for realizing simple step-down controller controller together with comparator (not shown) and error voltage amplifier.In one embodiment, current sensing circuit (not shown) can be used for determining load current.This information is subsequently as feedback signal, with controlled hypotension controller.Those skilled in the art will recognize that, can use equally more complicated control program, for example VCM.
In one embodiment, work as output voltage V
oUT326 than input voltage V
iN1303 when relatively much lower, and circuit 300 operates with the bypass mode that imitates prior art step-down controller.In bypass mode, for example by turn-on transistor Q1 330 and Q2 332 and turn-off transistor Q3 334 and Q4 336 with forbidding charge pump 390 inductor 316 is directly connected to output node 326, carry out the charge pump 390 of shut-off circuit 300 to save energy.The ability operating in bypass mode further improves the gross efficiency of circuit 300.
Fig. 4 is the schematic diagram of the illustrative two-stage bust-boost converter that comprises two-phase charge pump according to various embodiments of the present invention.Circuit 400 comprises voltage source V
iN302, switching device Q9 310 and Q10 312, inductor L316, first-phase charge pump 390 and second-phase charge pump 494.First-phase charge pump 390 is similar to the charge pump 390 in Fig. 3.Second-phase charge pump 494 comprises transistor Q5-Q8 438-444 and striding capacitance device C4 470.Parts in charge pump 390 and 494 and function thereof are similarly, and are not repeating here for simplicity purposes.
Charge pump 390 and 494 operates in tandem so that the input voltage receiving at node LX2 318 places doubles.In one embodiment, first-phase charge pump 390 and second-phase charge pump 494 are each all with 50% duty ratio operation, and the electric current of each leg that makes to flow through is the only half of the electric current of the single-phase charge pump shown in Fig. 3.This has increased efficiency, and does not obviously increase silicon die size.
In one embodiment, first-phase charge pump 390 and second-phase charge pump 494 be the operation of out-phase 180 degree relative to each other, and the electric current of make to flow through node OUT326, LX2 318 and GND328 is DC electric current.As a result, a major advantage of circuit 400 is, because shortage has the pulsating current of peak value, there is no in fact to produce ripple current or the di/dt induction ringing voltage of EMI noise.Alternatively, DC load current flows to load.
Fig. 5 illustrates exemplary current and the voltage waveform of the voltage doubler in Fig. 4.As shown in Figure 5, at time t1 510, transistor Q2, Q4, Q5 and Q7 are turned off, and transistor Q1, Q3, Q6 and Q8 keep turn-offing.Flow through the electric current of Q1, Q3, Q6 and Q8 and electric current I _ C1 and I_C4 in t1 510 vanishing 530.Now, the voltage at transistor Q2, Q4, Q5 and Q7 two ends remains 0 540, therefore, does not occur handoff loss.The loss of unique obvious appearance is the gate capacitance discharge loss in transistor Q1, Q3, Q6 and Q8.
During cross-conduction loss mainly appears at MOSFET turn off process.Being described in the time that Q1, Q3, Q5 and Q7 turn-off 550 t3 514 above keeps.
At time t2512, transistor Q1, Q3, Q6 and Q8 conducting (560).Their drain-to-source voltage electric discharge, and the drain-to-source voltage of Q2, Q4, Q5 and Q7 increases.The half that this process reaches output voltage at the drain-to-source voltage of transistor Q2, Q4, Q5 and Q7 finishes.In this moment, the complete conducting of transistor Q1, Q3, Q5 and Q7.
Capacitor C1 discharges into output, and capacitor C4 is charged by input during time period [t2, t3] 512-514.Except capacitor C4 discharge into output and capacitor C1 by inputting charging, this is described in during the period [t4, t5] and keeps.During conduction loss appears at the period [t2, t3] 512-514 and [t4, t5] 516-518.
Because capacitor C1 and C4 are alternately at period [t2, t3] 512-514 and [t4, t5] during 516-518 by Energy transfer to output and switching conversion [t1, t2] 510-512 and [t3, t4] stop during 514-516 carrying, output ripple electric current is essentially zero, thereby causes very little output ripple voltage under all input voltage conditions.
Fig. 6 be according to various embodiments of the present invention for input voltage being converted with bust-boost converter to the flow chart of the illustrative process of output voltage.
In the time that bust-boost converter receives input signal, start in step 602 transfer process.Input signal is applied to the first order of bust-boost converter.The first order can be step-down controller.
In step 604, the first order converts input signal to first output signal.
In step 606, the first output signal is applied to voltage multiplier circuit, and it can be mark voltage multiplier.
In step 608, voltage multiplier circuit converts the first output signal to second output signal.
In step 610, the second output signal is fed back to the controller of the first order.
Those skilled in the art will recognize that, still less or extra step can merge with step shown in this article, and do not depart from scope of the present invention.The layout of the piece at flow chart or in describing herein does not imply particular order.
Fig. 7 illustrates that bust-boost converter system in Fig. 2 is as the exemplary realization of hysteresis step down voltage redulator that is suitable for the application of two-stage buck-boost.Hysteresis step down voltage redulator system 700 comprises power supply 702, the transistor 704 and 706 that comprises respectively grid buffer 714 and 716, inductor 710, capacitor 712,750, reference voltage 760, voltage multiplier 720, voltage error amplifier 726, load 770, resistor 742-748, comparator 722,724 and latch 730.Transistor 704,706, grid buffer 714,716, inductor 710 and output capacitor 712 form step-down controller, and it is coupled to power supply 702 to receive input voltage V
iNand convert it to intermediate voltage output V
oUT1718.This voltage is imported into voltage multiplier 720, and it produces desired output voltage V
oUT2740.
Output voltage V
oUT2740 via compensating network Z
f1746 are fed to the negative terminal of voltage error amplifier 726.Plus end is coupled to ground 788 via reference voltage 760.Compensation feedback network Z
f2752 are coupling between the input and output of voltage error amplifier 726.Voltage error amplifier 726 produces the error voltage signal 728 of the negative input terminal that is forwarded to the first hysteresis comparator 722.The positive input terminal of the first hysteresis comparator 722 is via resistor R
t1744 and forward direction capacitor C
t750 parallel combination is coupled to ground 788.Note different from general single-stage, decompression capacitor C
t750 are not directly connected to output voltage.The input of the opposite polarity of the first hysteresis comparator 722 is coupled in the input of the second hysteresis comparator 724.The output of the first and second hysteresis comparators 722,724 is imported into the latch 730 that is coupled to grid buffer 714,716.
In the time of operation, voltage error amplifier 726 is compared the output of voltage multiplier 720 with reference voltage 760, to produce error voltage signal 728.Error voltage signal 728 feeds back to transistor 704,706 via grid buffer 714,716, to control output voltage 718.The compensating circuit that comprises network 746,752 is guaranteed the stable operation of voltage error amplifier 726, thereby prevents for example undesirable vibration.Compensation feedback network 746,752 can comprise resistor and capacitor (not shown).In one embodiment, comparator 722,724 is by allowing error voltage signal 728 and unequal two threshold of value, realize the hysteresis control of voltage multiplier 720, transistor Q1 704 and the Q2 706 time error voltage signals 728 of the step-down of working as controlled hypotension-boosting converter system 700 can be maintained in lag window.
In one embodiment, comparator 1 722 is for regulating upper threshold value, and comparator 2 724 regulates lower threshold value.As a result, the width of window, that is, upper and lower bound is fixed by the indoor design of comparator 1 722 and comparator 2 724.Via error voltage signal 728 by based on output voltage 740 by window move higher or lower come the position of automatic control lag window.
Signal 708 has pulsating voltage waveform conventionally, and it has the peak value that equals input voltage 702.When signal 708 is by resistor R
t1744 and capacitor C
twhen 750 parallel combination receives, this combination results allows comparator 722,724 by the voltage ramp of error voltage signal 728 and two threshold.Based on the position of window, voltage ramp is determined switching frequency and the duty ratio of hysteresis step down voltage redulator system 700.
Latch 730 determines that by the output signal of device 1 722 and comparator 2 724 based on the comparison which transistor 704,706 will carry out conducting via grid buffer 714,716 in any given time.For example, when the output of latch 730 is in response to being converted to logic when high by the signal of comparator 1 722, transistor Q1 704 conductings and transistor Q2 706 turn-off, because as shown, buffer 716 is inverter buffers.On the contrary, in the time that the signal of latch 730 turns back to low value, Q1 704 turn-offs and Q2 706 conductings.By this way, latch 730 guarantees that the noise signal (for example shake) receiving from the output of comparator 1 722 and comparator 2 724 is by the decision that can not lead to errors.
To recognize, example above and embodiment are exemplary, and object in order to be aware and understand, instead of limit the scope of the invention.Be intended that in the time reading specification and research accompanying drawing, significantly its all displacements of those skilled in the art, enhancing, equivalence, combination and improvement are included within the scope of the invention.Therefore be intended that claim and comprise all such amendment, displacement and the equivalents that drop in true spirit of the present invention and scope.
Claims (20)
1. a switching regulaor that input voltage is converted to output voltage, described switching regulaor comprises:
Be coupled to the first stage of switches of the first output voltage node, described the first stage of switches receives the first input voltage, to convert thereof into the first output voltage lower than described the first input voltage relatively; And
Be coupled to the second stage of switches of described the first output voltage node, described the second stage of switches receives described the first output voltage and described the first output voltage is converted to the second output voltage that is relatively higher than the second input voltage.
2. switching regulaor according to claim 1, also comprises the first Electricity storage device that is coupled to described the first output voltage node, and described the first Electricity storage device is as the output capacitor of described the first stage of switches.
3. switching regulaor according to claim 1, also comprises the second Electricity storage device that is coupled to described the first Electricity storage device and the second output voltage node, and described the first Electricity storage device and described the second Electricity storage device form voltage.
4. switching regulaor according to claim 1, wherein said the second stage of switches is one of voltage doubler, voltage tripler and mark voltage multiplier.
5. switching regulaor according to claim 1, also comprises the second striding capacitance device being coupling in the second level, the first striding capacitance device and described the second striding capacitance device alternately by charging and discharging to produce described the second output voltage.
6. switching regulaor according to claim 1, wherein said the second stage of switches comprises the first-phase voltage multiplier and the second-phase voltage multiplier that are configured to out-phase 180 degree operations relative to each other.
7. switching regulaor according to claim 6, also comprise multiple switching devices of the first striding capacitance device that is coupled to the second level, described the first striding capacitance device during the charging stage with described the first Electricity storage device parallel coupled, and during charge transfer phase with described the second Electricity storage device parallel coupled.
8. switching regulaor according to claim 7, wherein one or more switching devices are mosfet transistors of being controlled in response to difference signal by gate drivers.
9. system according to claim 1, also comprises the voltage multiplier controller for controlling described the second stage of switches.
10. a method for console switch adjuster, described method comprises:
Input voltage is applied to the first order of switching regulaor;
Convert described input voltage to first output voltage;
Described the first output voltage is applied to voltage multiplier circuit; And
Convert described the first output voltage to second output voltage.
11. methods according to claim 10, wherein said the second output voltage is higher than described the first output voltage.
12. methods according to claim 10, also comprise described the first output voltage are operated in to the only about half of of described the second output voltage.
13. methods according to claim 10, wherein change described the first output voltage and also comprise and operate first-phase voltage multiplier and the second-phase voltage multiplier that out-phase 180 is spent relative to each other.
14. methods according to claim 10, also comprise described the second output voltage are applied to the controller that is configured to control the described first order.
15. methods according to claim 10, also comprise voltage error signal are applied to step-down controller controller.
16. methods according to claim 15, also comprise the output impedance via voltage multiplier described in described step-down controller controller compensation.
17. methods according to claim 10, make first order output capacitor and striding capacitance device parallel coupled during being also included in the charging stage.
18. 1 kinds of switching regulaor systems, comprising:
The first stage of switches, it is coupled into and receives the first input voltage, and converts it to relatively the first output voltage lower than described the first input voltage;
The second stage of switches, it is coupled into and receives described the first output voltage, and converts it to be relatively higher than the second input voltage the second output voltage;
The first hysteresis comparator and the second hysteresis comparator, its definition corresponding upper threshold value of lag window and lower threshold value; And
Error amplifier, it is coupling in the feedback configuration between the second output voltage node and described the first stage of switches, described error amplifier produces error signal to regulate the position of described lag window, makes converter controller control described the second output voltage based on described error signal.
19. systems according to claim 18, also comprise the forward direction capacitor being coupling between described the first hysteresis comparator and earth potential.
20. systems according to claim 18, also comprise the current sensing circuit for generation of the output signal of expression load current, and described output signal is fed back to described error amplifier and produces described error signal to control.
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| US201361785831P | 2013-03-14 | 2013-03-14 | |
| US61/785,831 | 2013-03-14 | ||
| US13/858,740 US9136756B2 (en) | 2013-03-14 | 2013-04-08 | System and methods for two-stage buck boost converters with fast transient response |
| US13/858,740 | 2013-04-08 |
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