CN101841239B - Boost DC/DC converter and logic control circuit thereof - Google Patents

Boost DC/DC converter and logic control circuit thereof Download PDF

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Publication number
CN101841239B
CN101841239B CN2010101445235A CN201010144523A CN101841239B CN 101841239 B CN101841239 B CN 101841239B CN 2010101445235 A CN2010101445235 A CN 2010101445235A CN 201010144523 A CN201010144523 A CN 201010144523A CN 101841239 B CN101841239 B CN 101841239B
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signal
pulse
control circuit
pin
duty cycle
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CN101841239A (en
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杨喆
董贤辉
王钊
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Wuxi Zhonggan Microelectronics Co Ltd
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Wuxi Vimicro Corp
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Priority to CN2010101445235A priority Critical patent/CN101841239B/en
Priority to PCT/CN2010/074148 priority patent/WO2011127685A1/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/017—Adjustment of width or dutycycle of pulses

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention discloses a logic control circuit applied for a boost DC/DC converter, which is used for adjusting the pulse width modulation signal in the boost DC/DC converter. The logic control circuit comprises a judgment circuit, a counting circuit and a control circuit, wherein the judgment circuit is used for judging whether the pulse width modulation signal reaches the maximum duty cycle or not; the counting circuit is used for counting the times of the pulse width modulation signal reaching the maximum duty cycle, and then sending out an adjustment signal if the times of the pulse width modulation signal continuously reaching the maximum duty cycle reach a preset value; and the control circuit is used for adjusting the pulse width modulation signal during a period into the minimum duty cycle or zero according to the adjustment signal. By adopting the logic control circuit of the invention, the boost DC/DC converter can be effectively softly started to avoid overshoot of output voltage and input current, and a normal working condition can be reached as soon as possible.

Description

DC/DC transducer and interior logic control circuit thereof boost
[technical field]
The DC/DC transducer field that the present invention relates to boost is particularly about effective soft start scheme of the DC/DC transducer that boosts.
[background technology]
Voltage boosting dc-direct current transducer (Boost DC/DC Converter) is a kind of common, widely used electric power management circuit.Fig. 1 shows a kind of circuit diagram of the DC/DC of boosting transducer.Please refer to shown in Figure 1ly, the said DC/DC of boosting transducer 100 includes the output module 120 that boosts, Voltage Feedback module 140 and control circuit module 160.
The said output module 120 that boosts comprises inductance L, diode D, nmos pass transistor MN1 and capacitor C out; One end of inductance L connects input voltage vin; The other end links to each other with the anode of diode D; The negative electrode of diode D links to each other with the end of capacitor C out, and the intermediate node voltage of diode D and capacitor C out is as output voltage V out, and the grid of said nmos pass transistor MN1 is as the pulse-width signal (PWM) of the control end reception control circuit module 160 of the output module that boosts; The drain electrode of said NMOS pipe MN1 links to each other with the intermediate node of inductance L and diode, and the source electrode of said NMOS pipe MN1 and the other end of capacitor C link to each other with ground.Said transistor MN1 is a power switch pipe, and when power switch pipe MN1 conducting, inductive current is with dI LThe speed of/dt=Vin/L is linear to be increased, and electric energy converts the magnetic energy stored in form in inductance L.At this moment, because diode D bears reverse voltage and is in cut-off state, load is discharged by output capacitance Cout provides energy; When power switch pipe MN1 breaks off, because inductive current can not suddenly change, the magnetic field among the coil L will change the polarity of voltage at L two ends, diode D forward conduction, and inductive current is with dI LLinear decline of the speed of/dt=(Vout-Vin)/L and power supply are given load and Cout power supply together, and this moment, the voltage of power supply was power supply Vin and inductive drop sum, had promptly played the effect of boosting.
Said voltage feedback circuit 140 comprises resistance R 1 and the R2 that is connected between output voltage and the ground, and said resistance R 1 has been formed a branch pressure voltage with R2, thereby the said output voltage V out that samples is to obtain feedback voltage Vfb.Said control circuit module 160 includes error amplifier EA, pulse-width modulation comparator PWM_CMP and logic control circuit LOGIC.Said error amplifier is used for reference voltage Vref and feedback voltage Vfb are carried out the error amplification with generated error amplifying voltage V EAOSaid pulse-width modulation comparator PWM_CMP is used for error amplifying voltage V EAOCompare to generate pulse-width signal PWM with triangular signal RAMP.Said logic control circuit is used for pulse-width signal PWM is carried out logic control; And go to control conducting and the shutoff of said power switch MN1 with the pulse-width signal NPWM after the logic control; Said logic control comprises control logics such as maximum duty cycle and minimum duty cycle are set; Maximum duty cycle can determine the maximum ON time of power switch MN1, and minimum duty cycle can determine the minimum ON time of power switch MN1.
After setting reference voltage Vref and output feedback resistance R1 and R2, system's loop will make output voltage reach set point through the pulse-width signal that error amplifier EA and PWM comparator produce certain duty ratio (Duty cycle):
Vout = Vref · R 1 + R 2 R 2 .
But in actual use, can occur surge current and output voltage overshoot during system start-up, therefore, soft starting circuit 180 is widely used in the various DC/DC transducers.Please with reference to shown in Figure 1; The current source Iref that said soft starting circuit 180 comprises capacitor C ss, charge to capacitor C ss and select circuit MUX; Said selection circuit MUX promptly starts end signal SS_finish when invalid in start-up course; Select the reference voltage Vref of capacitance voltage Vref_ss,, can help guidance system normally to start because capacitance voltage Vref_ss is linear increasing as error amplifier EA; Start to finish promptly to start end signal SS_finish when effective, the choice criteria reference voltage Vref ' as the reference voltage Vref of error amplifier EA.
Yet even adopted said soft starting circuit 180, still can there be some problems in the DC/DC of boosting change-over circuit of the prior art when starting.The characteristics of DC/DC transducer are inductive current IL and not all flow to output owing to boost; When being the charging of power switch pipe MN1 conducting inductive current; Output voltage V out is but reducing; This moment, the output load was supplied power by Cout, even make when duty ratio (Dutycycle) is very big, output voltage V out but possibly descend.Thereby when start-up course; If the difference of feedback voltage Vfb and reference voltage Vref is very big; Then the duty ratio Duty_cycle of pulse-width signal will be very big; Even the quantity of electric charge that provides to output of each cycle just seldom when inductive current IL is very big, can not make output voltage V out fast and effeciently raise so.
For instance; If the rate of climb of feedback voltage Vfb is little more a lot of than the rate of climb of reference voltage Vref; The duty ratio of pulse-width signal has arrived maximum duty cycle Dmax soon so, and inductive current IL also is raised to electric current limit (Ilim, current limit) very soon; Even be output as zero load this moment, the voltage Δ Vout that each cycle Vout rises is:
ΔVout = Ilim · ( 1 - D max ) · Tsw Cout
Wherein Tsw is the switch periods of transistor MN1, at representative value Ilim=2A, and Dmax=95%, Tsw=1us, under the condition of Cout=47uF, the voltage Δ Vout=2mV that each cycle Vout rises, the voltage that is assigned to Vfb rises just littler:
ΔVfb = R 2 R 1 + R 2 · ΔVout
If the voltage that Vfb rises then can make V less than Vref_ss EAORise De Genggao, remain on maximum duty cycle, thereby vicious circle makes the output voltage rate of climb very slow, and start when finishing and gather huge electric current on the inductive current, output voltage V out also can overshoot (overshoot).
Fig. 2 illustrates the waveform sketch map of the existing DC/DC of the boosting transducer with soft starting circuit shown in Figure 1 at each circuit parameter of start-up course; Wherein start-up course roughly is divided into two stages; Start working A stage and A to the B stage, starting working A during the stage, reference voltage Vref and feedback voltage Vfb gap are little; Be the rate of climb that rise of output voltage speed can be mated capacitance voltage Vref_ss, V EAOValue less, inductive current IL is smaller, at A-B stage (ss_finish=1 after the B point; Soft start finishes) time; Reference voltage Vref and feedback voltage Vfb gap increase gradually, and promptly rise of output voltage speed has been unable to catch up with the rate of climb of capacitance voltage Vref_ss, V EAOIncrease gradually, inductive current IL increases to electric current limit Ilim very soon, and maintains near the electric current limit.
Though the rate of climb of capacitance voltage Vref_ss is transferred the startup that helps the DC/DC transducer slowly; But so just need to increase the capacitance of capacitor C ss; Thereby can take bigger chip area, and be difficult to find the rate of climb of a fixing capacitance voltage Vref_ss to satisfy the condition and the unequally loaded condition of various different input and output.
Therefore, be necessary to propose a kind of scheme more preferably and solve the problems referred to above that the DC/DC transducer runs in start-up course.
[summary of the invention]
The purpose of this part is to summarize some aspects of embodiments of the invention and briefly introduces some preferred embodiments.In this part and the application's specification digest and denomination of invention, may do a little simplification or omit avoiding the making purpose of this part, specification digest and denomination of invention fuzzy, and this simplification or omit and can not be used to limit scope of the present invention.
One object of the present invention is to provide a kind of DC/DC of boosting transducer, be beneficial to the to boost normal startup of DC/DC transducer of its duty ratio that can dynamically adjust the pulse-width signal in it.
Another object of the present invention is to provide a kind of logic control circuit of the DC/DC transducer that is applied to boost, be beneficial to the to boost normal startup of DC/DC transducer of its duty ratio that can dynamically adjust pulse-width signal.
In order to reach the object of the invention; According to an aspect of the present invention; The present invention provides a kind of DC/DC of boosting transducer, and it comprises: include the output circuit that boosts of power switch, be used for an input voltage being boosted to obtain an output voltage with turn-offing under the control in the conducting of power switch; Voltage feedback circuit is used for sampling and outputting voltage and obtains a feedback voltage; Error amplifier is used for the error of reference voltage and feedback voltage is amplified with the generated error amplifying voltage; The pulse-width modulation comparator is used for error amplifying voltage and triangular signal are compared to generate pulse-width signal;
Logic control circuit; Be used for pulse-width signal is carried out logic control; And go to control the conducting and the shutoff of said power switch with the pulse-width signal after the logic control, especially, the said DC/DC of boosting transducer also includes soft starting circuit; The current source that said soft starting circuit comprises electric capacity, charge to electric capacity and select circuit; Said selection circuit selects said capacitance voltage as said reference voltage at said capacitance voltage during less than a canonical reference voltage, selects said canonical reference voltage as said reference voltage at said capacitance voltage during more than or equal to said canonical reference voltage
Said logic control circuit includes: decision circuitry is used to judge whether said pulse-width signal arrives maximum duty cycle; Counting circuit, the number of times that is used for said pulse-width signal is reached maximum duty cycle is counted, and sends the adjustment signal if pulse-width signal reaches continuously after the number of times of maximum duty cycle reaches predetermined value; Control circuit, the duty ratio of adjusting the pulse-width signal of one-period according to said adjustment signal is minimum duty cycle or 0.
Further; Decision circuitry in the said logic control circuit comprises a d type flip flop, and the D pin of said d type flip flop connects pulse-width signal, and the CP pin connects maximum duty cycle signal; When pulse-width signal reached maximum duty cycle, said d type flip flop was through QB pin output low level.
Further; Decision circuitry in the said logic control circuit also comprises a NOR gate; An input of said NOR gate is the output signal of said d type flip flop QB pin, and another input is a soft-start signal, after soft start finishes; Said soft-start signal is a high level, and the output signal of said NOR gate is exactly the output signal of said decision circuitry.
Further; Counting circuit in the said logic control circuit comprises a counter; The R pin of said counter receives the output signal of said decision circuitry, and when said decision circuitry judged that said pulse-width signal arrives maximum duty cycle, said counter was counted; If count results reaches the Q pin output high level of said counter after the said predetermined value, the Q pin output signal of said counter is exactly the output signal of said counting circuit.
Further; Control circuit in the said logic control circuit comprise delayer, not gate, with door and rest-set flip-flop; Said delayer and not gate be parallel connection mutually; The input signal of said delayer and not gate is the output signal of said counting circuit, and the output signal of said delayer and not gate is an input signal said and door, and said output signal with door is the input signal of the R pin of said rest-set flip-flop; The S pin input signal of said rest-set flip-flop is a pulse-width signal, and the NQ pin output signal of said rest-set flip-flop is exactly the output signal of said control circuit.
According to another aspect of the present invention; The present invention provides a kind of logic control circuit of the DC/DC of boosting transducer; Be used for adjusting the pulse-width signal of DC/DC transducer of boosting, it comprises: decision circuitry is used to judge whether said pulse-width signal arrives maximum duty cycle; Counting circuit, the number of times that is used for said pulse-width signal is reached maximum duty cycle is counted, and sends the adjustment signal if pulse-width signal reaches continuously after the number of times of maximum duty cycle reaches predetermined value; Control circuit, the duty ratio of adjusting the pulse-width signal of one-period according to said adjustment signal is minimum duty cycle or 0.
Further, said decision circuitry comprises a d type flip flop, and the D pin of said d type flip flop connects pulse-width signal, and the CP pin connects maximum duty cycle signal, and when pulse-width signal reached maximum duty cycle, said d type flip flop was through QB pin output low level.
Further; Said decision circuitry also comprises a NOR gate; An input of said NOR gate is the output signal of said d type flip flop QB pin, and another input is a soft-start signal, after soft start finishes; Said soft-start signal is a high level, and the output signal of said NOR gate is exactly the output signal of said decision circuitry.
Further; Said counting circuit comprises a counter; The R pin of said counter receives the output signal of said decision circuitry, and when said decision circuitry judged that said pulse-width signal arrives maximum duty cycle, said counter was counted; If count results is above the Q pin output high level of said counter after the predetermined value, the Q pin output signal of said counter is exactly the output signal of said counting circuit.
Further; Said control circuit comprise delayer, not gate, with door and rest-set flip-flop; Said delayer and not gate be parallel connection mutually; The input signal of said delayer and not gate is the output signal of said counting circuit, and the output signal of said delayer and not gate is an input signal said and door, and said output signal with door is the input signal of the R pin of said rest-set flip-flop; The S pin input signal of said rest-set flip-flop is a pulse-width signal, and the NQ pin output signal of said rest-set flip-flop is exactly the output signal of said control circuit.
Compared with prior art, dynamically adjust the duty ratio of pulse-width signal in the present invention through logic control circuit, make input current fully pass to output, let output voltage raise efficiently and effectively, avoid the excessive electric current of accumulation on the inductance.
[description of drawings]
In conjunction with reference to accompanying drawing and ensuing detailed description, the present invention will be more readily understood, the structure member that wherein same Reference numeral is corresponding same, wherein:
Fig. 1 shows a kind of circuit diagram of the DC/DC of boosting transducer;
Fig. 2 illustrates the waveform sketch map of the existing DC/DC of the boosting transducer with soft starting circuit shown in Figure 1 at each circuit parameter of start-up course;
Fig. 3 shows the logic control circuit functional-block diagram in one embodiment among the present invention;
Fig. 4 shows the logic control circuit functional-block diagram in another embodiment among the present invention; With
Fig. 5 shows the waveform sketch map that has adopted each circuit parameter of DC/DC transducer in start-up course that boost behind the logic control circuit among the present invention.
[embodiment]
Detailed description of the present invention is mainly come the running of direct or indirect simulation technical scheme of the present invention through program, step, logical block, process or other symbolistic descriptions.Be the thorough the present invention that understands, in ensuing description, stated a lot of specific detail.And when not having these specific detail, the present invention then possibly still can realize.Affiliated those of skill in the art use these descriptions here and state that the others skilled in the art in affiliated field effectively introduce their work essence.In other words, be the object of the invention of avoiding confusion, owing to method, program, composition and the circuit known are readily appreciated that, so they are not described in detail.
Alleged here " embodiment " or " embodiment " are meant special characteristic, structure or the characteristic that can be contained at least one implementation of the present invention.Different in this manual local " in one embodiment " that occur not are all to refer to same embodiment, neither be independent or optionally mutually exclusive with other embodiment embodiment.In addition, represent that the sequence of modules and revocable in method, flow chart or the functional block diagram of one or more embodiment refers to any particular order, also be not construed as limiting the invention.
For the inductive current of the DC/DC transducer that in start-up course, will boost fully passes to output; Let output voltage raise efficiently and effectively; Accelerate start-up course, avoid the excessive electric current of accumulation on the inductance, need in start-up course, control the duty ratio of adjustment pulse-width signal dynamically.Therefore; The present invention also proposes the DC/DC transducer that boosts as shown in Figure 1; Concrete structure sees also the associated description of background technology to the DC/DC transducer 100 that boosts; Difference from prior art is, has increased the interrelated logic of the duty ratio of dynamic adjustment pulse-width signal in the logic control circuit LOGIC among the present invention.
Fig. 3 shows logic control circuit 300 functional-block diagram in one embodiment among the present invention; Said logic control circuit 300 can be applied in the DC/DC transducer 100 that boosts shown in Fig. 1, to realize the dynamic adjustment control of the pulse-width signal in the start-up course.In order to give top priority to what is the most important, said logic control circuit 300 only shows and dynamically adjusts the relevant control logic of said pulse-width signal.Said logic control circuit 300 comprises decision circuitry 320, counting circuit 340 and control circuit 360.
Said decision circuitry 320 judges whether pulse-width signal reaches maximum duty cycle, and notifies said counting circuit 340 with comparative result.Said counting circuit 340 begins to count when pulse-width signal reaches maximum duty cycle, when pulse-width signal reaches maximum duty cycle, counting is not carried out zero clearing, and after count value reaches predetermined value, sends the adjustment signal.Said count value representes that pulse-width signal reaches the number of times of maximum duty cycle continuously; Said predetermined value can arbitrarily be set as required; Such as 2,3,4,5 and other natural numbers; Said count value reaches predetermined value and representes that then pulse-width signal has continued the abundant time on maximum duty cycle, need dynamically adjust pulse-width signal.Said control circuit 360 is minimum duty cycle or 0 according to the duty ratio of the pulse-width signal of said adjustment signal adjustment one-period; So just can switch-off power switching tube MN1 one-period or make power switch pipe MN1 with minimum duty cycle work one-period; Thereby let the electric current that accumulates on the inductance L fully discharge to output; Output voltage is raise fast, accelerate start-up course, and can avoid gathering on the inductance L too big electric current.
Fig. 4 shows the circuit diagram of logic control circuit 400 of the present invention at another embodiment; Said logic control circuit 400 can be applied in the DC/DC transducer 100 that boosts shown in Fig. 1, to realize the dynamic adjustment control of the pulse-width signal in the start-up course.Please referring to shown in Figure 4, said logic control circuit 400 comprises decision circuitry 420, counting circuit 440 and control circuit 460.
Said decision circuitry 420 comprises a d type flip flop; The D pin of said d type flip flop meets pulse-width signal PWM; The CP pin connects the maximum duty cycle pulse signal; Because the clock pulse rising edge of d type flip flop triggers character (CP pin be input as clock pulse), if said pulse-width signal has reached maximum duty cycle, the QB pin of said d type flip flop output signal Dmax_lim is a low level just.In one embodiment; Said decision circuitry 420 can also comprise a NOR gate; An one of which input signal is that the output signal Dmax_lim of d type flip flop meets startup end signal SS_finish (SS_finish=1 when soft start finishes) with another input; Before the startup of the DC/DC transducer 100 that boosts finishes (SS_finish=0), logic control circuit 400 of the present invention just normally plays the effect of dynamic adjustment duty ratio like this.Said NOR gate can be three inputs.
Said counting circuit 440 comprises a counter; The D pin of said counter meets VDD; Its pin connects the output signal of the NOR gate of said decision circuitry 420; Its pin CP connects normal clock signal, and the Q pin output of said counter will be as the output signal pwm_sync of said counting circuit 440, and the QB of said counter (CLR) pin connects an input of three input NOR gates of said decision circuitry 420.In one embodiment; The pin R of said counting circuit 440 is 0 o'clock; Counter is exported normal clock signal, is to begin counting at 1 o'clock at pin R, when the enough predetermined value N of note (such as 2,3,4,5 or other natural numbers) after; Be that the output signal pwm_sync of counting circuit 440 was continuously height always after said pulse-width signal N continuous time reached maximum duty cycle in one-period.
Said control circuit 460 comprise delayer, not gate, with door and rest-set flip-flop; Said delayer and not gate be parallel connection mutually; The input signal of said delayer and not gate is the output signal pwm_sync of said counting circuit 440; The output signal of said delayer and not gate is an input signal said and door, and said output signal with door is the input signal MIN_pwm of the R pin of said rest-set flip-flop, and the input signal of the pin S of said rest-set flip-flop is pulse-width signal PWM; When the output signal pwm_sync of counting circuit 440 when being high in one-period always; Signal MIN_pwm is a low level just at one-period, and the duty ratio of pulse-width signal in this cycle of said rest-set flip-flop NQ pin output will remain 0, thereby obtained through adjusted pulse-width signal NPWM.
Adopted the DC/DC transducer (during SS_finish=0) in start-up course that boosts behind the logic control circuit among the present invention; If the duty ratio N continuous cycle of pulse-width signal PWM all reaches maximum duty cycle; Then can let power switch pipe MN1 turn-off or minimum conducting one-period,, let output voltage raise as early as possible to let the output of in a complete cycle, releasing of the electric current that gathers on the inductance L; Along with rising, also accelerates the output feedback voltage afterwards; Error amplification signal EAO can be too not high yet, and inductive current L can not accumulate too big yet, makes the normal startup fast of system.
Fig. 5 shows the waveform sketch map that has adopted each circuit parameter of DC/DC transducer in start-up course that boost behind the logic control circuit among the present invention.Please refer to Fig. 5, start-up course equally roughly is divided into two stages, and start working A stage and A are to the B stage; Starting working A during the stage, similar with start-up course among Fig. 2, at A to B during the stage; With respect to the B stage among Fig. 2; Reference voltage Vref and feedback voltage Vfb gap are little, and promptly rise of output voltage speed can be mated the rate of climb of capacitance voltage Vref_ss, V EAOValue less, inductive current IL is less relatively, toggle speed is more rapid.
Above-mentioned explanation has fully disclosed embodiment of the present invention.It is pointed out that any change that technical staff's specific embodiments of the invention of being familiar with this field is done does not all break away from the scope of claims of the present invention.Correspondingly, the scope of claim of the present invention also is not limited only to said embodiment.

Claims (10)

1. DC/DC transducer that boosts, it comprises:
Include the output circuit that boosts of power switch, be used for turn-offing under the control input voltage being boosted to obtain an output voltage in the conducting of power switch;
Voltage feedback circuit is used for sampling and outputting voltage and obtains a feedback voltage;
Error amplifier is used for the error of reference voltage and feedback voltage is amplified with the generated error amplifying voltage;
The pulse-width modulation comparator is used for error amplifying voltage and triangular signal are compared to generate pulse-width signal;
Logic control circuit; Be used for pulse-width signal is carried out logic control; And go to control the conducting and the shutoff of said power switch with the pulse-width signal after the logic control, it is characterized in that the said DC/DC of boosting transducer also includes soft starting circuit; The current source that said soft starting circuit comprises electric capacity, charge to electric capacity and select circuit; Said selection circuit selects said capacitance voltage as said reference voltage at said capacitance voltage during less than a canonical reference voltage, selects said canonical reference voltage as said reference voltage at said capacitance voltage during more than or equal to said canonical reference voltage
Said logic control circuit includes:
Decision circuitry is used to judge whether the pulse-width signal that said pulse-width modulation comparator generates arrives maximum duty cycle;
Counting circuit, the number of times that is used for the pulse-width signal that said pulse-width modulation comparator generates is reached maximum duty cycle is counted, if this pulse-width signal reaches the number of times of maximum duty cycle continuously reach predetermined value after, then send the adjustment signal;
Control circuit, the duty ratio of the pulse-width signal that generates according to the said pulse-width modulation comparator of said adjustment signal adjustment one-period is minimum duty cycle or 0.
2. the DC/DC transducer that boosts according to claim 1; It is characterized in that: the decision circuitry in the said logic control circuit comprises a d type flip flop; The D pin of said d type flip flop connects the pulse-width signal that said pulse-width modulation comparator generates; The CP pin connects maximum duty cycle signal, and when the pulse-width signal of said pulse-width modulation comparator generation reached maximum duty cycle, said d type flip flop was through QB pin output low level.
3. the DC/DC transducer that boosts according to claim 2; It is characterized in that: the decision circuitry in the said logic control circuit also comprises a NOR gate; An input of said NOR gate is the output signal of said d type flip flop QB pin, and another input is a soft-start signal, after soft start finishes; Said soft-start signal is a high level, and the output signal of said NOR gate is exactly the output signal of said decision circuitry.
4. the DC/DC transducer that boosts according to claim 3; It is characterized in that: the counting circuit in the said logic control circuit comprises a counter; The R pin of said counter receives the output signal of said decision circuitry; When said decision circuitry judged that the pulse-width signal of said pulse-width modulation comparator generation arrives maximum duty cycle, said counter was counted, if after count results reaches said predetermined value; Then the Q pin of said counter is exported high level, and the Q pin output signal of said counter is exactly the output signal of said counting circuit.
5. according to the arbitrary described DC/DC transducer that boosts of claim 1 to 4; It is characterized in that: the control circuit in the said logic control circuit comprise delayer, not gate, with door and rest-set flip-flop; Said delayer and not gate be parallel connection mutually; The input signal of said delayer and not gate is the output signal of said counting circuit; The output signal of said delayer and not gate is an input signal said and door; Said output signal with door is the input signal of the R pin of said rest-set flip-flop, and the S pin input signal of said rest-set flip-flop is the pulse-width signal that said pulse-width modulation comparator generates, and the NQ pin output signal of said rest-set flip-flop is exactly the output signal of said control circuit.
6. logic control circuit of DC/DC transducer that boosts is used for adjusting the pulse-width signal of DC/DC transducer of boosting, and it is characterized in that it comprises:
Decision circuitry is used to judge whether said pulse-width signal arrives maximum duty cycle;
Counting circuit, the number of times that is used for said pulse-width signal is reached maximum duty cycle is counted, if pulse-width signal reaches the number of times of maximum duty cycle continuously reach predetermined value after, then send the adjustment signal;
Control circuit, the duty ratio of adjusting the pulse-width signal of one-period according to said adjustment signal is minimum duty cycle or 0.
7. logic control circuit according to claim 6; It is characterized in that: said decision circuitry comprises a d type flip flop; The D pin of said d type flip flop connects said pulse-width signal; The CP pin connects maximum duty cycle signal, and when this pulse-width signal reached maximum duty cycle, said d type flip flop was through QB pin output low level.
8. logic control circuit according to claim 7; It is characterized in that: said decision circuitry also comprises a NOR gate; An input of said NOR gate is the output signal of said d type flip flop QB pin, and another input is a soft-start signal, after soft start finishes; Said soft-start signal is a high level, and the output signal of said NOR gate is exactly the output signal of said decision circuitry.
9. logic control circuit according to claim 8; It is characterized in that: said counting circuit comprises a counter, and the R pin of said counter receives the output signal of said decision circuitry, when said decision circuitry judges that said pulse-width signal arrives maximum duty cycle; Said counter is counted; After if count results surpasses predetermined value, then the Q pin of said counter is exported high level, and the Q pin output signal of said counter is exactly the output signal of said counting circuit.
10. according to the arbitrary described logic control circuit of claim 6 to 9; It is characterized in that: the control circuit in the said logic control circuit comprise delayer, not gate, with door and rest-set flip-flop; Said delayer and not gate be parallel connection mutually; The input signal of said delayer and not gate is the output signal of said counting circuit, and the output signal of said delayer and not gate is an input signal said and door, and said output signal with door is the input signal of the R pin of said rest-set flip-flop; The S pin input signal of said rest-set flip-flop is said pulse-width signal, and the NQ pin output signal of said rest-set flip-flop is exactly the output signal of said control circuit.
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