CN101840882B - Shallow slot isolation method - Google Patents

Shallow slot isolation method Download PDF

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Publication number
CN101840882B
CN101840882B CN2009100479481A CN200910047948A CN101840882B CN 101840882 B CN101840882 B CN 101840882B CN 2009100479481 A CN2009100479481 A CN 2009100479481A CN 200910047948 A CN200910047948 A CN 200910047948A CN 101840882 B CN101840882 B CN 101840882B
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Prior art keywords
etching
photoresistance
light resistance
shallow slot
pattern
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CN101840882A (en
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周建军
张京晶
王军
石锗元
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Abstract

The invention discloses a shallow slot isolation method, comprising the following steps: (1) providing a silicon substrate; (2) successively arranging an oxide layer, a nitride layer and a light resistance layer on the silicon substrate; (3) etching light resistance to form a pattern; (4) etching the nitride layer; (5) etching the oxide layer; (6) etching silicon to form a shallow slot; (7) stripping the light resistance to remove the residual light resistance; and (8) carrying out gas purging. The shallow slot isolation method is characterized in that the step of stripping is carried out after etching to thoroughly remove the light resistance and prevent the light resistance from residing on products; and the step of gas purging is added to thoroughly remove the residual light resistance and the by-products of the light resistance in the etching process, thus preventing the etched residual light resistance and the produced by-product thereof from depositing on the edge side or the surface of the etched pattern, ensuring the accuracy of the pattern formed by etching, and improving product yield.

Description

Shallow slot isolation method
Technical field
The present invention relates to the manufacture of semiconductor field, particularly a kind of shallow slot isolation method.
Background technology
In manufacture of semiconductor technology, etching technics is in important status.Etching technics (etchingprocess) is to remove the thin layer of not sheltered by resist, thus obtain on the film with resist film on the technology of identical figure.In ic manufacturing process; Through mask alignment, exposure and development; On resist film, run off required figure; Perhaps be depicted in electron beam direct and produce figure on the resist film, dielectric film (like silica, silicon nitride, polysilicon) or the metallic film (like aluminium and alloy thereof) accurately transferred to this figure below the resist then get on, and produce required thin layer pattern.Etching be exactly with the chemistry, method physics or that use chemistry and physics simultaneously, remove that a part of thin layer of not sheltered selectively by resist, thus obtain on the film with resist film on all four figure.
Desirable etching technics must have following characteristics: 1. anisotropic etching, promptly have only vertical etching, and there is not horizontal undercutting.Could guarantee so accurately copy on the film that is etched with resist on all four geometric figure; 2. good etching selection property; Promptly to all the etch rate than the film that is etched is much little with being in another layer film or the etch rate of material under it as the resist of mask; With the validity that guarantees that resist is sheltered in the etching process, unlikely generation damages the other materials below the film because of over etching; 3. manufacturing batch is big, and control is easy, and cost is low, and environmental pollution is few, is applicable to commercial production.
But in actual mechanical process, because the restriction of each side condition can cause etching can't reach desirable effect.A undesirable influence is avris or the surface that residue is deposited on etching pattern in the plasma etching of dry etching; Residue has many violent chemical reactions from photoresistance and photoresistance residual accessory substance after etching in the plasma etching environment, hydrogen-oxygen group and halide gas in the photoresistance react; To form stable metal halide (like AlF3; WF5, WF6) and these accessory substances of oxide (like TiO3, TiO etc.) produce pollution problems; Influence the formation of etching pattern, and then influence the quality of etching product.See also Fig. 1 and Fig. 2; What make is the logic product that a kind of grid live width is 130nm, when silicon chip 100 is carried out trench isolations, through regular meeting behind plasma etching; Because the accessory substance 110 that residual photoresistor produces causes the undesirable of etching pattern; Can't accurately demonstrate required specific pattern, and then reduce the yield of product, increase manufacturing cost.
Summary of the invention
The present invention is intended to solve in the above-mentioned prior art, because in traditional etching, the residue of residual photoresistor and formation thereof like metal halide and oxide, is deposited on the avris or the surface of etching pattern, causes the problem that presents pattern that can't reach desirable.
In view of this, the present invention provides a kind of shallow slot isolation method, may further comprise the steps: (1) provides a silicon substrate; (2) on said silicon substrate, form oxide skin(coating) successively, nitride layer, photoresist layer; (3) the etching photoresistance forms pattern; (4) etch nitride layer; (5) etching oxide layer; (6) etch silicon forms shallow slot; (7) peel off photoresistance, to remove remaining photoresistance; (8) carry out the gas blow-washing operation.
Optional, wherein step (7) is that reative cell is vacuumized, when stable gas pressure 9 to 11mtorr the time, add 900 to 1100W RF power source, at this moment feed 180 to 220sccm oxygen, produce plasma and peeled off for 80 to 100 seconds.
Optional, wherein step (8) adopts the oxygen of 225 to 275sccm helium mix 405 to 495sccm, 25 to 35 seconds of purge.
In sum, method of shallow trench provided by the present invention is after strip step is placed etching; Can more thoroughly remove photoresistance, prevent that photoresistance from remaining on the product, and increase the gas blow-washing step; Can remove remaining photoresistance and the accessory substance of photoresistance in the etching process more up hill and dale; Avoid the by-product deposition that residual photoresistor produces after the etching on the avris or the surface of etching pattern, guaranteed the accuracy of pattern that etching forms, improved the yield of product.
Description of drawings
Fig. 1 and shown in Figure 2 for causing the unfavorable figure of etching owing to polymer residue in the prior art;
Shown in Figure 3 for being depicted as the process chart that carries out shallow-trench isolation in the prior art;
Shown in Figure 4 for the process chart of the shallow-trench isolation that one embodiment of the invention provided.
Embodiment
For making the object of the invention, characteristic more obviously understandable, provide preferred embodiment and combine accompanying drawing, the present invention is described further.
See also Fig. 3, it is depicted as the process chart that carries out shallow-trench isolation in the prior art, may further comprise the steps: S31: a silicon substrate is provided;
S32: on said silicon substrate, form oxide skin(coating), nitride layer, photoresist layer successively;
S33: the etching photoresistance forms pattern;
S34: etch nitride layer;
S35: etching oxide layer;
S36: peel off photoresistance, to remove remaining photoresistance;
S37: etch silicon forms shallow slot.
Place the S37 etch silicon to form before the shallow slot because S36 peels off photoresistance, when photoresistance is removed, photoresistance can residually be arranged; Yet this residual photoresistor is in the dry plasma etch of thereafter formation shallow slot; Halide gas reacts in hydrogen-oxygen group in the photoresistance and the dry plasma etch, can produce a large amount of accessory substances, influences the pattern of etching; And then influence the quality of product, please combine referring to Fig. 1 and Fig. 2.
See also Fig. 4, the process chart that it is depicted as the shallow-trench isolation that one embodiment of the invention provides may further comprise the steps:
S41 a: silicon substrate is provided;
S42: on said silicon substrate, form oxide skin(coating), nitride layer, photoresist layer successively, these layers are formed for the masking layer of composition in surface of silicon.
S43: the etching photoresistance forms pattern;
S44: do not having the photoresistance region covered, etch nitride layer, with form with photoresistance on identical pattern;
S45: in the zone that does not have photoresistance and nitride, the etching oxide layer forms above-mentioned pattern;
Through step S43 to S45, form through pattern at above-mentioned masking layer.
S46: etch silicon forms shallow slot.Because the silicon substrate that can only etching not be covered by above-mentioned masking layer, so it is regional on silicon substrate, to form the groove identical with above-mentioned specific pattern.
S47: peel off photoresistance, to remove remaining photoresistance.Reative cell is vacuumized, when stable gas pressure 9 to 11mtorr the time, add 900 to 1100W RF power source, at this moment feed 180 to 220sccm oxygen, produce plasma said product peeled off for 80 to 100 seconds.Plasma field is energized into upper state to oxygen, can the photoresistance composition be oxidized to gas, gets rid of again, therefore can remove remaining photoresistance, facts have proved the effect that can reach a good removing photoresistance like this
S48: carry out the gas blow-washing operation.This step is not charged; Only adopt gas blow-washing; The oxygen of the helium mix 405 to 495sccm of employing 225 to 275sccm; 25 to 35 seconds of purge, can remove residue photoresistance and photoresistance in the etching process residual accessory substance after etching up hill and dale, avoided these residue photoresistance accessory substances to produce pollution problem.
Relatively the prior art and the embodiment of the invention provide the technological process of shallow-trench isolation, its main distinction is two:
1. in an embodiment of the present invention, will peel off the photoresistance step and place the etch silicon substrate to form the shallow slot back,, prevent that photoresistance from remaining on the product so can more thoroughly remove photoresistance.
2. increase the gas blow-washing step in an embodiment of the present invention to remove residue photoresistance and photoresistance residual accessory substance after etching more up hill and dale, avoided the product defective of incomplete etching to occur.
In sum, method of shallow trench provided by the present invention is after strip step is placed etching; Can more thoroughly remove photoresistance, prevent that photoresistance from remaining on the product, and increase the gas blow-washing step; Can remove remaining photoresistance and the accessory substance of photoresistance in the etching process more up hill and dale; Avoid the by-product deposition that residual photoresistor produces after the etching on the avris or the surface of etching pattern, guaranteed the accuracy of pattern that etching forms, improved the yield of product.
Though the present invention discloses as above with preferred embodiment; Right its is not in order to limiting the present invention, anyly has the knack of this operator, do not breaking away from the spirit and scope of the present invention; When can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.

Claims (1)

1. a shallow slot isolation method is characterized in that, may further comprise the steps:
(1) silicon substrate is provided;
(2) on said silicon substrate, form oxide skin(coating) successively, nitride layer, photoresist layer;
(3) the etching photoresistance forms pattern;
(4) etch nitride layer;
(5) etching oxide layer;
(6) etch silicon forms shallow slot;
(7) peel off photoresistance, to remove remaining photoresistance;
(8) carry out the gas blow-washing operation;
Wherein, step (7) is that reative cell is vacuumized, when stable gas pressure 9 to 11mtorr the time, add 900 to 1100W RF power source, at this moment feed 180 to 220sccm oxygen, produce plasma and peeled off for 80 to 100 seconds;
Wherein, step (8) adopts the oxygen of 225 to 275sccm helium mix 405 to 495sccm, 25 to 35 seconds of purge.
CN2009100479481A 2009-03-20 2009-03-20 Shallow slot isolation method Active CN101840882B (en)

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CN103545259B (en) * 2012-07-13 2016-11-02 中芯国际集成电路制造(上海)有限公司 The minimizing technology of the PMOS replacement gate of CMOS tube
CN108630526B (en) * 2018-05-03 2020-11-06 武汉新芯集成电路制造有限公司 Method for improving cavity of interlayer dielectric layer
US11581692B2 (en) * 2019-06-18 2023-02-14 KLA Corp. Controlling pressure in a cavity of a light source

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1647257A (en) * 2002-04-16 2005-07-27 东京电子株式会社 Method for removing photoresist and etch residues
CN101179046A (en) * 2006-11-06 2008-05-14 北京北方微电子基地设备工艺研究中心有限责任公司 Silicon chip shallow plow groove isolation etching method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1647257A (en) * 2002-04-16 2005-07-27 东京电子株式会社 Method for removing photoresist and etch residues
CN101179046A (en) * 2006-11-06 2008-05-14 北京北方微电子基地设备工艺研究中心有限责任公司 Silicon chip shallow plow groove isolation etching method

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