CN101839984B - Navigational satellite signal receiver - Google Patents
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Abstract
The invention relates to an antenna of a navigational satellite signal receiving machine, which comprises an antenna, a radio frequency front end module and a base band processing module, wherein the antenna is used for receiving one or a plurality of wave beams of navigational satellite signals, the radio frequency front end module is used for converting each wave beam of navigational satellite signals received by the antenna into two paths of middle frequency digital signals: path I and path Q, the base band processing module is used for carrying out base band signal processing on the middle frequency digital signals to obtain original data, the base band processing module concretely comprises a memory and a viterbi decoder, the memory is used for storing each path of middle frequency digital signals, when a path of stored middle frequency digital signals is a complete frame of data, the complete frame of data is sent into the viterbi decoder, and the viterbi decoder is used for decoding the sent data to obtain serial original data. The invention can realize the simultaneous receiving of a plurality of wave beams of signals, and in addition, the cost can not be greatly increased.
Description
Technical field
The present invention relates to navigation field, be specifically related to a kind of navigational satellite signal receiver.
Background technology
Navigational satellite signal receiver is a kind of downstream signal that is used to receive navigation satellite (like satellite of the Big Dipper); Extract location, the communication of the affiliated subscriber computer of modulating in the signal of subordinate user and the broadcasting of setting off etc. for information about; And this information is outputed to the external data treatment system carry out decryption processing, the equipment of submitting to the user to use.
Scale fpga chip in the general use of existing receiver can't realize receiving simultaneously a plurality of beam signals, such as the Big Dipper 3 satellites is arranged for No. one; Totally 6 beam signals; According to prior art,, then need strengthen the Base-Band Processing ability if receive simultaneously; If but used more massive fpga chip, the cost of receiver then could be increased greatly.
In addition, existing receiver can't be supervised location, the communication information of receiving 100 above subordinate users.
Summary of the invention
The technical problem that the present invention will solve provides a kind of navigational satellite signal receiver, receives when can realize a plurality of beam signal, and can not increase cost greatly.
In order to address the above problem, the invention provides a kind of navigational satellite signal receiver, comprising:
Antenna is used to receive the navigation satellite signal of one or more wave beams;
RF front-end module, the navigation satellite signal of each wave beam that is used for antenna is received converts I, Q two-way digital intermediate frequency signal into;
Baseband processing module is used for said digital intermediate frequency signal is carried out base band signal process, obtains initial data;
Said baseband processing module specifically comprises:
Memory, viterbi decoder, serial-parallel conversion circuit and output FIFO;
Said memory is used to preserve each road digital intermediate frequency signal, and when the road digital intermediate frequency signal of being preserved was complete frame data, the frame data that this is complete were sent into said viterbi decoder;
Said viterbi decoder be used to the decode data sent into obtain the initial data of serial.
Further, said baseband processing module also comprises: serial-parallel conversion circuit and output FIFO;
Said serial-parallel conversion circuit is used for converting the initial data of the serial of said viterbi decoder output to parallel initial data, is buffered among the said output FIFO;
Described receiver also comprises:
Processor; Prestore one comprise ID and ID1 information content corresponding relation the local ident table; And one comprise ID and the Q road special-purpose first phase table in Q road of phase information corresponding relation just; Be used for reading said parallel initial data, in said local ident table, find corresponding ID, in the special-purpose first phase table in said Q road, find the corresponding first phase information of this ID according to this ID according to the ID1 information content of I road initial data wherein from said output FIFO; Before the next flag of frame of Q road digital intermediate frequency signal, insert first phase according to this first phase information.
Further, the corresponding relation in the special-purpose first phase table in said local ident table of preserving in the said processor and said Q road is arranged according to the size order of ID; When said processor is searched said ID according to the said ID1 information content, and when searching said phase information just, adopt binary search to search according to said ID.
Further, said memory comprises:
Dispatch circuit, receive FIFO one to one with each road digital intermediate frequency signal respectively;
Said reception FIFO is used for the pairing digital intermediate frequency signal of buffer memory;
Said dispatch circuit is used for when a digital intermediate frequency signal that receives the FIFO buffer memory is complete frame data, sending into said viterbi decoder continuously with the digital intermediate frequency signal that high-frequency clock will be buffered among this reception FIFO.
Further, described receiver also comprises: processor;
Said dispatch circuit also is used for after the initial data that full 1 frame of said output FIFO buffer memory walks abreast, sending interrupt requests to said processor;
After said processor is received said interrupt requests, from said output FIFO, read said parallel initial data.
Further, said reception FIFO is 12, I, the Q two-way digital intermediate frequency signal of respectively corresponding 6 wave beams.
Further, said memory comprises:
One or more memory cell, corresponding one by one with the wave beam that is received respectively;
Each memory cell comprises respectively: register, timer;
RAM, be used to preserve I, the Q two-way digital intermediate frequency signal of corresponding wave beam;
First control unit, be used for corresponding wave beam I, Q two-way digital intermediate frequency signal a road write said RAM earlier, again another road is write said RAM; When I, Q two-way are respectively write full 1 frame data; Produce an interrupt signal and start said timer; With I, the Q two-way digital intermediate frequency signal of corresponding wave beam be temporarily stored in earlier in the said register, up to said timer then after with said register in temporary data write said RAM;
Second control unit is used for when receiving said interrupt signal, from said RAM, reads I, Q two-way digital intermediate frequency signal, sends into said viterbi decoder; When said timer stops to read then.
Further, said timer duration regularly is 2.5ms.
Further, said viterbi decoder comprises:
The logical sequence control unit is used to produce the logical sequence control signal;
The normalized decision unit is used to receive the branch metric maximum, produces the normalization control signal;
Transfering state storage RAM is used to receive said logical sequence control signal and said normalization control signal, produces current status data;
Local code and succeeding state generation unit are used to receive said current status data, produce the succeeding state data and read in the address as the probability accumulated value, and produce 0 branch road, 1 circuit-switched data;
Data processing unit is used to receive the said digital signal of sending into, said 0 branch road, 1 circuit-switched data and current branch road probability accumulated value, produces succeeding state and chooses indication, said branch metric maximum and 0 branch road, 1 branch road probability accumulated value;
The succeeding state processing unit is used to receive said succeeding state data and succeeding state and chooses indication, produces the probability accumulated value and writes the address;
Probability is measured the accumulated value unit, is used to receive said 0 branch road, 1 branch road probability accumulated value, branch metric maximum, the probability accumulated value writes the address and the probability accumulated value reads in the address, produces said current branch road probability accumulated value;
The error code decision unit is used to receive said current status data, produces the initial data of serial;
The Error detection unit is used for according to said current status data and the said digital signal that received, output error code number.
Further, said data processing unit comprises:
Probability is measured the generation subelement, is used to receive the said digital signal of sending into, and produces four groups of probable values, is respectively 00 attitude, 01 attitude, 10 attitudes and 11 attitudes;
Branch metric produces subelement, is used to receive said four groups of probable values, and said 0 branch road, 1 circuit-switched data, produces 0 branch road, 1 branch road branch metric value;
Branch metric is chosen and probability adds up subelement is used to receive said 0 branch road, I branch road branch metric value and said current branch road probability accumulated value, produces succeeding state and chooses indication, said branch metric maximum and 0 branch road, 1 branch road probability accumulated value.
One embodiment of the present of invention comprise following advantage at least: viterbi decoder is carried out time division multiplexing, can under the situation that does not change disposal ability, realize the reception of a plurality of wave beams; Such as with 6 I branch roads of 6 wave beams of a viterbi decoder IP kernel, 6 the Q branch roads viterbi decoder of totally 12 road signals, thereby can on middle scale fpga chip, realize receiving in 6 beam signals of 3 satellites.An alternative embodiment of the invention comprises following advantage at least: improved the efficient of searching Q road first phase, thereby can support 1000 above subordinate users' location, the communication information.
Description of drawings
Fig. 1 carries out the schematic flow sheet that Q road first phase is inserted for the processor of the navigational satellite signal receiver of embodiment one;
Fig. 2 is the sketch map of baseband processing module of the navigational satellite signal receiver of embodiment one;
Fig. 3 is the sketch map of viterbi decoder of the navigational satellite signal receiver of embodiment one;
Fig. 4 is the sketch map of the RAM in the baseband processing module of navigational satellite signal receiver of embodiment one.
Embodiment
To combine accompanying drawing and embodiment that technical scheme of the present invention is explained in more detail below.
Embodiment one, and a kind of navigational satellite signal receiver comprises:
Antenna, RF front-end module, and baseband processing module;
Said antenna is used to receive the navigation satellite signal of one or more wave beams;
Said RF front-end module is used for converting the navigation satellite signal of each wave beam of antenna reception into I, Q two-way digital intermediate frequency signal;
Said baseband processing module is used for said digital intermediate frequency signal is carried out base band signal process, obtains initial data.
Said baseband processing module is caught signal, follows the tracks of, and despreading, the scheme of demodulation can repeat no more among this paper by existing techniques in realizing.
In the present embodiment, said baseband processing module specifically can comprise:
Memory, viterbi decoder;
Said memory is used to preserve each road digital intermediate frequency signal, and when the road digital intermediate frequency signal of being preserved was complete frame data, the frame data that this is complete were sent into said viterbi decoder;
Said viterbi decoder be used to the decode data sent into obtain the initial data of serial.
In the present embodiment, said baseband processing module can also comprise: serial-parallel conversion circuit and output FIFO (first-in first-out register);
Said serial-parallel conversion circuit is used for converting the initial data of the serial of said viterbi decoder output to parallel initial data, is buffered among the said output FIFO;
Said navigational satellite signal receiver can further include processor.
In the present embodiment, said baseband processing module can but be not limited to FPGA; Said processor can but be not limited to CPU.
According to the exit signal format protocol of " No. one, the Big Dipper " system, departures Q adopts Gold sequence spread spectrum technology in the road, requires the real-time Q of realization road Gold sequence first phase to insert treatment technology.
Said processor prestore one comprise ID and ID1 information content corresponding relation the local ident table; And one comprise ID and the Q road special-purpose first phase table in Q road of phase information corresponding relation just; Be used for reading said parallel initial data from said output FIFO; In said local ident table, find corresponding ID according to the ID1 information content of I road initial data wherein, in the special-purpose first phase table in said Q road, find the corresponding first phase information of this ID according to this ID; Before the next flag of frame of Q road digital intermediate frequency signal, insert first phase according to this first phase information.
In the present embodiment, the corresponding relation in the special-purpose first phase table in said local ident table of preserving in the said processor and said Q road is arranged according to the size order of ID; When said processor is searched said ID according to the said ID1 information content, and when searching said phase information just, adopt binary search to search according to said ID.
In the practical application, also can adopt Hash table to search or other mode of searching realizes.
The processing that just is complementary has the requirement of high speed hard real-time, and total duration of the once-through operation that Viterbi decoding is inserted to first phase from the I road is not more than the correlation demodulation time of the frame synchronization head of 13bit, counts 812.5us.Wherein, the time overhead of accomplishing I road Viterbi decoding is about 188us, and the time that can be used for just being complementary is 624.5us.Processor prop up from I obtain id information the circuit-switched data after, classical lookup method such as can adopt that binary search or Hash table are searched can find ID number pairing first phase of coupling in the short time, and insert Q road PN sign indicating number generator.The response time that processor interrupts is less than 100us; Binary search only need just be searched for 10 times can search for 1000 ID information; To be far smaller than 624.5us from interrupt response to inserting the used time of Q road first phase, thereby realize at least 1000 users' the real-time search matched of ID.
In the concrete example, it is as shown in Figure 1 that said processor carries out the flow process that Q road first phase inserts, and may further comprise the steps:
101,1000 IDs of initialization;
102, wait for I branch road data interruption;
103, carry out the data parsing of I branch road;
104, judge whether the ID that I props up in the circuit-switched data has occurrence; If have, then carry out step 105; If no, then carry out step 109;
105, local ident is searched, and obtains corresponding first phase information;
The first phase information that 106, will obtain is inserted GOLD sign indicating number generator;
107, wait for Q branch road data interruption;
108, carry out the data parsing of Q branch road;
109, carry out other processing; Return step 102.
Because this reception function receives I, the Q of 6 wave beams simultaneously and props up circuit-switched data; And all customer data of satellite system all sends from I, the Q branch road of 6 wave beams; This receiver also receives problem with regard to having solved 1000 user's data in the ID real-time searching that has solved 1000 users.
In a kind of execution mode of present embodiment, said memory specifically can comprise:
Dispatch circuit, receive FIFO one to one with each road digital intermediate frequency signal respectively;
Said reception FIFO is used for the pairing digital intermediate frequency signal of buffer memory;
Said dispatch circuit is used for when a digital intermediate frequency signal that receives the FIFO buffer memory is complete frame data, sending into said viterbi decoder continuously with the digital intermediate frequency signal that high-frequency clock will be buffered among this reception FIFO.
When said receiver comprised processor, said dispatch circuit can also be further used for after the initial data that full 1 frame of said output FIFO buffer memory walks abreast, sending interrupt requests to said processor, and notification processor is read said parallel initial data;
After said processor is received said interrupt requests, from said output FIFO, read said parallel initial data.
Baseband processing module in object lesson of this execution mode is as shown in Figure 2, and in this example, said reception FIFO is 12, is respectively applied for the I that preserves 6 wave beams, Q two-way totally 12 road digital intermediate frequency signals; The reception FIFO of the I road part of only having drawn among Fig. 2, the structure of Q road part and I road part are similar, in Fig. 2, do not draw.
In the another kind of execution mode of present embodiment, said memory specifically can comprise:
One or more memory cell, corresponding one by one with the wave beam that is received respectively;
Each memory cell is as shown in Figure 3, comprises respectively:
Register (not drawing among Fig. 3), timer (not drawing among Fig. 3);
RAM, be used to preserve I, the Q two-way digital intermediate frequency signal of corresponding wave beam;
First control unit, control RAM writes clock and write address, be used for corresponding wave beam I, Q two-way digital intermediate frequency signal a road write said RAM earlier, again another road is write said RAM; When I, Q two-way are respectively write full 1 frame data; Produce an interrupt signal and start said timer; With I, the Q two-way digital intermediate frequency signal of corresponding wave beam be temporarily stored in earlier in the said register, up to said timer then after with said register in temporary data write said RAM;
Second control unit, control RAM reads clock and reads the address, is used for when receiving said interrupt signal, from said RAM, reads I, Q two-way digital intermediate frequency signal, sends into said viterbi decoder; When said timer stops to read then.
It is thus clear that in this embodiment, frame data will produce interruption after all writing RAM, in the RAM that has no progeny change read states over to, read states continues about 2.5ms, and then changes the state of writing over to, so circulation.
Said timer can realize also that when practical application its function is the time control that will accomplish read states with timer or counter; Duration regularly can should be able to guarantee to have read I, each frame data of Q road according to experiment or experience setting; In the present embodiment, be preset as 2.5ms.Also independently timer can be set during practical application, carry out timing, stop to read after the time that arrival is preset, and notify said first control unit to begin to write by second control unit.
During practical application, said first control unit can be integrated in the said RF front-end circuit, and second control unit can be integrated in the said viterbi decoder.
Said first control unit with I, when Q two-way digital intermediate frequency signal successively writes RAM because: I; The Q two paths of data arrives simultaneously; And both will be stored in the same block RAM, must the moment that two paths of data is write RAM be staggered, and clash with the moment of avoiding writing RAM.
In this execution mode,, therefore, can not carry out read and write simultaneously to RAM owing to be difficult to adopt the dual port RAM form; The serial data that receives is successively to arrive, and the time interval of writing RAM will be carried out read operation to RAM less than 1ms, can only in writing the gap of RAM, carry out.RAM storage I, each 1 frame data of Q two-way are supposed totally 64 bytes, have whenever deposited 64 bytes and have provided an interrupt signal, notify said viterbi decoder to read; But in the time less than 1ms, said viterbi decoder can not all run through this 64 byte.Therefore; RAM changes read states over to after providing interrupt signal, and read states will keep more than the 2ms, and the digital intermediate frequency signal that arrives within many times at this 2ms is stored in the register earlier; After running through, again it is write RAM; I, Q two-way respectively have two bytes temporarily to deposit register in, and like this, the time of reading RAM that vacates is more than 2.5ms.
In the present embodiment, said viterbi decoder adopts large-scale integration technology, and is as shown in Figure 4, specifically can comprise:
The logical sequence control unit is used to produce the logical sequence control signal;
The normalized decision unit is used to receive the branch metric maximum, produces the normalization control signal;
Transfering state storage RAM is used to receive said logical sequence control signal and said normalization control signal, produces current status data;
Local code and succeeding state generation unit are used to receive said current status data, produce the succeeding state data and read in the address as the probability accumulated value, and produce 0 branch road, 1 circuit-switched data;
Data processing unit is used to receive the said digital signal of sending into, said 0 branch road, 1 circuit-switched data and current branch road probability accumulated value, produces succeeding state and chooses indication, said branch metric maximum and 0 branch road, 1 branch road probability accumulated value;
The succeeding state processing unit is used to receive said succeeding state data and succeeding state and chooses indication, produces the probability accumulated value and writes the address;
Probability is measured the accumulated value unit, is used to receive said 0 branch road, 1 branch road probability accumulated value, branch metric maximum, the probability accumulated value writes the address and the probability accumulated value reads in the address, produces said current branch road probability accumulated value;
The error code decision unit is used to receive said current status data, produces the initial data of serial;
The Error detection unit is used for according to said current status data and the said digital signal that received, output error code number.
In the present embodiment, said data processing unit specifically can comprise:
Probability is measured the generation subelement, is used to receive the said digital signal of sending into, and produces four groups of probable values, is respectively 00 attitude, 01 attitude, 10 attitudes and 11 attitudes;
Branch metric produces subelement, is used to receive said four groups of probable values, and said 0 branch road, 1 circuit-switched data, produces 0 branch road, 1 branch road branch metric value;
Branch metric is chosen and probability adds up subelement is used to receive said 0 branch road, I branch road branch metric value and said current branch road probability accumulated value, produces succeeding state and chooses indication, said branch metric maximum and 0 branch road, 1 branch road probability accumulated value.
Certainly; The present invention also can have other various embodiments; Under the situation that does not deviate from spirit of the present invention and essence thereof; Those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of claim of the present invention.
Claims (9)
1. navigational satellite signal receiver comprises:
Antenna is used to receive the navigation satellite signal of one or more wave beams;
RF front-end module, the navigation satellite signal of each wave beam that is used for antenna is received converts I, Q two-way digital intermediate frequency signal into;
Baseband processing module is used for said digital intermediate frequency signal is carried out base band signal process, obtains initial data;
Processor;
It is characterized in that said baseband processing module comprises: output FIFO;
Memory, viterbi decoder;
Said memory is used to preserve each road digital intermediate frequency signal, and when the road digital intermediate frequency signal of being preserved was complete frame data, the frame data that this is complete were sent into said viterbi decoder;
Said viterbi decoder be used to the decode data sent into obtain the initial data of serial;
Serial-parallel conversion circuit is used for converting the initial data of the serial of said viterbi decoder output to parallel initial data, is buffered among the said output FIFO;
Said processor prestore one comprise ID and ID1 information content corresponding relation the local ident table; And one comprise ID and the Q road special-purpose first phase table in Q road of phase information corresponding relation just; Be used for reading said parallel initial data from said output FIFO; In said local ident table, find corresponding ID according to the ID1 information content of I road initial data wherein, in the special-purpose first phase table in said Q road, find the corresponding first phase information of this ID according to this ID; Before the next flag of frame of Q road digital intermediate frequency signal, insert first phase according to this first phase information.
2. receiver as claimed in claim 1 is characterized in that:
Corresponding relation in the special-purpose first phase table in said local ident table of preserving in the said processor and said Q road is arranged according to the size order of ID; When said processor is searched said ID according to the said ID1 information content, and when searching said phase information just, adopt binary search to search according to said ID.
3. receiver as claimed in claim 1 is characterized in that, said memory comprises:
Dispatch circuit, receive FIFO one to one with each road digital intermediate frequency signal respectively;
Said reception FIFO is used for the pairing digital intermediate frequency signal of buffer memory;
Said dispatch circuit is used for when a digital intermediate frequency signal that receives the FIFO buffer memory is complete frame data, sending into said viterbi decoder continuously with the digital intermediate frequency signal that high-frequency clock will be buffered among this reception FIFO.
4. receiver as claimed in claim 3 is characterized in that:
Said dispatch circuit also is used for after the initial data that full 1 frame of said output FIFO buffer memory walks abreast, sending interrupt requests to said processor;
After said processor is received said interrupt requests, from said output FIFO, read said parallel initial data.
5. receiver as claimed in claim 3 is characterized in that:
Said reception FIFO is 12, I, the Q two-way digital intermediate frequency signal of respectively corresponding 6 wave beams.
6. receiver as claimed in claim 1 is characterized in that, said memory comprises:
One or more memory cell, corresponding one by one with the wave beam that is received respectively;
Each memory cell comprises respectively: register, timer;
RAM, be used to preserve I, the Q two-way digital intermediate frequency signal of corresponding wave beam;
First control unit, be used for corresponding wave beam I, Q two-way digital intermediate frequency signal a road write said RAM earlier, again another road is write said RAM; When I, Q two-way are respectively write full 1 frame data; Produce an interrupt signal and start said timer; With I, the Q two-way digital intermediate frequency signal of corresponding wave beam be temporarily stored in earlier in the said register, up to said timer then after with said register in temporary data write said RAM;
Second control unit is used for when receiving said interrupt signal, from said RAM, reads I, Q two-way digital intermediate frequency signal, sends into said viterbi decoder; When said timer stops to read then.
7. receiver as claimed in claim 6 is characterized in that:
Said timer duration regularly is 2.5ms.
8. like each described receiver in the claim 1 to 7, it is characterized in that said viterbi decoder comprises:
The logical sequence control unit is used to produce the logical sequence control signal;
The normalized decision unit is used to receive the branch metric maximum, produces the normalization control signal;
Transfering state storage RAM is used to receive said logical sequence control signal and said normalization control signal, produces current status data;
Local code and succeeding state generation unit are used to receive said current status data, produce the succeeding state data and read in the address as the probability accumulated value, and produce 0 branch road, 1 circuit-switched data;
Data processing unit is used to receive the said digital intermediate frequency signal of sending into, said 0 branch road, 1 circuit-switched data and current branch road probability accumulated value, produces succeeding state and chooses indication, said branch metric maximum and 0 branch road, 1 branch road probability accumulated value;
The succeeding state processing unit is used to receive said succeeding state data and succeeding state and chooses indication, produces the probability accumulated value and writes the address;
Probability is measured the accumulated value unit, is used to receive said 0 branch road, 1 branch road probability accumulated value, branch metric maximum, the probability accumulated value writes the address and the probability accumulated value reads in the address, produces said current branch road probability accumulated value;
The error code decision unit is used to receive said current status data, produces the initial data of serial;
The Error detection unit is used for according to said current status data and the said digital intermediate frequency signal that received, output error code number.
9. receiver as claimed in claim 8 is characterized in that, said data processing unit comprises:
Probability is measured the generation subelement, is used to receive the said digital intermediate frequency signal of sending into, and produces four groups of probable values, is respectively 00 attitude, 01 attitude, 10 attitudes and 11 attitudes;
Branch metric produces subelement, is used to receive said four groups of probable values, and said 0 branch road, 1 circuit-switched data, produces 0 branch road, 1 branch road branch metric value;
Branch metric is chosen and probability adds up subelement is used to receive said 0 branch road, 1 branch road branch metric value and said current branch road probability accumulated value, produces succeeding state and chooses indication, said branch metric maximum and 0 branch road, 1 branch road probability accumulated value.
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| CN104917560B (en) * | 2015-05-12 | 2018-06-05 | 北京九天利建信息技术股份有限公司 | Beidou communication satellite multi-beam multi-user supervises receiving apparatus and method |
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| CN106936447A (en) * | 2017-01-12 | 2017-07-07 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | The method of multichannel time division multiplex folding coding |
| CN115630537B (en) * | 2022-12-21 | 2023-03-28 | 长沙北斗产业安全技术研究院股份有限公司 | Navigation signal simulation method and system based on-chip simulation |
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