CN101839984A - Navigational satellite signal receiver - Google Patents
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Abstract
The invention relates to an antenna of a navigational satellite signal receiving machine, which comprises an antenna, a radio frequency front end module and a base band processing module, wherein the antenna is used for receiving one or a plurality of wave beams of navigational satellite signals, the radio frequency front end module is used for converting each wave beam of navigational satellite signals received by the antenna into two paths of middle frequency digital signals: path I and path Q, the base band processing module is used for carrying out base band signal processing on the middle frequency digital signals to obtain original data, the base band processing module concretely comprises a memory and a viterbi decoder, the memory is used for storing each path of middle frequency digital signals, when a path of stored middle frequency digital signals is a complete frame of data, the complete frame of data is sent into the viterbi decoder, and the viterbi decoder is used for decoding the sent data to obtain serial original data. The invention can realize the simultaneous receiving of a plurality of wave beams of signals, and in addition, the cost can not be greatly increased.
Description
Technical field
The present invention relates to navigation field, be specifically related to a kind of navigational satellite signal receiver.
Background technology
Navigational satellite signal receiver is a kind of downgoing signal that is used to receive Navsat (as satellite of the Big Dipper), extract location, the communication of the affiliated subscriber computer of modulating in the signal of subordinate user and the broadcasting of setting off etc. for information about, and this information is outputed to the external data disposal system be decrypted processing, the equipment of submitting to the user to use.
Scale fpga chip in the general use of existing receiver, can't realize receiving simultaneously a plurality of beam signals, such as the Big Dipper 3 satellites are arranged for No. one, totally 6 beam signals, according to prior art,, then need to strengthen the Base-Band Processing ability if receive simultaneously, if but used more massive fpga chip, the cost of receiver then could be increased greatly.
In addition, existing receiver can't be supervised location, the communication information of receiving 100 above subordinate users.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of navigational satellite signal receiver, receives when can realize a plurality of beam signal, and can not increase cost greatly.
In order to address the above problem, the invention provides a kind of navigational satellite signal receiver, comprising:
Antenna is used to receive the navigation satellite signal of one or more wave beams;
RF front-end module, the navigation satellite signal that is used for each wave beam that antenna is received is converted to I, Q two-way digital intermediate frequency signal;
Baseband processing module is used for described digital intermediate frequency signal is carried out base band signal process, obtains raw data;
Described baseband processing module specifically comprises:
Storer, viterbi decoder, serial-parallel conversion circuit and output FIFO;
Described storer is used to preserve each road digital intermediate frequency signal, and when the road digital intermediate frequency signal of being preserved was complete frame data, the frame data that this is complete were sent into described viterbi decoder;
Described viterbi decoder be used to the decode data sent into obtain the raw data of serial.
Further, described baseband processing module also comprises: serial-parallel conversion circuit and output FIFO;
Described serial-parallel conversion circuit is used for converting the raw data of the serial of described viterbi decoder output to parallel raw data, is buffered among the described output FIFO;
Described receiver also comprises:
Processor, prestore a local ident table that comprises ID and ID1 information content corresponding relation, and one comprise ID and the Q road special-purpose first phase table in Q road of phase information corresponding relation just, be used for reading described parallel raw data from described output FIFO, in described local ident table, find corresponding ID according to the ID1 information content of I road raw data wherein, in the special-purpose first phase table in described Q road, find the first phase information of this ID correspondence according to this ID; Before the next flag of frame of Q road digital intermediate frequency signal, insert first phase according to this first phase information.
Further, the corresponding relation in the special-purpose first phase table in described local ident table of preserving in the described processor and described Q road is arranged according to the size order of ID; When described processor is searched described ID according to the described ID1 information content, and when searching described phase information just, adopt binary search to search according to described ID.
Further, described storer comprises:
Dispatch circuit, receive FIFO one to one with each road digital intermediate frequency signal respectively;
Described reception FIFO is used for the pairing digital intermediate frequency signal of buffer memory;
Described dispatch circuit is used for sending into described viterbi decoder continuously with the digital intermediate frequency signal that high-frequency clock will be buffered among this reception FIFO when a digital intermediate frequency signal that receives the FIFO buffer memory is complete frame data.
Further, described receiver also comprises: processor;
Described dispatch circuit also is used for sending interrupt request to described processor after the raw data that full 1 frame of described output FIFO buffer memory walks abreast;
After described processor is received described interrupt request, from described output FIFO, read described parallel raw data.
Further, described reception FIFO is 12, I, the Q two-way digital intermediate frequency signal of respectively corresponding 6 wave beams.
Further, described storer comprises:
One or more storage unit, corresponding one by one with the wave beam that is received respectively;
Each storage unit comprises respectively: register, timer;
RAM, be used to preserve I, the Q two-way digital intermediate frequency signal of corresponding wave beam;
First control module, be used for corresponding wave beam I, Q two-way digital intermediate frequency signal a road write described RAM earlier, again another road is write described RAM; When I, Q two-way are respectively write full 1 frame data, produce a look-at-me and start described timer, with I, the Q two-way digital intermediate frequency signal of corresponding wave beam be temporarily stored in earlier in the described register, up to described timer then after with described register in temporary data write described RAM;
Second control module is used for when receiving described look-at-me, reads I, Q two-way digital intermediate frequency signal from described RAM, sends into described viterbi decoder; When described timer stops to read then.
Further, described timer duration regularly is 2.5ms.
Further, described viterbi decoder comprises:
The logical sequence control module is used to produce the logical sequence control signal;
The normalized decision unit is used to receive the branch metric maximal value, produces the normalization control signal;
Transfering state storage RAM is used to receive described logical sequence control signal and described normalization control signal, produces current status data;
Local code and succeeding state generation unit are used to receive described current status data, produce the succeeding state data and read in the address as the probability accumulated value, and produce 0 branch road, 1 circuit-switched data;
Data processing unit is used to receive the described digital signal of sending into, described 0 branch road, 1 circuit-switched data and current branch road probability accumulated value, produces succeeding state and chooses indication, described branch metric maximal value and 0 branch road, 1 branch road probability accumulated value;
The succeeding state processing unit is used to receive described succeeding state data and succeeding state and chooses indication, produces the probability accumulated value and writes the address;
Probability is measured the accumulated value unit, is used to receive described 0 branch road, 1 branch road probability accumulated value, branch metric maximal value, the probability accumulated value writes the address and the probability accumulated value reads in the address, produces described current branch road probability accumulated value;
The error code decision unit is used to receive described current status data, produces the raw data of serial;
The Error detection unit is used for according to described current status data and the described digital signal that received, output error code number.
Further, described data processing unit comprises:
Probability is measured the generation subelement, is used to receive the described digital signal of sending into, and produces four groups of probable values, is respectively 00 attitude, 01 attitude, 10 attitudes and 11 attitudes;
Branch metric produces subelement, is used to receive described four groups of probable values, and described 0 branch road, 1 circuit-switched data, produces 0 branch road, 1 branch road branch metric value;
Branch metric is chosen and probability adds up subelement is used to receive described 0 branch road, I branch road branch metric value and described current branch road probability accumulated value, produces succeeding state and chooses indication, described branch metric maximal value and 0 branch road, 1 branch road probability accumulated value.
One embodiment of the present of invention comprise following advantage at least: viterbi decoder is carried out time division multiplex, can realize the reception of a plurality of wave beams under the situation that does not change processing power; Such as with 6 I branch roads of 6 wave beams of a viterbi decoder IP kernel, 6 the Q branch roads viterbi decoder of totally 12 road signals, thereby can on middle scale fpga chip, realize receiving in 6 beam signals of 3 satellites.An alternative embodiment of the invention comprises following advantage at least: improved the efficient of searching Q road first phase, thereby can support 1000 above subordinate users' location, the communication information.
Description of drawings
Fig. 1 carries out the schematic flow sheet that Q road first phase is inserted for the processor of the navigational satellite signal receiver of embodiment one;
Fig. 2 is the synoptic diagram of baseband processing module of the navigational satellite signal receiver of embodiment one;
Fig. 3 is the synoptic diagram of viterbi decoder of the navigational satellite signal receiver of embodiment one;
Fig. 4 is the synoptic diagram of the RAM in the baseband processing module of navigational satellite signal receiver of embodiment one.
Embodiment
Below in conjunction with drawings and Examples technical scheme of the present invention is described in detail.
Embodiment one, and a kind of navigational satellite signal receiver comprises:
Antenna, RF front-end module, and baseband processing module;
Described antenna is used to receive the navigation satellite signal of one or more wave beams;
Described RF front-end module is used for the navigation satellite signal of each wave beam of antenna reception is converted to I, Q two-way digital intermediate frequency signal;
Described baseband processing module is used for described digital intermediate frequency signal is carried out base band signal process, obtains raw data.
Described baseband processing module is caught signal, follows the tracks of, and despreading, the scheme of demodulation can repeat no more herein by existing techniques in realizing.
In the present embodiment, described baseband processing module specifically can comprise:
Storer, viterbi decoder;
Described storer is used to preserve each road digital intermediate frequency signal, and when the road digital intermediate frequency signal of being preserved was complete frame data, the frame data that this is complete were sent into described viterbi decoder;
Described viterbi decoder be used to the decode data sent into obtain the raw data of serial.
In the present embodiment, described baseband processing module can also comprise: serial-parallel conversion circuit and output FIFO (first-in first-out register);
Described serial-parallel conversion circuit is used for converting the raw data of the serial of described viterbi decoder output to parallel raw data, is buffered among the described output FIFO;
Described navigational satellite signal receiver can further include processor.
In the present embodiment, described baseband processing module can but be not limited to FPGA; Described processor can but be not limited to CPU.
According to the exit signal format protocol of " No. one, the Big Dipper " system, departures Q adopts Gold sequence spread spectrum technology in the road, requires the real-time Q of realization road Gold sequence first phase to insert treatment technology.
Described processor prestores a local ident table that comprises ID and ID1 information content corresponding relation, and one comprise ID and the Q road special-purpose first phase table in Q road of phase information corresponding relation just, be used for reading described parallel raw data from described output FIFO, in described local ident table, find corresponding ID according to the ID1 information content of I road raw data wherein, in the special-purpose first phase table in described Q road, find the first phase information of this ID correspondence according to this ID; Before the next flag of frame of Q road digital intermediate frequency signal, insert first phase according to this first phase information.
In the present embodiment, the corresponding relation in the special-purpose first phase table in described local ident table of preserving in the described processor and described Q road is arranged according to the size order of ID; When described processor is searched described ID according to the described ID1 information content, and when searching described phase information just, adopt binary search to search according to described ID.
In the practical application, also can adopt Hash table to search or other mode of searching realizes.
The processing that just is complementary has the requirement of high speed hard real-time, and total duration of the single job of inserting from I road Viterbi decoding to first phase is not more than the correlation demodulation time of the frame synchronization head of 13bit, counts 812.5us.Wherein, the time overhead of finishing I road Viterbi decoding is about 188us, and the time that can be used for just being complementary is 624.5us.Processor prop up from I obtain id information the circuit-switched data after, classical lookup method such as can adopt that binary search or Hash table are searched can find ID number pairing first phase of coupling in the short time, and insert Q road PN sign indicating number generator.The response time that processor interrupts is less than 100us, binary search only need just be searched for 10 times can search for 1000 user ID information, to be far smaller than 624.5us from interrupt response to inserting the used time of Q road first phase, thereby realize at least 1000 users' the real-time search matched of ID.
In the concrete example, described processor carries out flow process that Q road first phase inserts as shown in Figure 1, may further comprise the steps:
101,1000 user ID of initialization;
102, wait for I branch road data interruption;
103, carry out the data parsing of I branch road;
104, judge whether the ID that I props up in the circuit-switched data has occurrence; If have, then carry out step 105; If no, then carry out step 109;
105, local ident is searched, and obtains corresponding first phase information;
106, the first phase information that will obtain is inserted GOLD sign indicating number generator;
107, wait for Q branch road data interruption;
108, carry out the data parsing of Q branch road;
109, carry out other processing; Return step 102.
Because this reception function receives I, the Q of 6 wave beams simultaneously and props up circuit-switched data, and all customer data of satellite system all sends from I, the Q branch road of 6 wave beams, this receiver also receives problem with regard to having solved 1000 user's data in the ID real-time searching that has solved 1000 users.
In an embodiment of the present embodiment, described storer specifically can comprise:
Dispatch circuit, receive FIFO one to one with each road digital intermediate frequency signal respectively;
Described reception FIFO is used for the pairing digital intermediate frequency signal of buffer memory;
Described dispatch circuit is used for sending into described viterbi decoder continuously with the digital intermediate frequency signal that high-frequency clock will be buffered among this reception FIFO when a digital intermediate frequency signal that receives the FIFO buffer memory is complete frame data.
When described receiver comprised processor, described dispatch circuit can also be further used for sending interrupt request to described processor after the raw data that full 1 frame of described output FIFO buffer memory walks abreast, and notification processor is read described parallel raw data;
After described processor is received described interrupt request, from described output FIFO, read described parallel raw data.
Baseband processing module in object lesson of this embodiment as shown in Figure 2, in this example, described reception FIFO is 12, is respectively applied for the I that preserves 6 wave beams, Q two-way totally 12 road digital intermediate frequency signals; The reception FIFO of the I road part of only having drawn among Fig. 2, the structure of Q road part and I road part are similar, do not draw in Fig. 2.
In the another kind of embodiment of present embodiment, described storer specifically can comprise:
One or more storage unit, corresponding one by one with the wave beam that is received respectively;
Each storage unit comprises respectively as shown in Figure 3:
Register (not drawing among Fig. 3), timer (not drawing among Fig. 3);
RAM, be used to preserve I, the Q two-way digital intermediate frequency signal of corresponding wave beam;
First control module, control RAM writes clock and write address, be used for corresponding wave beam I, Q two-way digital intermediate frequency signal a road write described RAM earlier, again another road is write described RAM; When I, Q two-way are respectively write full 1 frame data, produce a look-at-me and start described timer, with I, the Q two-way digital intermediate frequency signal of corresponding wave beam be temporarily stored in earlier in the described register, up to described timer then after with described register in temporary data write described RAM;
Second control module, control RAM reads clock and reads the address, is used for when receiving described look-at-me, reads I, Q two-way digital intermediate frequency signal from described RAM, sends into described viterbi decoder; When described timer stops to read then.
As seen, in this embodiment, frame data will produce interruption after all writing RAM, in the RAM that has no progeny change read states over to, read states continues about 2.5ms, and then changes the state of writing over to, so circulation.
Described timer can realize also that when practical application its function is the time control that will finish read states with timer or counter; Duration regularly can should be able to guarantee to have read I, each frame data of Q road according to experiment or experience setting; In the present embodiment, be preset as 2.5ms.Also independently timer can be set during practical application, carry out timing, stop to read after the time that arrival is preset, and notify described first control module to begin to write by second control module.
During practical application, described first control module can be integrated in the described radio-frequency (RF) front-end circuit, and second control module can be integrated in the described viterbi decoder.
Described first control module with I, when Q two-way digital intermediate frequency signal successively writes RAM because: I, the Q two paths of data arrives simultaneously, and both will be stored in the same block RAM, two paths of data must be write the moment of RAM and stagger, and clash with the moment of avoiding writing RAM.
In this embodiment,, therefore, can not carry out read and write simultaneously to RAM owing to be difficult to adopt the dual port RAM form; The serial data that receives is successively to arrive, and the time interval of writing RAM will be carried out read operation to RAM less than 1ms, can only carry out in writing the gap of RAM.RAM storage I, each 1 frame data of Q two-way are supposed totally 64 bytes, have whenever deposited 64 bytes and have provided a look-at-me, notify described viterbi decoder to read; But in the time less than 1ms, described viterbi decoder can not all run through this 64 byte.Therefore, RAM changes read states over to after providing look-at-me, read states will keep more than the 2ms, the digital intermediate frequency signal that arrives within many times at this 2ms is stored in the register earlier, after running through, again it is write RAM, I, Q two-way respectively have two bytes temporarily to deposit register in, and like this, the time of reading RAM that vacates is more than 2.5ms.
In the present embodiment, described viterbi decoder adopts large-scale integration technology, as shown in Figure 4, specifically can comprise:
The logical sequence control module is used to produce the logical sequence control signal;
The normalized decision unit is used to receive the branch metric maximal value, produces the normalization control signal;
Transfering state storage RAM is used to receive described logical sequence control signal and described normalization control signal, produces current status data;
Local code and succeeding state generation unit are used to receive described current status data, produce the succeeding state data and read in the address as the probability accumulated value, and produce 0 branch road, 1 circuit-switched data;
Data processing unit is used to receive the described digital signal of sending into, described 0 branch road, 1 circuit-switched data and current branch road probability accumulated value, produces succeeding state and chooses indication, described branch metric maximal value and 0 branch road, 1 branch road probability accumulated value;
The succeeding state processing unit is used to receive described succeeding state data and succeeding state and chooses indication, produces the probability accumulated value and writes the address;
Probability is measured the accumulated value unit, is used to receive described 0 branch road, 1 branch road probability accumulated value, branch metric maximal value, the probability accumulated value writes the address and the probability accumulated value reads in the address, produces described current branch road probability accumulated value;
The error code decision unit is used to receive described current status data, produces the raw data of serial;
The Error detection unit is used for according to described current status data and the described digital signal that received, output error code number.
In the present embodiment, described data processing unit specifically can comprise:
Probability is measured the generation subelement, is used to receive the described digital signal of sending into, and produces four groups of probable values, is respectively 00 attitude, 01 attitude, 10 attitudes and 11 attitudes;
Branch metric produces subelement, is used to receive described four groups of probable values, and described 0 branch road, 1 circuit-switched data, produces 0 branch road, 1 branch road branch metric value;
Branch metric is chosen and probability adds up subelement is used to receive described 0 branch road, I branch road branch metric value and described current branch road probability accumulated value, produces succeeding state and chooses indication, described branch metric maximal value and 0 branch road, 1 branch road probability accumulated value.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection domain of claim of the present invention.
Claims (10)
1. navigational satellite signal receiver comprises:
Antenna is used to receive the navigation satellite signal of one or more wave beams;
RF front-end module, the navigation satellite signal that is used for each wave beam that antenna is received is converted to I, Q two-way digital intermediate frequency signal;
Baseband processing module is used for described digital intermediate frequency signal is carried out base band signal process, obtains raw data;
It is characterized in that described baseband processing module comprises:
Storer, viterbi decoder;
Described storer is used to preserve each road digital intermediate frequency signal, and when the road digital intermediate frequency signal of being preserved was complete frame data, the frame data that this is complete were sent into described viterbi decoder;
Described viterbi decoder be used to the decode data sent into obtain the raw data of serial.
2. receiver as claimed in claim 1 is characterized in that, also comprises: processor;
Described baseband processing module also comprises: serial-parallel conversion circuit and output FIFO;
Described serial-parallel conversion circuit is used for converting the raw data of the serial of described viterbi decoder output to parallel raw data, is buffered among the described output FIFO;
Described processor prestores a local ident table that comprises ID and ID1 information content corresponding relation, and one comprise ID and the Q road special-purpose first phase table in Q road of phase information corresponding relation just, be used for reading described parallel raw data from described output FIFO, in described local ident table, find corresponding ID according to the ID1 information content of I road raw data wherein, in the special-purpose first phase table in described Q road, find the first phase information of this ID correspondence according to this ID; Before the next flag of frame of Q road digital intermediate frequency signal, insert first phase according to this first phase information.
3. receiver as claimed in claim 2 is characterized in that:
Corresponding relation in the special-purpose first phase table in described local ident table of preserving in the described processor and described Q road is arranged according to the size order of ID; When described processor is searched described ID according to the described ID1 information content, and when searching described phase information just, adopt binary search to search according to described ID.
4. receiver as claimed in claim 1 is characterized in that, described storer comprises:
Dispatch circuit, receive FIFO one to one with each road digital intermediate frequency signal respectively;
Described reception FIFO is used for the pairing digital intermediate frequency signal of buffer memory;
Described dispatch circuit is used for sending into described viterbi decoder continuously with the digital intermediate frequency signal that high-frequency clock will be buffered among this reception FIFO when a digital intermediate frequency signal that receives the FIFO buffer memory is complete frame data.
5. receiver as claimed in claim 4 is characterized in that, also comprises: processor;
Described dispatch circuit also is used for sending interrupt request to described processor after the raw data that full 1 frame of described output FIFO buffer memory walks abreast;
After described processor is received described interrupt request, from described output FIFO, read described parallel raw data.
6. receiver as claimed in claim 4 is characterized in that:
Described reception FIFO is 12, I, the Q two-way digital intermediate frequency signal of respectively corresponding 6 wave beams.
7. receiver as claimed in claim 1 is characterized in that, described storer comprises:
One or more storage unit, corresponding one by one with the wave beam that is received respectively;
Each storage unit comprises respectively: register, timer;
RAM, be used to preserve I, the Q two-way digital intermediate frequency signal of corresponding wave beam;
First control module, be used for corresponding wave beam I, Q two-way digital intermediate frequency signal a road write described RAM earlier, again another road is write described RAM; When I, Q two-way are respectively write full 1 frame data, produce a look-at-me and start described timer, with I, the Q two-way digital intermediate frequency signal of corresponding wave beam be temporarily stored in earlier in the described register, up to described timer then after with described register in temporary data write described RAM;
Second control module is used for when receiving described look-at-me, reads I, Q two-way digital intermediate frequency signal from described RAM, sends into described viterbi decoder; When described timer stops to read then.
8. receiver as claimed in claim 7 is characterized in that:
Described timer duration regularly is 2.5ms.
9. as each described receiver in the claim 1 to 8, it is characterized in that described viterbi decoder comprises:
The logical sequence control module is used to produce the logical sequence control signal;
The normalized decision unit is used to receive the branch metric maximal value, produces the normalization control signal;
Transfering state storage RAM is used to receive described logical sequence control signal and described normalization control signal, produces current status data;
Local code and succeeding state generation unit are used to receive described current status data, produce the succeeding state data and read in the address as the probability accumulated value, and produce 0 branch road, 1 circuit-switched data;
Data processing unit is used to receive the described digital signal of sending into, described 0 branch road, 1 circuit-switched data and current branch road probability accumulated value, produces succeeding state and chooses indication, described branch metric maximal value and 0 branch road, 1 branch road probability accumulated value;
The succeeding state processing unit is used to receive described succeeding state data and succeeding state and chooses indication, produces the probability accumulated value and writes the address;
Probability is measured the accumulated value unit, is used to receive described 0 branch road, 1 branch road probability accumulated value, branch metric maximal value, the probability accumulated value writes the address and the probability accumulated value reads in the address, produces described current branch road probability accumulated value;
The error code decision unit is used to receive described current status data, produces the raw data of serial;
The Error detection unit is used for according to described current status data and the described digital signal that received, output error code number.
10. receiver as claimed in claim 9 is characterized in that, described data processing unit comprises:
Probability is measured the generation subelement, is used to receive the described digital signal of sending into, and produces four groups of probable values, is respectively 00 attitude, 01 attitude, 10 attitudes and 11 attitudes;
Branch metric produces subelement, is used to receive described four groups of probable values, and described 0 branch road, 1 circuit-switched data, produces 0 branch road, 1 branch road branch metric value;
Branch metric is chosen and probability adds up subelement is used to receive described 0 branch road, I branch road branch metric value and described current branch road probability accumulated value, produces succeeding state and chooses indication, described branch metric maximal value and 0 branch road, 1 branch road probability accumulated value.
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Cited By (7)
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| CN102096081A (en) * | 2010-12-14 | 2011-06-15 | 东莞市泰斗微电子科技有限公司 | Carrier wave and pseudo-random code stripping circuit |
| CN104407367A (en) * | 2014-12-19 | 2015-03-11 | 中国科学院重庆绿色智能技术研究院 | Device and method for improving baseband signal processing capacity of satellite navigation terminal receiver |
| CN104917560A (en) * | 2015-05-12 | 2015-09-16 | 北京九天利建信息技术有限公司 | Beidou communication satellite multi-beam and multi-user receiving monitoring device and method |
| CN105071974A (en) * | 2015-09-01 | 2015-11-18 | 四川九洲电器集团有限责任公司 | RDSS-based command management method of command terminal, and command terminal |
| CN106936447A (en) * | 2017-01-12 | 2017-07-07 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | The method of multichannel time division multiplex folding coding |
| CN115630537A (en) * | 2022-12-21 | 2023-01-20 | 长沙北斗产业安全技术研究院股份有限公司 | Navigation signal simulation method and system based on-chip simulation |
| CN117406249A (en) * | 2023-12-14 | 2024-01-16 | 成都安则优科技有限公司 | Anti-unmanned aerial vehicle satellite navigation equipment and data playback method |
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| CN102096081A (en) * | 2010-12-14 | 2011-06-15 | 东莞市泰斗微电子科技有限公司 | Carrier wave and pseudo-random code stripping circuit |
| CN102096081B (en) * | 2010-12-14 | 2012-10-03 | 东莞市泰斗微电子科技有限公司 | Carrier wave and pseudo-random code stripping circuit |
| CN104407367A (en) * | 2014-12-19 | 2015-03-11 | 中国科学院重庆绿色智能技术研究院 | Device and method for improving baseband signal processing capacity of satellite navigation terminal receiver |
| CN104917560A (en) * | 2015-05-12 | 2015-09-16 | 北京九天利建信息技术有限公司 | Beidou communication satellite multi-beam and multi-user receiving monitoring device and method |
| CN104917560B (en) * | 2015-05-12 | 2018-06-05 | 北京九天利建信息技术股份有限公司 | Beidou communication satellite multi-beam multi-user supervises receiving apparatus and method |
| CN105071974A (en) * | 2015-09-01 | 2015-11-18 | 四川九洲电器集团有限责任公司 | RDSS-based command management method of command terminal, and command terminal |
| CN105071974B (en) * | 2015-09-01 | 2019-01-11 | 四川九洲电器集团有限责任公司 | The method and command terminal of command terminal command and management based on RDSS |
| CN106936447A (en) * | 2017-01-12 | 2017-07-07 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | The method of multichannel time division multiplex folding coding |
| CN115630537A (en) * | 2022-12-21 | 2023-01-20 | 长沙北斗产业安全技术研究院股份有限公司 | Navigation signal simulation method and system based on-chip simulation |
| CN117406249A (en) * | 2023-12-14 | 2024-01-16 | 成都安则优科技有限公司 | Anti-unmanned aerial vehicle satellite navigation equipment and data playback method |
| CN117406249B (en) * | 2023-12-14 | 2024-03-08 | 成都安则优科技有限公司 | Anti-unmanned aerial vehicle satellite navigation equipment and data playback method |
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| CN101839984B (en) | 2012-10-10 |
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