CN101826530A - Homeotropic alignment type pixel structure and manufacturing method thereof - Google Patents
Homeotropic alignment type pixel structure and manufacturing method thereof Download PDFInfo
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- CN101826530A CN101826530A CN200910004546A CN200910004546A CN101826530A CN 101826530 A CN101826530 A CN 101826530A CN 200910004546 A CN200910004546 A CN 200910004546A CN 200910004546 A CN200910004546 A CN 200910004546A CN 101826530 A CN101826530 A CN 101826530A
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Abstract
The invention relates to a homeotropic alignment type pixel structure and a manufacturing method thereof. The pixel structure comprises a gate, a gate insulation layer, a gate amorphous silicon area, a source metal area, a drain metal area, an organic matter protective layer, a conducting layer and slits, wherein the gate is formed on a base plate; the gate insulation layer covers on the gate; the gate amorphous silicon area is formed on the gate insulation layer and is correspondingly positioned above the gate; the source metal area and the drain metal area are formed on the gate amorphous silicon area; the organic matter protective layer is formed on the gate insulation layer and covers on the source metal area and the drain metal area and comprises a dielectric layer hole and a plurality of bulges, and the dielectric layer hole exposes the partial surface of the drain metal area; the conducting layer is formed on the organic matter protective layer and covers on the dielectric layer hole; and the slits are formed among the bulges. The invention prevents from forming the bulges on an amorphous silicon layer as a base by forming the bulges on the organic matter protective layer, thereby reducing the light leakage current garneted by a thin film transistor.
Description
Technical field
The invention relates to a kind of homeotropic alignment type pixel structure and manufacture method thereof, particularly about a kind of homeotropic alignment type pixel structure and manufacture method thereof that reduces light leakage current.
Background technology
Social now multimedia technology is quite flourishing, is indebted to the progress of semiconductor element and display unit mostly.With regard to display, have that high image quality, space utilization efficient are good, the LCD of low consumpting power, advantageous characteristic such as radiationless becomes the main flow in market gradually.In order to allow LCD that better display quality is arranged, at present LCD all towards height contrast, no GTG reverse, characteristics such as colour cast is little, brightness is high, high color saturation, fast reaction and wide viewing angle develop.With the wide viewing angle technology, common for example have copline switching type liquid crystal display, stable twisted nematic LCD, a limit switching type liquid crystal display and a multiple domain vertical orientation type liquid crystal display etc.
Fig. 1 is the schematic diagram of known multidomain vertical alignment type dot structure.This dot structure comprises substrate 11, grid 12, gate insulator 13, grid amorphous silicon region 14, doped amorphous silicon district 15, source metal district 16, drain metal district 17, protective layer 18 and conductive layer 19.As can be known from Figure, pixel display area has slit 20 and a plurality of projection, and wherein projection is that substrate forms with amorphous silicon 14, has certain height in order to make projection, and then the thickness of amorphous silicon layer 14 can not be too thin, is approximately 0.2um to 0.3um.As everyone knows, amorphous silicon layer is a kind of photoactive substance in the liquid crystal pixel structure, behind irradiation, can produce light leakage current, because projection needs certain height in homeotropic alignment type pixel structure, therefore can correspondingly cause the thickness of grid amorphous silicon region 14 in the thin-film transistor to increase, cause thin-film transistor to produce light leakage current easily, and then pixel electrically caused bad influence.
Summary of the invention
In view of this, the invention provides a kind of homeotropic alignment type pixel structure and manufacture method thereof, to reduce the light leakage current that thin-film transistor produces.
According to purpose of the present invention, a kind of homeotropic alignment type pixel structure is provided, described dot structure comprises:
Grid is formed on the substrate;
Gate insulator, cover gate;
The grid amorphous silicon region is formed on the gate insulator and is positioned at grid top accordingly;
Source metal district and drain metal district are formed on the grid amorphous silicon region;
The organic substance protective layer is formed on the gate insulator and covers the source metal district and the drain metal district, and this organic substance protective layer comprises interlayer hole and a plurality of projection, and this interlayer hole exposes the part surface in drain metal district; With
Conductive layer is formed on the organic substance protective layer and covers interlayer hole, and forms slit between organic projection.
Further comprise the doping grid amorphous silicon region between described source metal district, drain metal district and the grid amorphous silicon region.
The area of described grid amorphous silicon region is greater than the area of the grid that is positioned at the below.
The organic substance of described organic substance protective layer is a phenolic resins.
Described conductive layer is an indium tin oxide layer.
According to purpose of the present invention, a kind of manufacture method of homeotropic alignment type pixel structure is provided, described one pixel structure process method comprises:
Form grid on substrate;
Form gate insulator with cover gate;
Form the grid amorphous silicon region on gate insulator and be positioned at the grid top accordingly;
Form source metal district, drain metal district in the top of gate insulator;
Form the organic substance protective layer on gate insulator and cover source metal district, drain metal district;
Form interlayer hole and a plurality of organic substance protective layer place that is projected on, this interlayer hole exposes the part surface in drain metal district; With
The formation conductive layer is on the organic substance protective layer and cover interlayer hole, and forms slit between the projection of organic substance protective layer.
The step of described this grid of formation comprises: form the first metal layer on substrate; With
The patterning the first metal layer is to form grid.
The step of described formation grid amorphous silicon region comprises: form amorphous silicon layer on gate insulator;
Form doped amorphous silicon layer on amorphous silicon layer; And
Patterning doped amorphous silicon layer and amorphous silicon layer are to form doped amorphous silicon district and grid amorphous silicon region.
The step in described formation source metal district, drain metal district comprises:
Form the top of second metal level in gate insulator; And
Patterning second metal level is to form source metal district, drain metal district;
Wherein, has passage between source metal district and the drain metal district.
The step of described formation organic substance protective layer comprises: form the organic substance protective layer on gate insulator; And
Patterning organic substance protective layer to form a plurality of projections, forms the passage between smooth organic substance protective layer covering source metal district, drain metal district and source metal district and the drain metal district, forms interlayer hole to expose the part surface in drain metal district.
The step of described formation conductive layer comprises:
Form conductive layer on the organic substance protective layer and cover interlayer hole; And
Between the projection of organic substance protective layer, form slit.
Description of drawings
Fig. 1 is the schematic diagram of known multidomain vertical alignment type dot structure.
Fig. 2 A--2E is the schematic diagram of homeotropic alignment type pixel structure fabrication steps of the present invention.
Embodiment
Please refer to Fig. 2 A--2E, Fig. 2 A--2E is the schematic diagram of homeotropic alignment type pixel structure fabrication steps of the present invention.
Shown in Fig. 2 A, at first, provide substrate 21, and on substrate 21, form the first metal layer, then, the patterning the first metal layer is to form grid 22.
Please refer to Fig. 2 B, on the basis of Fig. 2 A, on substrate 21, form gate insulator 23 and cover gate 22 again.Then, on this gate insulator 23, form amorphous silicon layer, on amorphous silicon layer, form doped amorphous silicon layer again.Then, patterning amorphous silicon layer and doped amorphous silicon layer, forming grid amorphous silicon region 24 and doping grid amorphous silicon region 25, and grid amorphous silicon region 24 and doping grid amorphous silicon region 25 are positioned at grid 22 tops accordingly.
Then, please refer to Fig. 2 C, on the basis of Fig. 2 B, form second metal level, second metal level cover gate amorphous silicon region 24 and the doping grid amorphous silicon region 25.Patterning second metal level and doping grid amorphous silicon region 25 with formation source metal district 26, drain metal district 27, and have passage 28 between source metal district 26 and the drain metal district 27.
Please refer to Fig. 2 D, on the basis of Fig. 2 C, form the organic substance protective layer on the gate insulator 23 and cover passage 28 between source metal district 26, drain metal district 27 and source metal district 26 and the drain metal district 27.Then, form interlayer hole 30 and a plurality of projection 31 on organic substance protective layer 29, wherein interlayer hole 30 is in order to expose the part surface in drain metal district 27.The material of organic substance protective layer of the present invention is resin, for example phenolic resins.
At last, shown in Fig. 2 E, form conductive layer 32 on organic substance protective layer 29, conductive layer 32 covers interlayer hole 30 to electrically connect drain metal district 27 and pixel display area, and in addition, conductive layer 32 forms slit 33 between a plurality of projections 31.The material of conductive layer 32 for example is a tin indium oxide.
According to homeotropic alignment type pixel structure of the present invention, the projection 31 of pixel display area need not to do substrate with amorphous silicon and forms, the height of the thickness of the amorphous silicon layer 24 of thin-film transistor and the projection 31 of pixel display area does not have corresponding relation, solved in traditional homeotropic alignment type pixel structure because the requirement for height of pixel display area projection causes in the thin-film transistor thickness of amorphous silicon layer blocked up, caused thin-film transistor to produce the problem of light leakage current easily.Homeotropic alignment type pixel structure of the present invention can effectively reduce the phenomenon of light leakage current.
Claims (10)
1. homeotropic alignment type pixel structure, it is characterized in that: described dot structure comprises
Grid is formed on the substrate;
Gate insulator, cover gate;
The grid amorphous silicon region is formed on the gate insulator and is positioned at grid top accordingly;
Source metal district and drain metal district are formed on the grid amorphous silicon region;
The organic substance protective layer is formed on the gate insulator and covers the source metal district and the drain metal district, and this organic substance protective layer comprises interlayer hole and a plurality of projection, and this interlayer hole exposes the part surface in drain metal district; With
Conductive layer is formed on the organic substance protective layer and covers interlayer hole, and forms slit between described projection.
2. homeotropic alignment type pixel structure according to claim 1 is characterized in that: further comprise the doping grid amorphous silicon region between described source metal district, drain metal district and the grid amorphous silicon region.
3. homeotropic alignment type pixel structure according to claim 1 is characterized in that: the area of described grid amorphous silicon region is greater than the area of the grid that is positioned at the below.
4. homeotropic alignment type pixel structure according to claim 1 is characterized in that: the organic substance of described organic substance protective layer is a phenolic resins.
5. homeotropic alignment type pixel structure according to claim 1 is characterized in that: described conductive layer is an indium tin oxide layer.
6. the manufacture method of a homeotropic alignment type pixel structure, it is characterized in that: described one pixel structure process method comprises:
Form grid on substrate;
Form gate insulator with cover gate;
Form the grid amorphous silicon region on gate insulator and be positioned at the grid top accordingly;
Form source metal district, drain metal district in the top of gate insulator;
Form the organic substance protective layer on gate insulator and cover source metal district, drain metal district;
Form interlayer hole and a plurality of organic substance protective layer place that is projected on, this interlayer hole exposes the part surface in drain metal district; With
The formation conductive layer is on the organic substance protective layer and cover interlayer hole, and forms slit between the projection of organic protection layer.
7. manufacture method according to claim 6 is characterized in that, the step that forms grid comprises:
Form the first metal layer on substrate; With
The patterning the first metal layer is to form grid.
8. manufacture method according to claim 6 is characterized in that, the step that forms the grid amorphous silicon region comprises:
Form amorphous silicon layer on gate insulator;
Form doped amorphous silicon layer on amorphous silicon layer; And
Patterning doped amorphous silicon layer and amorphous silicon layer are to form doped amorphous silicon district and grid amorphous silicon region.
9. manufacture method according to claim 6 is characterized in that, the step that forms source metal district, drain metal district comprises:
Form the top of second metal level in gate insulator; And
Patterning second metal level is to form source metal district and drain metal district;
Wherein, has passage between source metal district and the drain metal district.
10. manufacture method according to claim 6 is characterized in that, the step that forms the organic substance protective layer comprises:
Form the organic substance protective layer on gate insulator; And
Patterning organic substance protective layer to form a plurality of projections, forms the passage between smooth organic substance protective layer covering source metal district, drain metal district and source metal district and the drain metal district, forms interlayer hole to expose the part surface in drain metal district;
The step of described formation conductive layer comprises:
Form conductive layer on the organic substance protective layer and cover interlayer hole; And
Between the projection of organic substance protective layer, form slit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910004546A CN101826530A (en) | 2009-03-05 | 2009-03-05 | Homeotropic alignment type pixel structure and manufacturing method thereof |
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| CN200910004546A CN101826530A (en) | 2009-03-05 | 2009-03-05 | Homeotropic alignment type pixel structure and manufacturing method thereof |
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| CN200910004546A Pending CN101826530A (en) | 2009-03-05 | 2009-03-05 | Homeotropic alignment type pixel structure and manufacturing method thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102522411A (en) * | 2011-12-22 | 2012-06-27 | 深圳莱宝高科技股份有限公司 | Thin film transistor, array substrate using thin film transistor and manufacturing method of array substrate |
| CN103403873A (en) * | 2011-03-02 | 2013-11-20 | 应用材料公司 | Offset electrode TFT structure |
| CN109254457A (en) * | 2014-11-12 | 2019-01-22 | 群创光电股份有限公司 | Display panel |
-
2009
- 2009-03-05 CN CN200910004546A patent/CN101826530A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103403873A (en) * | 2011-03-02 | 2013-11-20 | 应用材料公司 | Offset electrode TFT structure |
| CN103403873B (en) * | 2011-03-02 | 2016-08-10 | 应用材料公司 | offset electrode TFT structure |
| CN102522411A (en) * | 2011-12-22 | 2012-06-27 | 深圳莱宝高科技股份有限公司 | Thin film transistor, array substrate using thin film transistor and manufacturing method of array substrate |
| CN102522411B (en) * | 2011-12-22 | 2016-02-10 | 深圳莱宝高科技股份有限公司 | Thin film transistor (TFT), the array base palte using this thin film transistor (TFT) and preparation method thereof |
| CN109254457A (en) * | 2014-11-12 | 2019-01-22 | 群创光电股份有限公司 | Display panel |
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Application publication date: 20100908 |