CN101826460B - Dry etching method of semiconductor component - Google Patents
Dry etching method of semiconductor component Download PDFInfo
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- CN101826460B CN101826460B CN2009100468877A CN200910046887A CN101826460B CN 101826460 B CN101826460 B CN 101826460B CN 2009100468877 A CN2009100468877 A CN 2009100468877A CN 200910046887 A CN200910046887 A CN 200910046887A CN 101826460 B CN101826460 B CN 101826460B
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Abstract
The invention discloses a dry etching method of a semiconductor component, comprising the following steps of: sequentially forming an SiO2 layer, a low dielectric constant insulating material layer, a top layer, an Si-containing bottom antireflection layer and a photoresist layer on a silicon substrate material; etching on the Si-containing bottom antireflection layer and the photoresist layer, then etching on the top layer and the low dielectric constant insulating material layer and removing residues generated in the etching process; carrying out fluorine gas treatment on the etched and exposed top layer so that the low dielectric constant insulating material under the top layer is not etched at the same time of etching the top layer; and removing residues generated in the etching process of the top layer. By using the dry etching method of the semiconductor component, the problems of top contraction and arch-shaped profiles are solved, the formed top layer can be ensured to have better profile, and the electrical property of the semiconductor component can be greatly improved.
Description
Technical field
The present invention relates to the manufacturing technology of semiconductor components and devices, refer in particular to a kind of dry-etching method of semiconductor components and devices.
Background technology
In recent years, along with the develop rapidly of semiconductor components and devices manufacturing technology, dry ecthing (Dry Etch) technology has been widely used among the manufacturing process of semiconductor components and devices.For example, in the photoetching process of the effective coverage in the semiconductor element manufacturing technology (AA, Active Area), the general SiO that on the silicon base material, forms successively earlier
2(undoped silicon glass) layer, black diamond (BD; Black Diamond) low-k (Low-K) insulation material layer, top layer (Cap layer), contain the bottom anti-reflective (Si-BARC of Si; Bottom Anti-Reflective Coating) layer and photoresistance (PR; Photo Resist) layer carries out etching to said PR layer and Si-BARC layer earlier then, again top layer and black diamond low dielectric constant insulating material layer is carried out etching.Generally, said etching process to top layer and black diamond low dielectric constant insulating material layer is referred to as main etching (ME, Main Etch) process.Behind main etching process, remove the residue that is produced in (Strip) above-mentioned main etching process through various cleaning methods again.
But; When stating dry etching process in the use and carrying out etching; For example; In first metal connecting layer (M1) dry etching process of 45nm manufacturing technology,, thereby make the problem that in above-mentioned dry etching process, has top layer contraction (Cap layer Shrinkage) or arc profile (Bowing Profile) because top oxide is different with the etch-rate between each thin layer or low-k (Low-K) material.Fig. 1 is the effect sketch map of top layer profile of the prior art.As shown in Figure 1; Above-mentioned arc profile will cause the effective coverage less; And be difficult to carry out spacer deposition (BarrierDepositon) and be difficult to carry out electrochemistry electroplating (Electrical Chemical Plating) through physical vapor deposition (PVD), therefore will bring adverse influence to the electric property of semiconductor components and devices.
Summary of the invention
In view of this, main purpose of the present invention is to provide a kind of dry-etching method of semiconductor components and devices, and shrink at the top and the problem of arc profile thereby solve, and makes formed top layer have profile preferably.
For achieving the above object, the technical scheme among the present invention is achieved in that
A kind of dry-etching method of semiconductor components and devices, this method comprises:
On the silicon base material, form SiO successively
2Layer, low dielectric constant insulating material layer, top layer, the bottom anti-reflection layer that contains Si and photoresist layer;
After the bottom anti-reflection layer that contains Si and photoresist layer carried out etching, top layer and low dielectric constant insulating material layer are carried out etching, and remove the residue that produces in the etching process;
To handling, make and the advanced low-k materials under the top layer is not carried out etching in that top layer is carried out the etched while owing to the top layer that top layer and low dielectric constant insulating material layer are carried out exposing after the etching carries out fluorine gas;
The residue that removal is produced when top layer is carried out etching.
When top layer being carried out the fluorine gas processing, employed source power is 800～1500 watts, and employed deflection power is zero.
When top layer being carried out the fluorine gas processing, employed source power is 1000 watts.
When top layer being carried out the fluorine gas processing, use carbon monoxide or nitrogen as diluent gas.
When using carbon monoxide as diluent gas, the flow of said carbon monoxide is 300～400 standard ml/min.
When top layer being carried out the fluorine gas processing, use CF4 or CHF3 as etching gas.
When using CF4 as etching gas, the flow of said CF4 is 50～80 standard ml/min.
When using CF4 as etching gas, the flow of said CF4 is 60 standard ml/min.
When using carbon monoxide as diluent gas, and when using CF4 as etching gas, the ratio of the flow of CF4 and carbon monoxide is less than 0.2
To sum up can know, a kind of dry-etching method of semiconductor components and devices is provided among the present invention.In the dry-etching method of said semiconductor components and devices; Owing to after said main etching process, carried out above-mentioned fluorine gas processing, thereby solved the problem of top contraction and arc profile; Make formed top layer have profile preferably, can improve the electric property of semiconductor components and devices greatly.
Description of drawings
Fig. 1 is the effect sketch map of top layer profile of the prior art.
Fig. 2 is the schematic flow sheet of the dry-etching method of semiconductor components and devices among the present invention.
Fig. 3 is the effect sketch map of the top layer profile after the use fluorine gas processing method of the present invention.
Embodiment
For making the object of the invention, technical scheme and advantage express clearlyer, the present invention is remake further detailed explanation below in conjunction with accompanying drawing and specific embodiment.
Fig. 2 is the schematic flow sheet of the dry-etching method of semiconductor components and devices among the present invention.As shown in Figure 2, the dry-etching method of the semiconductor components and devices that is provided among the present invention comprises the step that is described below:
In this step, said low dielectric constant insulating material layer is the dielectric layer that is formed by the dielectric material with lower dielectric constant K.In semiconductor fabrication process commonly used, the K value of Low-K material can approximate 3; Generally, the K value of Low-K material generally all is less than or equal to 2.8.In technical scheme of the present invention, described low dielectric constant insulating material layer can be a black diamond low dielectric constant insulating material layer.
In this step, at first said PR layer and Si-BARC layer are carried out etching, and then top layer and black diamond low dielectric constant insulating material layer are carried out etching.Generally, said etching process to top layer and low dielectric constant insulating material layer is referred to as main etching (ME, Main Etch) process.Behind main etching process, remove the residue that is produced in (Strip) above-mentioned etching process through various cleaning methods again.In this step, said to PR layer and Si-BARC with carry out etching, and carry out main etching process, all can use etching technique or method commonly used in this area to carry out etching, concrete etching technique or method repeat no more at this.
In this step, will handle carry out fluorine gas owing to the top layer that carries out exposing after the above-mentioned etching, make and the advanced low-k materials under the top layer is not carried out etching in that top layer is carried out the etched while.Said fluorine gas processing method is a kind of plasma-etching method, and said fluorine gas processing method can have the characteristics of the following stated:
1) employed source power (Source Power) is higher, but employed deflection power (BiasPower) is zero, does not promptly use deflection power.Wherein, high source power can be bigger so that be used for etched ion concentration, can improve the etch-rate to top layer; Simultaneously because deflection power is 0, then the ion bombardment effect of plasma a little less than, thereby make and can effectively must carry out etching top layer, and can not carry out etching to the advanced low-k materials under the top layer.
In technical scheme of the present invention, employed source power can be for 800～1500 watts (W), and preferable, employed source power is 1000W.
2) use carbon monoxide (CO) or nitrogen (N
2) as diluent gas (Dilute gas).
In the prior art, generally use argon gas (Ar) or helium (He) as diluent gas, but in technical scheme of the present invention, will not use Ar or He, and use CO or N
2As diluent gas, thus can effectively improve top layer to the selection of the advanced low-k materials under the top layer than (being the ratio of etch-rate), make in etching process etch-rate to top layer greater than etch-rate to the advanced low-k materials under the top layer.Preferable, in technical scheme of the present invention, employed diluent gas is CO, the flow of said CO is 300～400 standard ml/min (sccm); Preferable, the flow of said CO is 300sccm.
3) use CF
4Or CHF
3As etching gas,, promptly improve the selection ratio of top layer to the advanced low-k materials under the top layer because therefore the content of fluorine can effectively improve the selection ratio of oxide to advanced low-k materials than higher in the above-mentioned etching gas.In technical scheme of the present invention, employed etching gas is CF
4, said CF
4Flow be 50～80sccm; Preferable, said CF
4Flow be 60sccm.In addition, when using CO, and use CF as diluent gas
4During as etching gas, CF
4With the ratio of the flow of CO less than 0.2.
In technical scheme of the present invention, described fluorine gas processing method can only have characteristics 1), also can only have characteristics 1) and 2) or only have characteristics 1) and 3).
In technical scheme of the present invention, can remove through cleaning method commonly used in this area or other processing method and above-mentioned top layer carried out the residue in the etching process, repeat no more at this.
Fig. 3 is the effect sketch map of the top layer profile after the use fluorine gas processing method of the present invention.As shown in Figure 3, state the fluorine gas processing method in the use after, the problem that top layer shrinks (Cap layer shrinkage) and arc profile (Bowing profile) has obtained very big improvement, formed top layer has profile preferably.
To sum up can know; In the dry-etching method of above-mentioned semiconductor components and devices provided by the present invention; Owing to after said main etching process, carried out above-mentioned fluorine gas processing, thereby solved the problem of top contraction and arc profile; Make formed top layer have profile preferably, can improve the electric property of semiconductor components and devices greatly.
The above is merely preferred embodiment of the present invention, is not to be used to limit protection scope of the present invention.All within spirit of the present invention and principle, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. the dry-etching method of a semiconductor components and devices is characterized in that, this method comprises:
On the silicon base material, form SiO successively
2Layer, low dielectric constant insulating material layer, top layer, the bottom anti-reflection layer that contains Si and photoresist layer;
After photoresist layer and the bottom anti-reflection layer that contains Si carried out etching, top layer and low dielectric constant insulating material layer are carried out etching, and the residue that produces in the removal etching process;
To handling, make and the advanced low-k materials under the top layer is not carried out etching in that top layer is carried out the etched while owing to the top layer that top layer and low dielectric constant insulating material layer are carried out exposing after the etching carries out fluorine gas;
The residue that removal is produced when top layer is carried out etching.
2. method according to claim 1 is characterized in that:
When top layer being carried out the fluorine gas processing, employed source power is 800～1500 watts, and employed deflection power is zero.
3. method according to claim 2 is characterized in that:
When top layer being carried out the fluorine gas processing, employed source power is 1000 watts.
4. method according to claim 1 is characterized in that:
When top layer being carried out the fluorine gas processing, use carbon monoxide or nitrogen as diluent gas.
5. method according to claim 4 is characterized in that:
When using carbon monoxide as diluent gas, the flow of said carbon monoxide is 300～400 standard ml/min.
6. according to claim 1 or 4 described methods, it is characterized in that:
When top layer being carried out the fluorine gas processing, use CF
4Or CHF
3As etching gas.
7. method according to claim 6 is characterized in that:
When using CF
4During as etching gas, said CF
4Flow be 50～80 standard ml/min.
8. method according to claim 6 is characterized in that:
When using CF
4During as etching gas, said CF
4Flow be 60 standard ml/min.
9. method according to claim 6 is characterized in that:
When using carbon monoxide, and use CF as diluent gas
4During as etching gas, CF
4With the ratio of the flow of carbon monoxide less than 0.2.
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| CN2009100468877A CN101826460B (en) | 2009-03-02 | 2009-03-02 | Dry etching method of semiconductor component |
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|---|---|---|---|
| CN2009100468877A CN101826460B (en) | 2009-03-02 | 2009-03-02 | Dry etching method of semiconductor component |
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| CN101826460B true CN101826460B (en) | 2012-03-21 |
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| CN105590873B (en) * | 2015-12-23 | 2018-07-03 | 苏州工业园区纳米产业技术研究院有限公司 | A kind of preparation method of dry etching convex block morphology controllable |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200534429A (en) * | 2004-04-14 | 2005-10-16 | Taiwan Semiconductor Mfg | Dual damascene structure formed of low-k dielectric materials |
| JP2006032568A (en) * | 2004-07-14 | 2006-02-02 | Nec Electronics Corp | Dry etching method and manufacturing method of semiconductor device |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200534429A (en) * | 2004-04-14 | 2005-10-16 | Taiwan Semiconductor Mfg | Dual damascene structure formed of low-k dielectric materials |
| JP2006032568A (en) * | 2004-07-14 | 2006-02-02 | Nec Electronics Corp | Dry etching method and manufacturing method of semiconductor device |
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