CN101808462A - Wiring board and preparation method thereof - Google Patents

Wiring board and preparation method thereof Download PDF

Info

Publication number
CN101808462A
CN101808462A CN200910009506A CN200910009506A CN101808462A CN 101808462 A CN101808462 A CN 101808462A CN 200910009506 A CN200910009506 A CN 200910009506A CN 200910009506 A CN200910009506 A CN 200910009506A CN 101808462 A CN101808462 A CN 101808462A
Authority
CN
China
Prior art keywords
activation
layer
insulating barrier
wiring board
conductive pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN200910009506A
Other languages
Chinese (zh)
Other versions
CN101808462B (en
Inventor
余丞博
黄瀚霈
张启民
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xinxing Electronics Co Ltd
Original Assignee
Xinxing Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xinxing Electronics Co Ltd filed Critical Xinxing Electronics Co Ltd
Priority to CN2009100095068A priority Critical patent/CN101808462B/en
Publication of CN101808462A publication Critical patent/CN101808462A/en
Application granted granted Critical
Publication of CN101808462B publication Critical patent/CN101808462B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Abstract

The invention relates to a wiring board and a preparation method thereof. The preparation method of the wiring board comprises forming at least one initial insulation layer on a substrate, then performing an activating program to change the initial insulation layer to an activating insulation layer, wherein the activating insulation layer has a surface and an activating area arranged on the surface and contains a plurality of catalyst particles and some catalyst particles are exposed in the activating area; then forming a conductive pattern layer in the activating area, wherein the conductive pattern layer protrudes out of the surface. The wiring board of the invention is prepared by the preparation method.

Description

Wiring board and manufacture method thereof
Technical field
The invention relates to a kind of wiring board (wiring board) and manufacture method thereof, and particularly relevant for a kind of wiring board and manufacture method thereof with activation insulating barrier (activable insulation layer).
Background technology
Wiring board is the needed elements of electrical home appliances such as electronic installations (electronic device) such as mobile phone, computer and digital still camera, and TV, washing machine and refrigerator.In detail, wiring board can carry and assembled wafers (chip), passive component (passive component, or title passive device) with active element (active component, or claim active member) etc. multiple electronic component (electronic component), and allow these electronic components be electrically connected to each other.So, the signal of telecommunication can transmit between these electronic components, and allows above-mentioned electronic installation and electrical home appliances operate.
Summary of the invention
The objective of the invention is to, a kind of manufacture method of wiring board is provided, be used for making wiring board.
Another object of the present invention is to, a kind of wiring board is provided, it can be assembled with a plurality of electronic components.
The object of the invention to solve the technical problems realizes by the following technical solutions.The manufacture method of a kind of wiring board that proposes according to the present invention, it may further comprise the steps: form at least one initial insulating barrier on a substrate; Then, carry out an activation procedure, so that initial insulating barrier becomes an activation insulating barrier; The activation insulating barrier has a surface and and is positioned at the region of activation on surface, and comprises many catalyst grains, and the activation of some of them catalyst grains also is exposed in the region of activation; Then, form a conductive pattern layer in the region of activation, wherein conductive pattern layer protrudes from the surface.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
In an embodiment of the present invention, these catalyst grains are a plurality of nano particles.
In an embodiment of the present invention, the material of these catalyst grains comprises at least a transition metal complex compound.
In an embodiment of the present invention, above-mentioned transition metal complex compound is transition metal oxide, transition metal nitride, transition metal misfit thing or transition metal chelate.
In an embodiment of the present invention, the material of these catalyst grains is selected from the group that transition metal oxide, transition metal nitride, transition metal misfit thing and transition metal chelate are formed.
In an embodiment of the present invention, the material of above-mentioned transition metal complex compound is selected from the group that is made up of zinc, copper, silver, gold, nickel, palladium, platinum, cobalt, rhodium, iridium, indium, iron, manganese, chromium, molybdenum, tungsten, vanadium, tantalum and titanium.
In an embodiment of the present invention, above-mentioned activation insulating barrier more comprises a high-molecular weight compounds, and these catalyst grains are distributed in the high-molecular weight compounds.
In an embodiment of the present invention, above-mentioned high-molecular weight compounds is a high molecular polymer.
In an embodiment of the present invention, the material of above-mentioned high molecular polymer is to be selected from by epoxy resin, the epoxy resin of upgrading, polyester, acrylate, the plain polymer of fluorine, polyphenylene oxide, polyimides, phenolic resins, polysulfones, the plain polymer of silicon, two maleic acids-triazine resin (Bismaleimide Triazine resin, BT resin, promptly so-called BT resin), the cyanic acid polyester, polyethylene, polycarbonate resin, propylene-butadiene-styrene copolymer compound, polyethylene terephthalate resin, polybutylene terephthalate resin, liquid crystal polymer, polyamide 6, nylon, kematal, the group that polyphenylene sulfide and cyclic olefin copolymerized macromolecule are formed.
In an embodiment of the present invention, above-mentioned method of carrying out activation procedure comprises initial insulating barrier is carried out laser ablation, plasma etching or mechanical processing method.
In an embodiment of the present invention, the LASER Light Source that above-mentioned laser ablation adopted is infrared laser, ultraviolet laser, excimer laser or far infrared laser.
In an embodiment of the present invention, above-mentioned mechanical processing method comprises the cutting of water cutter, sandblast or external form cutting.
In an embodiment of the present invention, the method for above-mentioned formation conductive pattern layer comprises wireless plating technology or chemical vapour deposition (CVD).
In an embodiment of the present invention, the method for above-mentioned formation conductive pattern layer comprises galvanoplastic.
In an embodiment of the present invention, above-mentioned initial insulating barrier also comprises these catalyst grains.
In an embodiment of the present invention, aforesaid substrate is a circuit base plate, and circuit base plate comprises that one first line layer, second line layer with respect to first line layer, one are electrically connected at internal wiring structure between first line layer and second line layer at the dielectric layer and between first line layer and second line layer.
In an embodiment of the present invention, comprise that more at least one resin bed of formation is on substrate; Then, form initial insulating barrier on resin bed.
In an embodiment of the present invention, the method for above-mentioned formation resin bed comprises that the pressing resin bed is on substrate.
In an embodiment of the present invention, above-mentioned resin bed is for being selected from the group that is made up of film (prepreg) and blank core layer (blank core).
In an embodiment of the present invention, after forming initial insulating barrier, comprise also forming at least one conduction connecting structure (conductive connection structure) that wherein conduction connecting structure is connected between substrate and the conductive pattern layer.
In an embodiment of the present invention, above-mentioned conduction connecting structure is a conductive blind hole structures (conductive via structure).
In an embodiment of the present invention, the method for above-mentioned formation conduction connecting structure comprise carry out one boring step.
In an embodiment of the present invention, above-mentioned boring step is laser drill or machine drilling.
In an embodiment of the present invention, more be included in before the formation conductive pattern layer, form at least one resistance barrier patterned layer on substrate, wherein resistance barrier patterned layer has the pierced pattern of an exposure region of activation; Then, form conductive pattern layer in the region of activation that pierced pattern exposed; Then, remove resistance barrier patterned layer.
In an embodiment of the present invention, above-mentioned resistance barrier patterned layer is patterning photoresist layer (or claiming photoresist layer).
In an embodiment of the present invention, the method for above-mentioned formation conductive pattern layer is included in and forms before the resistance barrier patterned layer, forms at least one metal level, wherein comprehensive ground of metal level covering surfaces; Then, form resistance barrier patterned layer on metal level; Then, metal level is electroplated.
In an embodiment of the present invention, after metal level being electroplated and removed resistance barrier patterned layer, more comprise removing the part metals layer.
In an embodiment of the present invention, the above-mentioned method that removes the part metals layer comprises metal level is carried out etching.
The object of the invention to solve the technical problems also realizes in addition by the following technical solutions.According to a kind of wiring board that the present invention proposes, it comprises a substrate, one first activation insulating barrier, one second activation insulating barrier, one first conductive pattern layer and one second conductive pattern layer.Substrate has the lower surface of a upper surface and a relative upper surface; The first activation insulating barrier is disposed at upper surface, and has first region of activation that a first surface and is positioned at first surface; The second activation insulating barrier is disposed at lower surface, and has second region of activation that a second surface and is positioned at second surface; The first activation insulating barrier and the second activation insulating barrier all comprise many catalyst grains; First conductive pattern layer is disposed at first surface, and connects the catalyst grains that some are positioned at first region of activation, and wherein first conductive pattern layer protrudes from first surface; Second conductive pattern layer is disposed at second surface, and connects the catalyst grains that some are positioned at second region of activation, and wherein second conductive pattern layer protrudes from second surface.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
In an embodiment of the present invention, above-mentioned first region of activation is not more than 10 microns with respect to the degree of depth of first surface.
In an embodiment of the present invention, above-mentioned second region of activation is not more than 10 microns with respect to the degree of depth of second surface.
In an embodiment of the present invention, aforesaid substrate is a circuit base plate, and wiring board more comprises at least one first conduction connecting structure; First conduction connecting structure is disposed in the first activation insulating barrier, and is connected between first line layer of first conductive pattern layer and circuit base plate.
In an embodiment of the present invention, above-mentioned wiring board more comprises at least one second conduction connecting structure; Second conduction connecting structure is disposed in the second activation insulating barrier, and is connected between second line layer of second conductive pattern layer and circuit base plate.
In sum, utilize above-mentioned activation insulating barrier, the present invention is formed conductive pattern layer, and then makes the wiring board that can supply a plurality of electronic components assemblings.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1 is the flow chart of the manufacture method preferred embodiment of wiring board of the present invention.
Fig. 2 A to Fig. 2 G is the schematic diagram of manufacture method of the wiring board of first embodiment of the invention.
Fig. 3 A is the schematic diagram of the wiring board of second embodiment of the invention.
Fig. 3 B is the schematic diagram of wiring board when forming resin bed among Fig. 3 A.
Fig. 4 A to Fig. 4 E is the schematic diagram of manufacture method of the wiring board of third embodiment of the invention.
Fig. 5 A to Fig. 5 H is the schematic diagram of manufacture method of the wiring board of fourth embodiment of the invention.
200,300,400,500: wiring board 210: substrate
210a: upper surface 210b: lower surface
212a: the first line layer 212b: second line layer
214: dielectric layer 220a, 320a: the first activation insulating barrier
420a, 520a: the first activation insulating barrier 220a ', 320a ': the first initial insulating barrier
220b, 320b: the second activation insulating barrier 420b, 520b: the second activation insulating barrier
220b ', 320b ': second initial insulating barrier 222a, the 422a, 522a: first surface
222b, 422b, 522b: second surface 224a, 424a, 524a: first region of activation
224b, 424b:, 524b: second region of activation 226: catalyst grains
228: high- molecular weight compounds 230a, 430a, 530a: first conductive pattern layer
230b, 430b: the second conductive pattern layer 530b: second conductive pattern layer
240a, 440a: the first conduction connecting structure 540a: first conduction connecting structure
240b, 440b: the second conduction connecting structure 540b: second conduction connecting structure
250a, 250a ': the first resistance barrier patterned layer 450a, 550a: the first resistance barrier patterned layer
250b, 250b ': the second resistance barrier patterned layer 450b, 550b: the second resistance barrier patterned layer
252a, 452a: the first pierced pattern 552a: first pierced pattern
252b, 452b: the second pierced pattern 552b: second pierced pattern
310a, 310b: resin bed 460a, 560a ': the first metal layer
460b, 560b ': the second metal level 570a: first electrodeposited coating
570b: the second electrodeposited coating B1, B3, B5: first blind hole
B2, B4, B6:: the second blind hole D: the degree of depth
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, wiring board and its embodiment of manufacture method, structure, step, feature and effect thereof that foundation the present invention is proposed are elaborated.
Seeing also shown in Figure 1ly, is the flow chart of the manufacture method preferred embodiment of wiring board of the present invention.The manufacture method of the wiring board of preferred embodiment of the present invention can be made single face wiring board (single-sidecircuit board), double-sided wiring board (double-side circuit board) and multilayer circuit board (multi-layer circuit board).Step of manufacturing at this wiring board comprises:
At first, form at least one initial insulating barrier (S100) on a substrate, wherein this initial insulating barrier can be a kind of dry film or wet film, and therefore initial insulating barrier can be formed on the substrate by the mode of pressing or coating.In addition, substrate can be a circuit base plate.
Initial insulating barrier comprises many catalyst grains, and wherein these catalyst grains can be a plurality of nano particles, and can be the metallic particles (metallic particle) with metal ingredient.These metallic particles have multiple variety classes, and can be activated.Specifically, before these metallic particles were not activated, the physics of these metallic particles and chemical characteristic might not be identical with metal block material (metal bulk), and for example the metallic particles of some kind was to have insulating properties before not activating.
Hold above-mentionedly, the composition of these metallic particles contains metallic atom or metal ion, and the material of these catalyst grains comprises a kind of transition metal complex compound.This transition metal complex compound for example is transition metal oxide, transition metal nitride, transition metal misfit thing or transition metal chelate, and wherein the material of transition metal complex compound for example is the combination in any that is selected from zinc, copper, silver, gold, nickel, palladium, platinum, cobalt, rhodium, iridium, indium, iron, manganese, chromium, molybdenum, tungsten, vanadium, tantalum, titanium or these metals.
In addition, the material of these catalyst grains can comprise multiple transition metal complex compound.Specifically, the material of these catalyst grains can be the combination in any that is selected from transition metal oxide, transition metal nitride, transition metal misfit thing, transition metal chelate or these compounds.For instance; these catalyst grains can comprise transition metal oxide, transition metal nitride or transition metal misfit thing; or these catalyst grains also can comprise multiple transition metal complex compounds such as transition metal oxide and transition metal misfit thing, and wherein these catalyst grains for example are cupric oxide, titanium nitride, cobalt molybdenum bimetallic nitride (Co2Mo3Nx) particle or palladium metal particle.
Initial insulating barrier also comprises a high-molecular weight compounds, and these catalyst grains are distributed in the high-molecular weight compounds.Specifically, this high-molecular weight compounds can be a kind of high molecular polymer, its material for example is to be selected from epoxy resin, the epoxy resin of upgrading, polyester (polyester), acrylate, the plain polymer (fluoro-polymer) of fluorine, polyphenylene oxide (polyphenylene oxide), polyimides (polyimide), phenolic resins (phenolicresin), polysulfones (polysulfone), the plain polymer (silicone polymer) of silicon, two maleic acids-triazine resin (bismaleimide triazine modified epoxy, be so-called BT resin), cyanic acid polyester (cyanate ester), polyethylene (polyethylene), polycarbonate resin (polycarbonate, PC), propylene-butadiene-styrene copolymer compound (acrylonitrile-butadiene-styrene copolymer, ABS copolymer), polyethylene terephthalate resin (polyethylene terephthalate, PET), polybutylene terephthalate resin (polybutylene terephthalate, PBT), liquid crystal polymer (liquidcrystal polymers, LCP), (polyamide 6 for polyamide 6, PA 6), nylon (Nylon), kematal (polyoxymethylene, POM), polyphenylene sulfide (polyphenylene sulfide, PPS), the cyclic olefin copolymerized macromolecule (cyclic olefin copolymer, COC) or the combination in any of these macromolecular materials.
Initial insulating barrier can contact substrate, and directly is formed on the substrate.Yet initial insulating barrier is contact substrate not also, and is formed on the substrate indirectly.For example, before forming initial insulating barrier, can form at least one deck resin bed earlier on substrate, the method that wherein forms resin bed can be the pressing resin bed on substrate, and resin bed can be film or blank core layer.Afterwards, form initial insulating barrier on this resin bed.
After forming initial insulating barrier, carry out an activation procedure (S102), so that initial insulating barrier becomes an activation insulating barrier, and the activation insulating barrier comprises above-mentioned high-molecular weight compounds and these catalyst grains that are distributed in this high-molecular weight compounds.Therefore, the two structural similarity of initial insulating barrier and activation insulating barrier, and the two significant difference is: the activation insulating barrier has a surface and and is positioned at this surperficial region of activation, and the activation of some of them catalyst grains also is exposed in the region of activation.
Above-mentioned method of carrying out activation procedure has a variety of.For example, the method for carrying out activation procedure can be that initial insulating barrier is carried out laser ablation or plasma etching.The employed laser of above-mentioned laser ablation, the wavelength of the laser beam that it sent (laser beam) can be in the scope of visible light, infrared light or ultraviolet light.Therefore, the LASER Light Source that laser ablation adopted can be infrared laser, ultraviolet laser, garnet laser (Yttrium Aluminum Garnet, YAG laser), carbon dioxide laser, excimer laser (excimer laser) or far infrared laser.
In addition, the method for carrying out activation procedure also can be that initial insulating barrier is carried out mechanical processing method.In detail, this mechanical processing method can comprise the cutting of water cutter, sandblast or external form cutting, and external form cutting wherein described here can be V-type cutting (V-cut) or mill and cut (routing).By above-mentioned mechanical processing method, the region of activation also can form.
Then, form a conductive pattern layer (S104) in the region of activation, wherein conductive pattern layer protrudes from the surface of activation insulating barrier, and conductive pattern layer comprises at least one connection pad and many cablings.The method that forms conductive pattern layer can be to adopt the chemical method that need not to apply foreign current, and it for example is wireless plating technology or chemical vapour deposition (CVD).
When conductive pattern layer is when adopting above-mentioned chemical method to form, the catalyst grains after the activation can directly produce reaction with the reactant that forms conductive pattern layer.Specifically, the activation insulating barrier is being carried out in the process of laser ablation or plasma etching, laser beam and plasma all can interrupt the chemical bond (Chemical bond) of these catalyst grains in the region of activation, allow these catalyst grains activate.
Secondly, conductive pattern layer can form by one deck resistance barrier patterned layer at least, and wherein resistance barrier patterned layer has a pierced pattern.Specifically, before the formation conductive pattern layer, can form resistance barrier patterned layer on substrate, and resistance barrier patterned layer can be the patterning photoresist layer, it for example is wet type photoresist or dry film after the development.Then, form conductive pattern layer in pierced pattern.Afterwards, remove resistance barrier patterned layer.
In the present invention wherein among the embodiment, conductive pattern layer more can be to form by above-mentioned resistance barrier patterned layer and one deck metal level at least.Specifically, at first, allow the region of activation contain the surface of the activation insulating barrier that it was positioned at fully.Then, form a metal level in the region of activation of activation insulating barrier.Because the region of activation is contained the surface of the activation insulating barrier that it was positioned at fully, so metal level can cover the surface of activation insulating barrier comprehensively.
Then, form resistance barrier patterned layer on metal level, wherein the local exposing metal layer of the pierced pattern of resistance barrier patterned layer.Afterwards, metal level is electroplated, in pierced pattern, to form conductive pattern layer.Hence one can see that, and conductive pattern layer also can be to form with the galvanoplastic that apply foreign current.Afterwards, remove the part metals layer, to expose part activation insulating barrier, the method that wherein removes the part metals layer can be that metal level is carried out etching.So, conductive pattern layer is formed.
What deserves to be mentioned is that in the present invention wherein among the embodiment, the manufacture method of above-mentioned wiring board more can comprise and forms at least one conduction connecting structure.Specifically, conduction connecting structure is connected between substrate and the conductive pattern layer, and by conduction connecting structure, the two is electrically conducted substrate and conductive pattern layer.
The method that forms conduction connecting structure has a variety of.In a kind of therein method that forms conduction connecting structure, at first, carry out a boring step, to form at least one blind hole, wherein this boring step can be laser drill or machine drilling.Afterwards, carry out wireless plating technology or galvanoplastic, to form conduction connecting structure in blind hole.Therefore, conduction connecting structure can be a kind of conductive blind hole structures that is positioned at blind hole, and it for example is hollow conductive pole or solid conductive pole.
In order to specify feature of the present invention, below enumerate some embodiment, and cooperate graphic, to describe.
" first embodiment "
Seeing also shown in Fig. 2 A to Fig. 2 G, is the schematic diagram of manufacture method of the wiring board of first embodiment of the invention.Please consult Fig. 2 G earlier, introduce the feature of the wiring board 200 of present embodiment earlier in configuration aspects at this.Wiring board 200 comprises a substrate 210, multilayer activation insulating barrier and multilayer conductive patterned layer.These activation insulating barriers comprise one first activation insulating barrier 220a and one second activation insulating barrier 220b, and these conductive pattern layer comprise one first conductive pattern layer 230a and one second conductive pattern layer 230b.
Substrate 210 has a upper surface 210a and a lower surface 210b, and upper surface 210a is with respect to lower surface 210b, and wherein the first activation insulating barrier 220a is disposed at upper surface 210a, and the second activation insulating barrier 220b is disposed at lower surface 210b.Substrate 210 can be a kind of circuit base plate, and it comprises that one first line layer 212a, one second line layer 212b, a dielectric layer 214 and are electrically connected at the internal wiring structure (not illustrating) between the first line layer 212a and the second line layer 212b.The first line layer 212a is with respect to the second line layer 212b, and dielectric layer 214 is between the first line layer 212a and the second line layer 212b.
The internal wiring structure can comprise at least one conduction connecting structure and one deck internal wiring layer at least, wherein the internal wiring layer electrically connects this conduction connecting structure, and conduction connecting structure for example is conductive blind hole structures, conductivity through-hole structure (conductive through hole structure) or conduction buried via hole structure (conductive buried hole structure).
Because above-mentioned conduction connecting structure and internal wiring layer are all the structure of the known wiring board that the persond having ordinary knowledge in the technical field of the present invention knows, therefore, even if the graphic internal wiring structure that do not show, the persond having ordinary knowledge in the technical field of the present invention still can be easily and is clearly learnt the concrete feature of internal wiring structure.
The first activation insulating barrier 220a has the first region of activation 224a that a first surface 222a and is positioned at first surface 222a, and the second activation insulating barrier 220b has the second region of activation 224b that a second surface 222b and is positioned at second surface 222b, and wherein the first activation insulating barrier 220a and the second activation insulating barrier 220b all comprise many catalyst grains 226.
These catalyst grains 226 can be a plurality of nano particles, and the material of these catalyst grains 226 can comprise at least a transition metal complex compound, its material is selected from by zinc, copper, silver, gold, nickel, palladium, platinum, cobalt, rhodium, iridium, indium, iron, manganese, chromium, molybdenum, tungsten, vanadium, tantalum and titanium, or the group that forms of these metals.Therefore, catalyst grains 226 can be the nano particle with metal ingredient.
In addition, above-mentioned transition metal complex compound can be transition metal oxide, transition metal nitride, transition metal misfit thing or transition metal chelate, and the material of these catalyst grains 226 for example is the combination in any that is selected from transition metal oxide, transition metal nitride, transition metal misfit thing, transition metal chelate or these compounds.
The two more comprises a high-molecular weight compounds 228 the first activation insulating barrier 220a and the second activation insulating barrier 220b, and these catalyst grains 226 are distributed in the high-molecular weight compounds 228.High-molecular weight compounds 228 can be a high molecular polymer, and its material is to be selected from epoxy resin, the epoxy resin of upgrading, polyester, acrylate, the plain polymer of fluorine, polyphenylene oxide, polyimides, phenolic resins, polysulfones, the plain polymer of silicon, two maleic acids-triazine resin (being the BT resin), the cyanic acid polyester, polyethylene, polycarbonate resin, propylene-butadiene-styrene copolymer compound, polyethylene terephthalate resin, polybutylene terephthalate resin, liquid crystal polymer, polyamide 6, nylon, kematal, polyphenylene sulfide, the combination in any of cyclic olefin copolymerization height or these macromolecular materials.
The first conductive pattern layer 230a is disposed at first surface 222a, and connects some catalyst grains that are positioned at the first region of activation 224a 226, and wherein the first conductive pattern layer 230a protrudes from first surface 222a.The second conductive pattern layer 230b is disposed at second surface 222b, and connects some catalyst grains that are positioned at the second region of activation 224b 226, and wherein the second conductive pattern layer 230b protrudes from second surface 222b.The first conductive pattern layer 230a and the second conductive pattern layer 230b the two all comprise a plurality of in order to the connection pad that is connected electronic component and the cabling of many delivered currents.
In addition, wiring board 200 more can comprise a plurality of conduction connecting structures, and it comprises at least one first conduction connecting structure 240a and at least one second conduction connecting structure 240b.The first conduction connecting structure 240a is disposed among the first activation insulating barrier 220a, and is connected between the first line layer 212a of the first conductive pattern layer 230a and substrate 210.The second conduction connecting structure 240b is disposed among the second activation insulating barrier 220b, and is connected between the second line layer 212b of the second conductive pattern layer 230b and substrate 210.
In the present embodiment, the first conduction connecting structure 240a and the second conduction connecting structure 240b can be a kind of conductive blind hole structures all, and this conductive blind hole structures for example is a kind of hollow conductive pole, shown in Fig. 2 G.By the first conduction connecting structure 240a and the second conduction connecting structure 240b, the two can electrically conduct the first conductive pattern layer 230a and the second conductive pattern layer 230b with substrate 210.
What deserves to be mentioned is that in the embodiment that other do not illustrate, the quantity of the conduction connecting structure that wiring board 200 is included can only be one.That is to say that the two total quantity of the first conduction connecting structure 240a that wiring board 200 is included and the second conduction connecting structure 240b can only be one.Therefore, the two total quantity of the first conduction connecting structure 240a shown in Fig. 2 G and the second conduction connecting structure 240b is only for illustrating, and non-limiting the present invention.
More than introduce the feature of the wiring board 200 of present embodiment in configuration aspects.Next will cooperate Fig. 2 A to Fig. 2 G to introduce the manufacture method of wiring board 200.
Please consult Fig. 2 A earlier, in the manufacture method of wiring board 200, at first, form at least one initial insulating barrier, promptly form one first initial insulating barrier 220a ' in the upper surface 210a of substrate 210, and form one second initial insulating barrier 220b ' in the lower surface 210b of substrate 210.The first initial insulating barrier 220a ' and the second initial insulating barrier 220b ' can be formed on the substrate 210 the two by the mode of pressing or coating.In addition, the first initial insulating barrier 220a ' and the second initial insulating barrier 220b ' the two also comprise high-molecular weight compounds 228 and be distributed in these catalyst grains 226 in the high-molecular weight compounds 228.
See also Fig. 2 B, then, carry out a boring step, to form at least one first blind hole B1 and at least one second blind hole B2, wherein the first blind hole B1 and the second blind hole B2 form with laser drill or machine drilling.The first blind hole B1 is arranged in the first initial insulating barrier 220a ', and the second blind hole B2 is arranged in the second initial insulating barrier 220b '.The first blind hole B1 is local to expose the first line layer 212a, and the local second line layer 212b that exposes of the second blind hole B2.
See also Fig. 2 C, then, forming at least, one deck resistance hinders patterned layer on substrate 210.Specifically, the flow process that forms resistance barrier patterned layer comprises that forming one first hinders barrier patterned layer 250a on the first initial insulating barrier 220a ', form one second resistance barrier patterned layer 250b on the second initial insulating barrier 220b ', wherein the first resistance barrier patterned layer 250a and the second resistance barrier patterned layer 250b all can be the patterning photoresist layer, and it for example is wet type photoresist or dry film after developing.
Hold above-mentionedly, the first resistance barrier patterned layer 250a has one first pierced pattern 252a, and the local first initial insulating barrier 220a ' that exposes of the first pierced pattern 252a.The second resistance barrier patterned layer 250b has one second pierced pattern 252b, and the local second initial insulating barrier 220b ' that exposes of the second pierced pattern 252b.In addition, the first pierced pattern 252a more exposes the first line layer 212a that the whole first blind hole B1 and the first blind hole B1 are exposed, and the second pierced pattern 252b more exposes the second line layer 212b that the whole second blind hole B2 and the second blind hole B2 are exposed.
See also Fig. 2 C and Fig. 2 D, then, carry out activation procedure, allow the first initial insulating barrier 220a ' become the first activation insulating barrier 220a, the second initial insulating barrier 220b ' becomes the second activation insulating barrier 220b.The method of carrying out activation procedure can be that the first initial insulating barrier 220a ' and the second initial insulating barrier 220b ' are carried out laser ablation, plasma etching or mechanical processing method, wherein this mechanical processing method comprises the cutting of water cutter, sandblast or external form cutting (for example be the V-type cutting or mill and cut), and the LASER Light Source that above-mentioned laser ablation adopted can be infrared laser, ultraviolet laser, garnet laser (YAGlaser), carbon dioxide laser, excimer laser or far infrared laser.
When the first initial insulating barrier 220a ' and the second initial insulating barrier 220b ' are carried out laser ablation or plasma etching, the first resistance barrier patterned layer 250a and second resistance can be hindered patterned layer 250b as shade, and use laser beam or plasma to come the first initial insulating barrier 220a ' and the second initial insulating barrier 220b ' are done comprehensive ablation or etching, allow the first region of activation 224a be formed at the first pierced pattern 252a, the second region of activation 224b is formed among the second pierced pattern 252b.
See also Fig. 2 E, it is the enlarged drawing of the first region of activation 224a among Fig. 2 D.After carrying out above-mentioned laser ablation or plasma etching, the part first initial insulating barrier 220a ' can be removed and form the first region of activation 224a.That is to say that the first region of activation 224a is a kind of depression, and the first region of activation 224a can be to be not more than 10 microns with respect to the depth D of first surface 222a, promptly depth D is equal to or less than 10 microns.In like manner, the second region of activation 224b can also be a kind of depression, and the second region of activation 224b also can be to be not more than 10 microns with respect to the degree of depth of second surface 222b.
Please consult Fig. 2 C and Fig. 2 D once more, because present embodiment is to hinder under the condition of patterned layer 250b as shade at the first resistance barrier patterned layer 250a and second resistance, use laser beam or plasma to come the first initial insulating barrier 220a ' and the second initial insulating barrier 220b ' are done comprehensive ablation or etching, so part first resistance barrier patterned layer 250a and the ablated or etching of the part second resistance barrier patterned layer 250b meeting, and the first resistance barrier patterned layer 250a ' that forms thinner thickness hinders barrier patterned layer 250b ' with second, shown in Fig. 2 D.
In addition, because the first pierced pattern 252a can expose the whole first blind hole B1, and the second pierced pattern 252b can expose the whole second blind hole B2 (shown in Fig. 2 C), therefore after carrying out activation procedure, some catalyst grains 226 can activate and be exposed in the first blind hole B1 and the second blind hole B2, shown in Fig. 2 D.In other words, the activation procedure of present embodiment not only can allow some catalyst grains 226 activate and be exposed in the first region of activation 224a and the second region of activation 224b, also allows other catalyst grains 226 activate and be exposed in the first blind hole B1 and the second blind hole B2 simultaneously.
See also Fig. 2 F, then, in the first region of activation 224a, form the first conductive pattern layer 230a, and in the second region of activation 224b, form the second conductive pattern layer 230b, wherein the first conductive pattern layer 230a is formed among the first pierced pattern 252a, and the second conductive pattern layer 230b is formed among the second pierced pattern 252b.The method that forms the first conductive pattern layer 230a and the second conductive pattern layer 230b can be to adopt the chemical method that need not to apply foreign current, and it for example is wireless plating technology or chemical vapour deposition (CVD).
Specifically, when carrying out chemical methodes such as above-mentioned wireless plating technology or chemical vapour deposition (CVD), the catalyst grains 226 that is positioned at after these activation of the first region of activation 224a and the second region of activation 224b can directly produce reaction with the reactant that forms the first conductive pattern layer 230a and the second conductive pattern layer 230b, to form the first conductive pattern layer 230a and the second conductive pattern layer 230b further.
For instance, when the first conductive pattern layer 230a and the second conductive pattern layer 230b are when being formed by wireless plating technology, the first activation insulating barrier 220a and the second activation insulating barrier 220b can directly be immersed in electroplate liquid, and do not need additionally to form Seed Layer (seed layer), can in the first region of activation 224a and the second region of activation 224b, form the first conductive pattern layer 230a and the second conductive pattern layer 230b.
Because some catalyst grains 226 activation also is exposed in the first blind hole B1 and the second blind hole B2, therefore when forming the first conductive pattern layer 230a and the second conductive pattern layer 230b, the first conduction connecting structure 240a and the second conduction connecting structure 240b also can be formed at respectively among the first blind hole B1 and the second blind hole B2 simultaneously.That is to say that the two can form the first conductive pattern layer 230a and the first conduction connecting structure 240a simultaneously, and the second conductive pattern layer 230b and the second conduction connecting structure 240b the two can form simultaneously.
See also Fig. 2 F and Fig. 2 G, after the first conductive pattern layer 230a, the second conductive pattern layer 230b, the first conduction connecting structure 240a and the second conduction connecting structure 240b form, remove resistance barrier patterned layer, promptly remove the first resistance barrier patterned layer 250a ' and the second resistance barrier patterned layer 250b ', allow the first surface 222a of the first activation insulating barrier 220a and the second surface 222b of the second activation insulating barrier 220b be exposed out.So far, wiring board 200 has been made basically and has been finished.
In addition, in the embodiment that other do not illustrate, more can form welding resisting layer (solder mask), wherein one deck welding resisting layer is formed at first surface 222a, and another layer welding resisting layer is formed at second surface 222b.These welding resisting layers can expose the two a plurality of connection pads of the first conductive pattern layer 230a and the second conductive pattern layer 230b.Secondly, these welding resisting layers more can fill up these the first blind hole B1 and the second blind hole B2.In addition, the type of these welding resisting layers can be welding resisting layer definition (Solder Mask Define, SMD) or the definition of non-welding resisting layer (Non-Solder Mask Define, SMD).
What deserves to be mentioned is that the wiring board 200 shown in Fig. 2 G is a kind of four layers of wiring board, and Fig. 2 A to Fig. 2 G discloses this Layer increasing method manufacture method with four layers of wiring board of double-sided substrate.Yet the manufacture method of present embodiment can also be made single face wiring board and multilayer circuit board.That is to say that in the embodiment that other do not illustrate, wiring board 200 also can be a kind of single face wiring board or multilayer circuit board.Therefore, disclosed wiring board 200 of Fig. 2 A to Fig. 2 G and manufacture method thereof are only for illustrating, and non-limiting the present invention.
" second embodiment "
Fig. 3 A is the schematic diagram of the wiring board of second embodiment of the invention.See also Fig. 3 A, introduce the feature of the wiring board 300 of present embodiment earlier in configuration aspects at this.With regard to structure, the wiring board 300 of present embodiment is similar to the wiring board 200 of first embodiment, and the significant difference between the two is: wiring board 300 more comprises one deck resin bed at least, and this resin bed is disposed between substrate and the activation insulating barrier.
Particularly, wiring board 300 comprises substrate 210, one first activation insulating barrier 320a, one second activation insulating barrier 320b, multi-layer resinous layer 310a and 310b, the first conductive pattern layer 230a, the second conductive pattern layer 230b, at least one first conduction connecting structure 240a and at least one second conduction connecting structure 240b.
Hold above-mentioned, it is identical that the two the first activation insulating barrier 220a and second of material and first embodiment of the first activation insulating barrier 320a and the second activation insulating barrier 320b activates insulating barrier 220b, and promptly the two all comprises high-molecular weight compounds 228 and is distributed in a plurality of catalyst grains 226 in the high-molecular weight compounds 228.
Resin bed 310a is disposed between the first activation insulating barrier 320a and the substrate 210, and resin bed 310b then is disposed between the second activation insulating barrier 320b and the substrate 210.In the present embodiment, these resin beds 310a, 310b can be the blank core layers of multi-disc film or multilayer, and these resin beds 310a, 310b can strengthen the structure of wiring board 300.
Fig. 3 B is the schematic diagram of wiring board when forming resin bed among Fig. 3 A, sees also Fig. 3 B, and the manufacture method of the wiring board of present embodiment is identical with first embodiment substantially, and the difference part is to form resin bed 310a, 310b.Specifically, in the manufacture method of wiring board 300, at first, form resin bed 310a on the upper surface 210a of substrate 210, form resin bed 310b on the lower surface 210b of substrate 210, the method that wherein forms resin bed 310a, 310b can be that pressing resin bed 310a, 310b are on substrate 210.
Then, form the first initial insulating barrier 320a ' on resin bed 310a, form the second initial insulating barrier 320b ' on resin bed 310b, wherein the two formation method of the first initial insulating barrier 320a ' and the second initial insulating barrier 320b ' is identical with the second initial insulating barrier 220b ' with the first initial insulating barrier 220a ' among first embodiment, so no longer repeat to introduce.
What deserves to be mentioned is that the first initial insulating barrier 320a ' and resin bed 310a can be formed at the upper surface 210a of substrate 210 simultaneously, and the second initial insulating barrier 320b ' and resin bed 310b can be formed at the lower surface 210b of substrate 210 simultaneously.For example, the first initial insulating barrier 320a ' and resin bed 310a can be pressed on the upper surface 210a of substrate 210 simultaneously, and the second initial insulating barrier 320b ' and resin bed 310b also can be pressed on the lower surface 210b of substrate 210 simultaneously.
Next, as the flow process shown in Fig. 2 B to Fig. 2 G in first enforcement, the step of holing and activation procedure, and form the first conductive pattern layer 230a, the second conductive pattern layer 230b, the first conduction connecting structure 240a and the second conduction connecting structure 240b.Above-mentioned boring step, activation procedure and the first conductive pattern layer 230a, the second conductive pattern layer 230b, the first conduction connecting structure 240a are all identical with first embodiment with the formation method of the second conduction connecting structure 240b, so no longer repeat to introduce.
" the 3rd embodiment "
Fig. 4 A to Fig. 4 E is the schematic diagram of manufacture method of the wiring board of third embodiment of the invention, and wherein the manufacture method of the 3rd embodiment is similar to first embodiment, therefore followingly will lay particular stress on the difference of introducing the present embodiment and first embodiment.
Please consult Fig. 4 A earlier, carry out activation procedure and form one first blind hole B3 and one second blind hole B4 in the first initial insulating barrier and the second initial insulating barrier after, the first blind hole B3 and the local first line layer 212a and the second line layer 212b that exposes substrate 210 of second blind hole B4 difference, and some catalyst grains 226 activate and are exposed in the first blind hole B3 and in the second blind hole B4.
The first activation insulating barrier 420a and the second activation insulating barrier 420b all comprise high-molecular weight compounds 228 and many catalyst grains 226 that are distributed in high-molecular weight compounds 228, wherein the first activation insulating barrier 420a has the first region of activation 424a that a first surface 422a and is positioned at first surface 422a, and the second activation insulating barrier 420b has the second region of activation 424b that a second surface 422b and is positioned at second surface 422b.Some catalyst grains 226 activation also are exposed in the first region of activation 424a and the second region of activation 424b.
The first region of activation 424a is contained whole first surface 422a, and the second region of activation 424b is contained whole second surface 422b.Therefore, exposed catalyst grains 226 is distributed in whole first surface 422a and second surface 422b, shown in Fig. 4 A.The method that forms the first region of activation 424a and the second region of activation 424b has multiple.For instance, when activation procedure adopts laser ablation or plasma etching, use laser beam or plasma is ablated or whole first surface 422a of etching and whole second surface 422b, to form the first region of activation 424a and the second region of activation 424b.
See also Fig. 4 B, then, form a first metal layer 460a in first surface 422a, and one second metal level 460b in second surface 422b, the method that wherein forms the first metal layer 460a and the second metal level 460b can be to adopt the chemical method that need not to apply foreign current, and it for example is wireless plating technology or chemical vapour deposition (CVD).In addition, because the first region of activation 424a and the second region of activation 424b are contained whole first surface 422a and whole second surface 422b, therefore the first metal layer 460a covers first surface 422a comprehensively, and the second metal level 460b covers second surface 422b comprehensively.
Secondly since some catalyst grains 226 activation and be exposed in the first blind hole B3 with the second blind hole B4 in, so the first metal layer 460a more is formed in the first blind hole B3, and the second metal level 460b more is formed in the second blind hole B4.The first metal layer 460a covers the first blind hole B3 comprehensively, and the second metal level 460b covers the second blind hole B4 comprehensively, and wherein the first metal layer 460a does not fill up the first blind hole B3, and the second metal level 460b does not fill up the second blind hole B4 yet.
See also Fig. 4 C, then, form one first resistance barrier patterned layer 450a on the first metal layer 460a, and form one second resistance barrier patterned layer 450b on the second metal level 460b.The first resistance barrier patterned layer 450a has local first a pierced pattern 452a who exposes the first metal layer 460a, and the second resistance barrier patterned layer 450b has the second pierced pattern 452b of local second a metal level 460b of exposure.The two material and formation method of the first resistance barrier patterned layer 450a and the second resistance barrier patterned layer 450b is all identical with first embodiment, so no longer repeat introduction.
See also Fig. 4 D, after the first resistance barrier patterned layer 450a and the second resistance barrier patterned layer 450b formation, the first metal layer 460a and the second metal level 460b are electroplated, with form one first conductive pattern layer 430a in the first pierced pattern 452a the first metal layer 460a that exposes of part, form one second conductive pattern layer 430b in the second metal level 460b of the local exposure of second pierced pattern 452b institute.Therefore, the first conductive pattern layer 430a and one second conductive pattern layer 430b the two be to form with the galvanoplastic that apply foreign current.
When forming the first conductive pattern layer 430a and the second conductive pattern layer 430b, pass through galvanoplastic, form one first conduction connecting structure 440a simultaneously in the first blind hole B3, form one second conduction connecting structure 440b in the 4th blind hole B4, wherein the first conduction connecting structure 440a is connected between the first line layer 212a of the first conductive pattern layer 430a and substrate 210, and the second conduction connecting structure 440b is connected between the second line layer 212b of the second conductive pattern layer 430b and substrate 210.
In the present embodiment, the first conduction connecting structure 440a and the second conduction connecting structure 440b can be a kind of conductive blind hole structures all, and this conductive blind hole structures for example is a kind of solid conductive pole, shown in Fig. 4 D.By the first conduction connecting structure 440a and the second conduction connecting structure 440b, the two all can electrically conduct the first conductive pattern layer 430a and the second conductive pattern layer 430b with substrate 210.
See also Fig. 4 D and Fig. 4 E, then, remove the first resistance barrier patterned layer 450a and the second resistance barrier patterned layer 450b, allow the first metal layer 460a and the second metal level 460b all be exposed out.Afterwards, remove part the first metal layer 460a and the part second metal level 460b, exposing first surface 422a and second surface 422b, and avoid the first conductive pattern layer 430a and the second conductive pattern layer 430b to be short-circuited.In addition, the method that removes part the first metal layer 460a and the part second metal level 460b can be that the first metal layer 460a and the second metal level 460b are carried out etching.
After removing part the first metal layer 460a and the part second metal level 460b, basically, a kind of wiring board 400 of substrate 210, the first activation insulating barrier 420a, the second activation insulating barrier 420b, the first conductive pattern layer 430a, the second conductive pattern layer 430b, the first conduction connecting structure 440a and the second conduction connecting structure 440b that comprises has been finished.
What deserves to be mentioned is that resin bed 310a, 310b among second embodiment all can be applied among the 3rd embodiment.Specifically, in the embodiment that other do not illustrate, before forming the first initial insulating barrier and the second initial insulating barrier, can form the upper surface 210a of one deck resin bed earlier, form the lower surface 210b of another layer resin bed in substrate 210 in substrate 210.Afterwards, form the first initial insulating barrier and the second initial insulating barrier on these resin beds.The material of above-mentioned resin bed is all identical with second embodiment with the formation method, so no longer repeat to introduce.
" the 4th embodiment "
Fig. 5 A to Fig. 5 H is the schematic diagram of manufacture method of the wiring board of fourth embodiment of the invention, and wherein the manufacture method of the wiring board of the 4th embodiment is similar to the 3rd embodiment, and the two significant difference is: the difference on opportunity that forms blind hole.Below will lay particular stress on the difference of introducing present embodiment and the 3rd embodiment.
See also Fig. 5 A, after carrying out activation procedure, the first activation insulating barrier 520a and the second activation insulating barrier 520b all form.The first activation insulating barrier 520a and the second activation insulating barrier 520b all comprise high-molecular weight compounds 228 and many catalyst grains 226 that are distributed in high-molecular weight compounds 228, wherein the first activation insulating barrier 520a has the first region of activation 524a that a first surface 522a and is positioned at first surface 522a, and the second activation insulating barrier 520b has the second region of activation 524b that a second surface 522b and is positioned at second surface 522b.Some catalyst grains 226 activation also are exposed to the first region of activation 524a and the second region of activation 524b.
Hold above-mentionedly, the first region of activation 524a is contained whole first surface 522a, and the second region of activation 524b is contained whole second surface 522b.That is to say that exposed catalyst grains 226 is distributed in whole first surface 522a and second surface 522b, shown in Fig. 5 A, and it is identical with the 3rd embodiment with the method for the second region of activation 524b to form the first region of activation 524a, so no longer repeat to introduce.
See also Fig. 5 B, then, form a first metal layer 560a in first surface 522a, and one second metal level 560b is in second surface 522b, wherein the first metal layer 560a covers first surface 522a comprehensively, and the second metal level 560b covers second surface 522b comprehensively.In addition, formation the first metal layer 560a is identical with the 3rd embodiment with the method for the second metal level 560b.
See also Fig. 5 C, then, form one first blind hole B5 in the first activation insulating barrier 520a and the first metal layer 560a, form one second blind hole B6 in second activation insulating barrier 520b and the second metal level 560b, wherein the two formation method of the first blind hole B5 and the second blind hole B6 is identical with the 3rd embodiment.The local first line layer 212a that exposes substrate 210 of the first blind hole B5, and the local second line layer 212b that exposes substrate 210 of the second blind hole B6.
See also Fig. 5 C and Fig. 5 D, then, reduce the first metal layer 560a and second the two thickness of metal level 560b, to form the first metal layer 560a ' and the second metal level 560b ', the method that wherein reduces the first metal layer 560a and second the two thickness of metal level 560b can be that the first metal layer 560a and the second metal level 560b are carried out etching.
Mandatory declaration be that the flow process of the above-mentioned minimizing the first metal layer 560a and second the two thickness of metal level 560b is the selectivity flow process in the present embodiment, is not to be necessary flow process.Therefore, in other embodiments, the first metal layer 560a and second the two thickness of metal level 560b can reduce.
See also Fig. 5 E, then, form one first electrodeposited coating 570a and one second electrodeposited coating 570b.The first electrodeposited coating 570a covers the surface of the first blind hole B5, and the second electrodeposited coating 570b covers the surface of the second blind hole B6, and wherein the first electrodeposited coating 570a connects the first metal layer 560a ', and the second electrodeposited coating 570b connects the second metal level 560b '.
Hold above-mentioned, the first electrodeposited coating 570a and the second electrodeposited coating 570b can adopt wireless plating technology to form, therefore in the process that forms the first electrodeposited coating 570a and the second electrodeposited coating 570b, the thickness of the first metal layer 560a ' and the second metal level 560b ' meeting thickening is shown in Fig. 5 E.
See also Fig. 5 F, after forming the first electrodeposited coating 570a and the second electrodeposited coating 570b, form one first resistance barrier patterned layer 550a on the first metal layer 560a ', form one second resistance barrier patterned layer 550b on the second metal level 560b ', wherein to hinder the two material and formation method of patterned layer 550b all identical with the 3rd embodiment for the first resistance barrier patterned layer 550a and second resistance.
Hold above-mentionedly, the first resistance barrier patterned layer 550a has one first pierced pattern 552a, and the second resistance barrier patterned layer 550b has one second pierced pattern 552b.The first pierced pattern 552a exposes the first electrodeposited coating 570a fully, and the local the first metal layer 560a ' that exposes.The second pierced pattern 552b exposes the second electrodeposited coating 570b fully, and the local second metal level 560b ' that exposes.
See also Fig. 5 F and Fig. 5 G, then, the first electrodeposited coating 570a and the second electrodeposited coating 570b are electroplated, to form one first conductive pattern layer 530a, one second conductive pattern layer 530b, one first conduction connecting structure 540a and one second conduction connecting structure 540b.The first conductive pattern layer 530a be formed at the first pierced pattern 552a the local the first metal layer 560a ' that exposes, and the second conductive pattern layer 530b is the second metal level 560b ' that is formed at the local exposure of second pierced pattern 552b institute.
The first conduction connecting structure 540a is formed among the first blind hole B5, and the second conduction connecting structure 540b is formed among the second blind hole B6, wherein the first conduction connecting structure 540a is connected between the first conductive pattern layer 530a and the first line layer 212a, and the second conduction connecting structure 540b is connected between the second conductive pattern layer 530b and the second line layer 212b.
See also Fig. 5 G and Fig. 5 H, then, remove the first resistance barrier patterned layer 550a and the second resistance barrier patterned layer 550b, the first metal layer 560a ' and the second metal level 560b ' all can be exposed out.Afterwards, remove part the first metal layer 560a ' and the part second metal level 560b ', to expose first surface 522a and second surface 522b, and avoid the first conductive pattern layer 530a and the second conductive pattern layer 530b to be short-circuited, it is identical with the 3rd embodiment with the method for the part second metal level 560b ' wherein to remove part the first metal layer 560a '.
Removing part the first metal layer 560a ' and the part second metal level 560b ' afterwards, basically, a kind of substrate 210, the first activation insulating barrier 520a, second wiring board 500 that activates insulating barrier 520b, the first conductive pattern layer 530a, the second conductive pattern layer 530b, the first conduction connecting structure 540a and the second conduction connecting structure 540b of comprising made and finished.In addition, resin bed 310a, 310b among second embodiment all can be applied among the 4th embodiment, and the method for using discloses in the aforementioned embodiment, so no longer repeat to introduce.
In sum, utilize above-mentioned activation insulating barrier (for example first activation insulating barrier and the second activation insulating barrier), the present invention is formed the conductive pattern layer (for example first conductive pattern layer and second conductive pattern layer) that comprises many cablings and a plurality of connection pads, and then makes the wiring board that can supply a plurality of electronic components assemblings.By wiring board of the present invention, the signal of telecommunication can transmit between these electronic components, and then allows electronic installation or electrical appliance be operated.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the method that can utilize above-mentioned announcement and technology contents are made a little change or be modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.

Claims (19)

1. the manufacture method of a wiring board is characterized in that it may further comprise the steps:
Form at least one initial insulating barrier on a substrate, wherein this initial insulating barrier comprises many catalyst grains;
Carry out an activation procedure, so that this initial insulating barrier becomes an activation insulating barrier, this activation insulating barrier has a surface and and is positioned at this surperficial region of activation, and comprises those catalyst grains, and the activation of some of them catalyst grains also is exposed in this region of activation; And
Form a conductive pattern layer in this region of activation, wherein this conductive pattern layer protrudes from this surface.
2. the manufacture method of wiring board according to claim 1 it is characterized in that wherein said activation insulating barrier also comprises a high-molecular weight compounds, and described catalyst grains is distributed in this high-molecular weight compounds.
3. the manufacture method of wiring board according to claim 1, it is characterized in that wherein said method of carrying out this activation procedure comprises carries out laser ablation, plasma etching or mechanical processing method to this initial insulating barrier.
4. the manufacture method of wiring board according to claim 1 is characterized in that the method for wherein said this conductive pattern layer of formation comprises wireless plating technology, chemical vapour deposition (CVD) or galvanoplastic.
5. the manufacture method of wiring board according to claim 1, it is characterized in that wherein said substrate is a circuit base plate, and this circuit base plate comprises that one first line layer, second line layer with respect to this first line layer, one are electrically connected at internal wiring structure between this first line layer and this second line layer at the dielectric layer and between this first line layer and this second line layer.
6. the manufacture method of wiring board according to claim 1 is characterized in that it also comprises:
Form at least one resin bed on this substrate; And
Form this initial insulating barrier on this resin bed.
7. the manufacture method of wiring board according to claim 6, it is characterized in that wherein said resin bed be selected from the group that forms by film and blank core layer one of them.
8. the manufacture method of wiring board according to claim 5 is characterized in that after forming this initial insulating barrier, also comprises forming at least one conduction connecting structure, and wherein this conduction connecting structure is electrically connected between this circuit base plate and this conductive pattern layer.
9. the manufacture method of wiring board according to claim 8 is characterized in that it also comprises:
Before this conductive pattern layer of formation, form at least one resistance barrier patterned layer on this substrate, wherein this resistance barrier patterned layer has the pierced pattern of this region of activation of exposure;
Form this conductive pattern layer in this region of activation that this pierced pattern exposed; And
Remove this resistance barrier patterned layer.
10. the manufacture method of wiring board according to claim 9 is characterized in that the method for wherein said this conductive pattern layer of formation comprises:
Before this resistance barrier patterned layer of formation, form at least one metal level, this metal level covers this surface comprehensively;
Form this resistance barrier patterned layer on this metal level;
This metal level is electroplated; And
After this metal level being electroplated and removed this resistance barrier patterned layer, remove this metal level of part.
11. a wiring board is characterized in that it comprises:
One substrate has the lower surface of a upper surface and relative this upper surface;
One first activation insulating barrier is disposed at this upper surface, and has first region of activation that a first surface and is positioned at this first surface;
One second activation insulating barrier is disposed at this lower surface, and has second region of activation that a second surface and is positioned at this second surface, and wherein this first activation insulating barrier and this second activation insulating barrier all comprise many catalyst grains;
One first conductive pattern layer is disposed at this first surface, and connects the catalyst grains that some are positioned at this first region of activation, and wherein this first conductive pattern layer protrudes from this first surface; And
One second conductive pattern layer is disposed at this second surface, and connects the catalyst grains that some are positioned at this second region of activation, and wherein this second conductive pattern layer protrudes from this second surface.
12. wiring board according to claim 11, the two also comprises a high-molecular weight compounds to it is characterized in that the wherein said first activation insulating barrier and this second activation insulating barrier, and described catalyst grains is distributed in this high-molecular weight compounds.
13. wiring board according to claim 11 is characterized in that wherein said first region of activation is not more than 10 microns with respect to the degree of depth of this first surface.
14. wiring board according to claim 13 is characterized in that wherein said second region of activation is not more than 10 microns with respect to the degree of depth of this second surface.
15. wiring board according to claim 11, it is characterized in that wherein said substrate is a circuit base plate, and this circuit base plate comprises that one first line layer, second line layer with respect to this first line layer, one are electrically connected at internal wiring structure between this first line layer and this second line layer at the dielectric layer and between this first line layer and this second line layer.
16. wiring board according to claim 15 is characterized in that it also comprises at least one first conduction connecting structure, this first conduction connecting structure is disposed in this first activation insulating barrier, and is connected between this first conductive pattern layer and this first line layer.
17. wiring board according to claim 16 is characterized in that it also comprises at least one second conduction connecting structure, this second conduction connecting structure is disposed in this second activation insulating barrier, and is connected between this second conductive pattern layer and this second line layer.
18. wiring board according to claim 11 is characterized in that it also comprises multi-layer resinous layer, wherein one deck resin bed is disposed between this first activation insulating barrier and this substrate, and another layer resin bed is disposed between this second activation insulating barrier and this substrate.
19. wiring board according to claim 18, it is characterized in that wherein said resin bed be selected from the group that forms by film and blank core layer one of them.
CN2009100095068A 2009-02-13 2009-02-13 Wiring board and preparation method thereof Expired - Fee Related CN101808462B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2009100095068A CN101808462B (en) 2009-02-13 2009-02-13 Wiring board and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2009100095068A CN101808462B (en) 2009-02-13 2009-02-13 Wiring board and preparation method thereof

Publications (2)

Publication Number Publication Date
CN101808462A true CN101808462A (en) 2010-08-18
CN101808462B CN101808462B (en) 2012-05-30

Family

ID=42610013

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2009100095068A Expired - Fee Related CN101808462B (en) 2009-02-13 2009-02-13 Wiring board and preparation method thereof

Country Status (1)

Country Link
CN (1) CN101808462B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102421256A (en) * 2010-09-24 2012-04-18 光宏精密股份有限公司 Manufacturing method for forming circuit structure on non-conductive carrier
CN105451456A (en) * 2015-12-08 2016-03-30 昆山联滔电子有限公司 Manufacturing method for non-conductive base material conductor circuit
CN108601234A (en) * 2018-04-04 2018-09-28 东莞市武华新材料有限公司 A kind of ceramic surface metal layer preparation method

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001291721A (en) * 2000-04-06 2001-10-19 Nec Corp Wiring structure, method of forming conductive pattern, semiconductor device, and method of manufacturing the same
JP2005243911A (en) * 2004-02-26 2005-09-08 Mitsui Mining & Smelting Co Ltd Multilayer laminated wiring board
JP4914012B2 (en) * 2005-02-14 2012-04-11 キヤノン株式会社 Manufacturing method of structure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102421256A (en) * 2010-09-24 2012-04-18 光宏精密股份有限公司 Manufacturing method for forming circuit structure on non-conductive carrier
CN105451456A (en) * 2015-12-08 2016-03-30 昆山联滔电子有限公司 Manufacturing method for non-conductive base material conductor circuit
CN108601234A (en) * 2018-04-04 2018-09-28 东莞市武华新材料有限公司 A kind of ceramic surface metal layer preparation method

Also Published As

Publication number Publication date
CN101808462B (en) 2012-05-30

Similar Documents

Publication Publication Date Title
US8368201B2 (en) Method for embedding a component in a base
CN101193502B (en) Circuit board structure and its making method
JP5117455B2 (en) Method for forming a conductive pattern on a composite structure
JP5089633B2 (en) Circuit board manufacturing process and circuit board
US20050124148A1 (en) Method for embedding a component in a base and forming a contact
CN100342526C (en) Semiconductor sealing baseplate structure of electric padding metal protective layer and producing method thereof
US20100224397A1 (en) Wiring board and method for manufacturing the same
US20080041621A1 (en) Circuit board structure and method for fabricating the same
CN100570841C (en) Make the method for circuitized substrate
US7754598B2 (en) Method for manufacturing coreless packaging substrate
JP2005183952A (en) Manufacturing method of printed circuit board having conductive holes and board thereof
CN104284514A (en) Printed circuit board and method of manufacturing the same
JP2009289802A (en) Module having electronic part built-in and production method thereof
KR20160043357A (en) Embedded board and method of manufacturing the same
KR20160059125A (en) Element embedded printed circuit board and method of manufacturing the same
CN101808462B (en) Wiring board and preparation method thereof
CN101567356B (en) Circuit board structure and manufacture method thereof
KR102473416B1 (en) Printed circuit board and method of manufacturing the same
CN102118919A (en) Electronic device and method of manufacturing the same
KR100393271B1 (en) Method for manufacturing a multilayer electronic component mounting substrate
TWI301662B (en) Package substrate and the manufacturing method making the same
US20090102045A1 (en) Packaging substrate having capacitor embedded therein
CN108307590A (en) Packaging structure and manufacturing method thereof
KR20130136248A (en) The printed circuit board
CN101295698A (en) Flip-chip substrate structure and production method thereof

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20120530