CN101807430A - Writing system for static random access memory and memory - Google Patents

Abstract

The invention provides a writing system and a memory. The writing system is applied to the static random access memory. A simulation write circuit, a negative pulse voltage control circuit and at least one conventional write circuit are arranged in the writing system; and each conventional write circuit comprises a write driving circuit and a negative pulse voltage supply circuit. In the writing process, the simulation write circuit drives a simulation bit line to change the electric potential thereof, so the negative pulse voltage control circuit generates a negative pulse voltage control signal according to the electric potential of the simulation bit line. In each conventional write circuit, when the write driving circuit switches on a corresponding conventional bit line to a bias voltage end to drive the electric potential of the corresponding conventional bit line to change, the negative pulse voltage supply circuit can switch on the bias voltage end from a working voltage to a different negative pulse voltage according to the received negative pulse voltage control signal. The writing system can effectively shorten time required by writing a procedure and accelerate the operating frequency of the memory.

Description

Writing system for static random access memory and storer

Technical field

The present invention relates to a kind of writing system and relevant apparatus, relate in particular to a kind of can the change and control negative pulse voltage that each routine writes the bit line and import opportunity to promote static RAM and write correctness and to promote writing speed, quicken the bit line and recover (bit-linerecovery) and shorten the storage operation cycle (cycle), improve the writing system for static random access memory and the relevant apparatus of operating frequency according to the current potential that emulation writes the bit line.

Background technology

Semiconductor memory is the indispensable square of constructing in the contemporary electronic systems.In general, be provided with many storage unit in the storer, these storage unit are arranged in matrix, and the storage unit of same delegation (row) is coupled to same character line, and the storage unit of same row then is coupled to same bit line (or a pair of/one group two differential each other bit lines).For the data in each storage unit of access, each (group) bit line can be respectively via one (group) corresponding write the write circuit that the bit line is coupled to a correspondence, also via the circuit that reads that the bit line is coupled to a correspondence that reads of one (group) correspondence.Signal potential on the character line is trench gate (pass gate) mechanism in the may command storage unit then.When the trench gate of this storage unit of the pairing character line of storage unit conducting was machine-processed, its pairing write circuit just can be via writing the pairing bit line of this storage unit of bit line traffic control data are write to this storage unit; Perhaps, this storage unit can be controlled corresponding bit line and read the bit line according to its stored data, makes and reads the data that circuit can read this cell stores.

In general storage unit, its trench gate mechanism be with one (to) the trench gate transistor realizes.But, along with the evolution of semiconductor advanced technologies and the demand of low-work voltage, this trench gate transistor has been more and more difficult satisfy simultaneously read with write between the demand of conflicting mutually.

With the static RAM is example, basic 6 transistors (6T) storage unit mainly cooperates a pair of trench gate transistor to form by pair of phase inverters, the output terminal that the input end of each phase inverter is connected to another phase inverter forms the lock circuit of fastening of a positive feedback, the output terminal of two phase inverters can be considered two differential each other back end, reflects the bit data of cell stores and anti-phase bit data respectively.Each back end is coupled to one of them of a pair of bit line respectively via a trench gate transistor.

During data in will reading a storage unit, can be precharged to the noble potential of a logical one earlier to a pair of bit line that should storage unit; When two trench gate transistors all after the conducting, the phase inverter that input end is connected to the logic one data node can attempt the bit line of correspondence is discharged to the electronegative potential of logical zero via the trench gate transistor of logic zero data node.But, when discharge was initial, the transistor in this this phase inverter of trench gate transistor AND gate can be equivalently in the dividing potential drop of carrying out on the logic zero data node between noble potential and electronegative potential.In this case, if the transistorized conducting resistance of trench gate is lower, the current potential of logic zero data node will be partial to noble potential.In case the current potential of this back end too high (surpassing the critical potential of fastening lock circuit resolution logic 0 and logical one), the data that will make this cell stores are by counter-rotating (flip) mistakenly.Read interference for fear of this kind, the trench gate transistor should be a transistor that ducting capacity is lower, conducting resistance is higher.

On the contrary, in the time will writing data to a storage unit, the a pair of bit line of this storage unit correspondence can be discharged and recharged respectively to noble potential and electronegative potential in advance, and after the trench gate transistor turns, two bit lines will discharge and recharge two back end respectively via each self-corresponding trench gate transistor.At this moment, the transistorized conducting resistance of trench gate should be low more good more, so that the electrical potential energy of back end is charged and discharged apace to the current potential of corresponding bit line.

By top description as can be known, what the trench gate transistor was faced is the demand that reads and write mutual contradiction, and especially in the low-work voltage storer that uses advanced technologies, its conflict is more and more obvious.At the conflict on this performance requirement, a solution is to adopt the lower weak trench gate transistor of ducting capacity to satisfy the demand that reads in storage unit, and write fashionable carrying out data, it then is the negative pulse voltage (transient negative pulse) that when the current potential with logical zero bit line is discharged to electronegative potential, on this bit line, imports transient state, strengthen the transistorized conducting degree of trench gate with this, reduce its conducting resistance, the demand of writing also can be taken into account.

But, this solution need accurately be controlled the opportunity that the transient state negative pulse voltage imports.To realize this solution smoothly, should wait the current potential of logical zero bit line to be discharged to the bit line so far that just the transient state negative pulse voltage is coupled behind the electronegative potential fully, the electrical potential energy of this bit line further is reduced to below the logical zero electronegative potential.If the bit line so far that when the current potential of this bit line also is not discharged to electronegative potential fully, just negative pulse voltage is coupled, this negative pulse voltage data of (flip) this cell stores of can't reversing effectively then.Because the drift and the unusual fluctuation of technology, operating voltage and/or temperature all can influence the time that the bit line discharges and recharges, jointly, the time point that imports negative pulse voltage also becomes and is difficult to correct control.

Summary of the invention

Therefore, the present invention proposes a kind of transient state negative pulse voltage solution based on emulation bit line, to control the opportunity that negative pulse voltage imports according to the potential change of emulation bit line, make time point that negative pulse voltage imports can be adaptively with drift adjustment automatically of technology/operating voltage/temperature with variation.In addition, the present invention further after data write, utilizes negative pulse voltage supply circuit and emulation bit line to quicken the speed that the bit line recovers (bit-line recovery), thereby shortens the write cycle of storer, make to write that to carry out ground compacter, accelerate the operating frequency of storer.

The invention provides a kind of writing system, be applied to a storer, this writing system includes: an emulation write circuit writes the bit line corresponding at least one emulation, to drive the current potential change that this emulation writes the bit line; One negative pulse voltage control circuit is coupled to this emulation and writes the bit line, and its current potential that writes the bit line according to this emulation produces the negative pulse voltage control signal of a correspondence; And at least one conventional write circuit, each conventional write circuit writes the bit line corresponding at least one routine, and each conventional write circuit includes: a write driver circuit, it has a bias terminal; This write driver circuit writes bit line conducting to the current potential of this bias terminal with matching convention and changes with the current potential that drives this routine and write the bit line; And a negative pulse voltage supply circuit, being coupled to this bias terminal, its current potential according to this negative pulse voltage control signal switches one of them that makes this bias terminal conducting to an operating voltage and a negative pulse voltage; Wherein this operating voltage and this negative pulse voltage inequality.

The present invention provides a kind of storer in addition, includes: an emulation write circuit writes the bit line corresponding at least one emulation, to drive the current potential change that this emulation writes the bit line; One negative pulse voltage control circuit is coupled to this emulation and writes the bit line, and its current potential that writes the bit line according to this emulation produces the negative pulse voltage control signal of a correspondence; And at least one conventional write circuit, each conventional write circuit writes the bit line corresponding at least one routine, and each conventional write circuit includes: a write driver circuit, it has a bias terminal; This write driver circuit writes bit line conducting to the current potential of this bias terminal with matching convention and changes with the current potential that drives this routine and write the bit line; And a negative pulse voltage supply circuit, being coupled to this bias terminal, its current potential according to this negative pulse voltage control signal switches one of them that makes this bias terminal conducting to an operating voltage and a negative pulse voltage; Wherein this operating voltage and this negative pulse voltage inequality.

Technology of the present invention can be implemented in the writing system of a storer.In one embodiment of this invention, be provided with an emulation write circuit in the writing system of the present invention, a negative pulse voltage control circuit, a conventional transmission circuit, an emulation transmission circuit and at least one conventional write circuit.Wherein, each conventional write circuit writes the bit line corresponding to a pair of routine, and each writes the bit line to routine and is coupled to the storage unit of same row via a pair of bit line of correspondence, and these storage unit can the actual storage data that is used for.Include one in each conventional write circuit and select circuit, a pre-charge circuit, a write driver circuit and a negative pulse voltage supply circuit.The character line sequential control mechanism of storer then can provide a character line clock signal and a write control signal according to a time clock.Character line clock signal is used for controlling beginning and the end that writes flow process, and write control signal then is used for controlling the operation sequential of each interlock circuit.The conventional transmission circuit that is coupled to each conventional write circuit promptly is used for write control signal is transferred to each conventional write circuit; The emulation transmission circuit that is coupled to each conventional write circuit equally then is used for a negative pulse voltage control signal is transferred to negative pulse voltage supply circuit in each conventional write circuit with the coupling sequential of control negative pulse voltage.

In each conventional write circuit, select circuit to be coupled to pre-charge circuit and write driver circuit; Write on the bit line for negative pulse voltage being coupled to corresponding routine, each write driver circuit has a bias terminal.Write fashionable, select circuit to receive one and write data, write by a pair of routine of correspondence so that write driver circuit is able to according to writing data and to select one of them routine in the bit line and write the bit line, and the current potential of the write control signal that transmits according to the conventional transmission circuit routine selecting whether will to select writes bit line conducting to the current potential of bias terminal and changes to drive its current potential.Pre-charge circuit then has the pair of control end, and it can be according to the current potential of control end and matching convention is write bit line conducting to one second operating voltage (as operating supply voltage) change with the current potential that drives routine and write the bit line.Pre-charge circuit and write driver circuit are complementally to drive routine according to write control signal to write the bit line; For example, can be provided with a pair of p channel metal oxide semiconductor transistor in the pre-charge circuit, its source electrode is coupled to operating supply voltage, and drain electrode is coupled to a routine respectively and writes the bit line, and the grid of two transistor just becomes the pair of control end.Accordingly, then be provided with a pair of n channel metal oxide semiconductor transistor in the write driver circuit, the routine that the drain electrode of each n channel metal oxide semiconductor transistor couples a correspondence respectively writes the bit line, the grid of two n channel metal oxide semiconductor transistors then becomes the pair of control end, and two source electrodes then are coupled in together as bias terminal.Select circuit promptly to be coupled to the control end of pre-charge circuit and write driver circuit, the routine of selecting to drive with the control write driver circuit writes the bit line; The negative pulse voltage supply circuit then is coupled to the bias terminal of write driver circuit, switches with the current potential of the negative pulse voltage control signal that transmits according to the emulation transmission circuit to make this bias terminal conducting to another operating voltage (for example being a ground end operating voltage) one of them with a negative pulse voltage; This negative pulse voltage and operating voltage are different.In the present invention, the signal path load of the signal path load of conventional transmission circuit transmission write control signal and emulation transmission circuit transmission negative pulse voltage control signal is mated mutually, is followed the trail of the propagation delay that (tracking) write control signal transfers to each conventional write circuit so that the negative pulse voltage control signal transfers to the propagation delay of each conventional write circuit.

On the other hand, be similar to conventional write circuit, the emulation write circuit also writes the bit line corresponding at least one emulation, has emulation pre-charge circuit and emulation write driver circuit equally, to drive the current potential change that emulation writes the bit line.Emulation writes the bit line also is coupled to same row via the emulation bit line of correspondence emulation storage unit.Circuit structure and layout that emulation storage unit/emulation bit line/emulation writes the bit line are duplicate (replica) that each storage unit/bit line/routine writes the bit line under the conventional write circuit, and emulation pre-charge circuit/emulation write driver circuit also is matched with the pre-charge circuit/write driver circuit in the conventional write circuit respectively, makes emulation write current potential on the bit line and changes response (speed) and the conventional current potential that writes on the bit line and change and respond (speed) and mate mutually and identical.But, emulation storage unit needn't be used for storing actual data.The emulation pre-charge circuit is controlled by character line clock signal, changes to drive its current potential to select whether emulation is write bit line conducting to operating supply voltage according to character line clock signal.The emulation write driver circuit is then the same with write driver circuit in each conventional write circuit to have bias terminal, and is controlled by write control signal.And negative pulse voltage control circuit of the present invention promptly is to change according to the current potential that emulation writes the bit line aforesaid negative pulse voltage control signal is provided.

Write fashionablely when storer of the present invention advancing row, write control signal can make the emulation write circuit begin that emulation is write the bit line and be discharged to electronegative potential by noble potential, equivalence in is exactly to respond in the conventional current potential transformation that writes the bit line of simulation.Finish current potential and change when emulation writes the bit line, the negative pulse voltage control circuit just can be in view of the above and in the negative pulse voltage control signal current potential with correspondence change the opportunity of reflecting that negative pulse voltage imports.Write control signal and negative pulse voltage control signal can be respectively transfer to write driver circuit and negative pulse voltage supply circuit in each conventional write circuit via conventional transmission circuit and emulation transmission circuit.That is to say, writing the bit line from emulation begins current potential and changes to the mistiming that imports between negative pulse voltage and can copy to one by one each conventional write circuit via the operation of write control signal/conventional transmission circuit and negative pulse voltage control signal/emulation transmission circuit, make each conventional write circuit can both wait until that the routine of its correspondence writes the bit line and finishes and just import negative pulse voltage after current potential changes, thereby optimize the opportunity that negative pulse voltage imports.

In other words, the present invention changes according to the current potential that emulation writes the bit line to control negative pulse voltage and be directed into the opportunity that each routine writes the bit line; Even routine writes the timing drift that the response that discharges and recharges on the bit line makes a variation to some extent with technology/operating voltage/temperature its current potential is changed, the time point that negative pulse voltage imports still can be followed the current potential change that routine writes the bit line adaptively, effectively brings into play the due function of negative pulse voltage.

In each conventional write circuit of the present invention, can be provided with an electric capacity, one first commutation circuit and one second commutation circuit in each negative pulse voltage supply circuit.This electric capacity has one first end and one second end, and first commutation circuit promptly is coupled to first end, with the current potential according to control of Electric potentials first end of negative pulse voltage control signal.Second commutation circuit then is coupled to the bias terminal of write driver circuit and second end of electric capacity, to select whether the bias terminal conducting of write driver circuit extremely will be held operating voltage according to the negative pulse voltage control signal.When second commutation circuit with the bias terminal conducting during to the ground end operating voltage of electronegative potential, first commutation circuit then is maintained at first end of electric capacity the noble potential of operating supply voltage, to charge into electric charge between first end of electric capacity and second end, making has a positive electricity pressure reduction between first end and second end.Under the control of negative pulse voltage control signal, when second commutation circuit stopped that the bias terminal conducting extremely held operating voltage, first commutation circuit can be held first end of electric capacity the electronegative potential of operating voltage on the contrary with switching to; At this moment, because the positive electricity pressure reduction that forms because of the electric charge accumulation between first end and second end, second end of electric capacity just can provide a negative pulse voltage of end operating voltage to the bias terminal of write driver circuit with being lower than.

In another embodiment of the present invention, negative pulse voltage supply circuit in each conventional write circuit includes a delay circuit in addition, be coupled to second commutation circuit, be used for postponing the current potential change of negative pulse voltage control signal, make second commutation circuit be able to select whether operating voltage extremely to be held in the bias terminal conducting according to the negative pulse voltage control signal after postponing.More particularly, after data write, when the bit line began to recover, this delay circuit can postpone the operation sequential of second commutation circuit; When first commutation circuit is changed first end-grain cutting of electric capacity to noble potential again, second commutation circuit can be after one postpones the period just again with the second end conducting to electronegative potential.Among this postpones the period, the voltage difference that is formed by the electric charge accumulation in the noble potential of first end and the electric capacity can provide a positive pulse voltage to be coupled to routine via write driver circuit and write the bit line, quickens the bit line recovery (bit-line recovery) that routine writes the bit line.

In another embodiment of the present invention, whether the selection circuit of each conventional write circuit then is coupled in the bias terminal of write driver circuit separately, make to select circuit also can select with the control end of bias terminal conducting to pre-charge circuit according to the write control signal current potential.When write control signal makes write driver circuit stop to drive and when making pre-charge circuit begin to drive routine to write the bit line, select circuit can be further with the control end conducting to bias terminal, make negative pulse voltage that the negative pulse voltage supply circuit provides to bias terminal equally also can conducting to control end.In this case, the conducting degree of pre-charge circuit can be enhanced, and improves its driving force, equally also can quicken the bit line recovery (bit-line recovery) that routine writes the bit line.

In an embodiment more of the present invention, writing system of the present invention is provided with an emulation negative pulse voltage supply circuit and in addition and writes the finishing control circuit.Emulation negative pulse voltage supply circuit can be the duplicating of each negative pulse voltage supply circuit in the conventional write circuit.Be similar to the operation situation of negative pulse voltage supply circuit in the conventional write circuit, emulation negative pulse voltage supply circuit is coupled to the bias terminal of emulation write driver circuit, switches one of them to operating voltage (end operating voltage) and the emulation negative pulse voltage of the bias terminal conducting that makes the emulation write driver circuit with the current potential that writes the bit line according to emulation with similarly being; Wherein, operating voltage and emulation negative pulse voltage are different.Emulation negative pulse voltage supply circuit can write in emulation and duplicate in the conventional write circuit negative pulse voltage supply circuit on the bit line for routine writes the operation that the bit line provides negative pulse voltage, makes emulation write current potential on the bit line and changes situation and more level off to the current potential that routine writes on the bit line and change situation.

In each emulation storage unit on emulation bit line, the present invention can use an emulation storage unit to be used as the index storage unit; This emulation storage unit can store the emulated data of a correspondence according to the current potential that emulation writes the bit line, just can produce an end signal and write the finishing control circuit according to emulated data, make character line clock signal/write control signal be able to change current potential, and change with this current potential and to finish to write flow process according to the current potential of end signal.That is to say, when writing flow process and begin to control each conventional write circuit data are write to conventional storage unit with write control signal, the emulation write circuit also can be under the control of write control signal writes the bit line with an emulated data via emulation and writes to emulation storage unit as the index storage unit.When the primary data of script in the index storage unit changes (by writing) for emulated data, the flow process that writes of representing emulation to write on the bit line is finished smoothly, and the present invention just can finish to write flow process according to this situation: write the finishing control circuit and can reflect this situation in end signal, and impel and write flow process and finish as early as possible.So, just can effectively shorten the required time of flow process that writes, the operating cycle of reduction storer, the operating frequency of speeds up memory.

In order to make your juror can further understand feature of the present invention and technology contents, see also following about detailed description of the present invention and accompanying drawing, yet the accompanying drawing formula only provide with reference to and explanation, be not to be used for the present invention is limited.

Description of drawings

Fig. 1 is the circuit diagram of one embodiment of the invention.

What Fig. 2 illustrated is the waveform sequential of coherent signal among Fig. 1.

Fig. 3 is the circuit diagram of another embodiment of the present invention.

What Fig. 4 illustrated is the waveform sequential of coherent signal among Fig. 3.

Fig. 5 is the circuit diagram of further embodiment of this invention.

What Fig. 6 illustrated is the waveform sequential of coherent signal among Fig. 5.

Fig. 7 is the circuit diagram of yet another embodiment of the invention.

What Fig. 8 illustrated is the waveform sequential of coherent signal among Fig. 7.

Description of reference numerals in the above-mentioned accompanying drawing is as follows:

The 10a-10d storer

The 12a-12d writing system

WDa (0)-WDa (n), WDb (0)-WDb (n), WDc (0)-WDc (n), WDd (0)-conventional write circuit of WDd (n)

DD, DDd emulation write circuit

WBL (0)-WBL (n), WBLB (0)-WBLB (n) routine writes the bit line

BL (0)-BL (n), BLB (0)-BLB (n) bit line

WL (m) character line

DWBL emulation writes the bit line

DBL emulation bit line

Ce (m, 0)-ce (m, n) storage unit

Dce emulation storage unit

Sw1-Sw2, Sw1b, Sw1d-Sw2d commutation circuit

NBL, NBLb negative pulse voltage supply circuit

DNBL emulation negative pulse voltage supply circuit

Tr negative pulse voltage control circuit

The DU delay circuit

The AD auxiliary circuit

NEGY, NEGY (0)-NEGY (n) negative pulse voltage control signal

RT, RTI, RTI (0)-RTI (n) write control signal

WLE character line clock signal

WTE writes end signal

The CK time clock

Di (0)-Di (n) writes data

The PU pre-charge circuit

DPU emulation pre-charge circuit

The WU write driver circuit

DWU, DWUd emulation write driver circuit

SU, SUc select circuit

Ts, Ts1 transmission circuit

WTEU writes the finishing control circuit

RC, RCx load

V, G operating voltage

Bs, bs1, b1-b3, b1d-b3d impact damper

I0-i3, id1-id2, i0d phase inverter

A1-A3 and door

The nA1-nA2 Sheffer stroke gate

Pd, Nd, P1-P2, N1-N3, Pa-Pb, Na-Nb, ga-gb, P1 '-P2 ', N1 '-N2 ', gad-gbd, Nd2, N3d transistor

D0-d7, ACC (0)-ACC (n), BCC (0)-BCC (n), da-db, da1-db1, Z0 (0)-Z0 (n), Z1 (0)-Z1 (n), DACC, DBCC, k1-k4 node

Cnb, Cdnb electric capacity

AA1-AA5, AB1-AB5, AD1-AD10 arrow

Td, tu period

Dv, dV voltage difference

Embodiment

Please refer to Fig. 1, what it was illustrated is the circuit diagram of storer one embodiment 10a of the present invention.In this embodiment, storer 10a can be a static RAM, and it has a plurality of storage unit that are arranged as matrix; Be coupled to the storage unit of character line WL (m) on capable jointly with m, it comprised the storage unit ce (m, 1) of storage unit ce (m, 0), the 1st row of the 0th row wait the storage unit ce that is listed as to n (m, n).Shown in the embodiment of Fig. 1, storage unit ce (m, n) be to form pair of phase inverters in, run between operating voltage V (operating supply voltage) and the G (hold operating voltage) by p channel metal oxide semiconductor transistor Pa, Pb and n NMOS N-channel MOS N crystal Na, Nb; Wherein, the phase inverter that transistor Pa/Na forms with node db as its input end, with node da as output terminal; The then staggered node da/db that is coupled to of the input end/output terminal of the phase inverter that transistor Pb/Nb forms.N channel metal oxide semiconductor transistor ga, gb are the trench gate transistor, and the drain/source of two transistor is respectively coupled to node da/da1 and node db/db1, and grid then is coupled to character line WL (m) equally.Node da1/db1 is respectively coupled to a pair of bit line BL (n)/BLB (n).Node da/db is two back end, and (m, n) stored data and these data is anti-phase to reflect storage unit ce respectively.Be coupled to the actual storage data that is used for of each storage unit meeting of above-mentioned each bit line BL (0)/BLB (0), BL (1)/BLB (1) and even BL (n)/BLB (n), these bit lines form the storage space of storer 10a, so can be considered the conventional bit line of storer 10a.

As discussed earlier, when want reading cells ce (m, during data in n), bit line BL (n)/BLB (n) all can be precharged to the noble potential of a logical one earlier; When character line WL (m) makes trench gate transistor ga and gb after the conducting, if storage unit ce (m, n) the bit data that store in are logical one, because the phase inverter that transistor Pb/Nb forms is the logic one data node at the input end of node da, so phase inverter can attempt bit line BLB (n) is discharged to the electronegative potential of logical zero via the trench gate transistor gb of logic zero data node db, make the machine-processed (not shown) that reads in the storer be judged storage unit ce (m, n) the middle bit data that store.But, when discharge was initial, the drain/source conducting resistance of trench gate transistor gb and the drain/source conducting resistance of transistor Nb can be equivalently in the dividing potential drops of carrying out on the logic zero data node db between noble potential (bit line BLB (n)) and electronegative potential (operating voltage G).In this case, if the conducting resistance of trench gate transistor gb is lower, the current potential of logic zero data node db will be partial to noble potential, in case the current potential of this back end too high (surpassing the critical potential of fastening lock circuit resolution logic 0 and logical one), will be taken as is logical one and make storage unit ce (m, n) data that store are by counter-rotating (flip) mistakenly.For fear of this kind situation, trench gate transistor ga and gb should be transistors that ducting capacity is lower, conducting resistance is higher.Relatively, writing fashionablely, trench gate transistor ga and gb then are that ducting capacity heals height better.And the present invention will solve the demand contradictory of this kind between reading and writing with the negative pulse voltage technology.

Promptly write in each each storage unit for data are effectively reached, also, be provided with a writing system 12a among the storer 10a of the present invention in order to realize negative pulse voltage technology of the present invention to conventional bit line; In the embodiment in figure 1, be provided with an emulation write circuit DD among the writing system 12a of the present invention, a negative pulse voltage control circuit Tr, a conventional transmission circuit Ts, an emulation transmission circuit Ts1 and each conventional write circuit WDa (0), WDa (1) etc. are to WDa (n).Each can be respectively writes conventional write circuit WDa (0), WDa (1) that bit line WBL (0)/WBLB (0), WBL (1)/WBLB (1) is coupled to a correspondence to WBL (n)/WBLB (n) to WDa (n) via the routine of a pair of correspondence to (routine) bit line BL (0)/BLB (0), BL (1)/BLB (1) and even BL (n)/BLB (n), makes conventional write circuit WDa (0), WDa (1) bit data Di (0), the Di (1) of correspondence can be write to storage unit on each conventional bit line to Di (n) to WDa (n).These conventional write circuit WDa (0) have identical circuit structure and operation logic to WDa (n), below are that example illustrates with n conventional write circuit WDa (n) promptly.

In Fig. 1, the character line sequential control mechanism (not shown) of storer 10a can provide a character line clock signal WLE and a synchronous write control signal RT according to a time clock CK (not shown).Character line clock signal WLE is used for controlling beginning and the end that writes flow process, and write control signal RT then controls the operation sequential of each interlock circuit.Being coupled to each conventional write circuit WDa (0), WDa (1) promptly is used for write control signal RT is transferred to each conventional write circuit WDa (0), WDa (1) to WDa (n) to the conventional transmission circuit Ts of WDa (n); The emulation transmission circuit Ts1 that is coupled to each conventional write circuit equally then is used for a negative pulse voltage control signal NEGY is transferred to each conventional write circuit WDa (0), WDa (1) coupling opportunity with the control negative pulse voltage to the WDa (n).As shown in Figure 1, can include an impact damper bs among the conventional transmission circuit Ts, so that write control signal RT is transmitted as write control signal RTI; Then the signal that negative pulse voltage control circuit Tr exports is transmitted as negative pulse voltage control signal NEGY among the emulation transmission circuit Ts1 with an impact damper bs1.In order to represent the operation of conventional transmission circuit Ts/ emulation transmission circuit Ts1, the write control signal RTI and the negative pulse voltage control signal NEGY that are transferred to n conventional write circuit WDa (n) are denoted as RTI (n) and NEGY (n) respectively separately; For example, conventional transmission circuit Ts/ emulation transmission circuit Ts1 can be transmitted as write control signal RTI/ negative pulse voltage control signal NEGY write control signal RTI (0)/negative pulse voltage control signal NEGY (0) and input to conventional write circuit WDa (0) respectively.In other words, n conventional write circuit WDa (n) can receive single bit to be written and write data Di (n), and drive corresponding routine according to the sequential control of write control signal RTI (n) and negative pulse voltage control signal NEGY (n) and write bit line WBL (n) and WBLB (n), with will write data Di (n) write to storage unit ce (m, n).

As shown in fig. 1, include one among the conventional write circuit WDa (n) and select circuit SU, a pre-charge circuit PU, a write driver circuit WU and a negative pulse voltage supply circuit NBL.Select circuit SU to be coupled to pre-charge circuit PU and write driver circuit WU.In the embodiment in figure 1, be provided with a pair of p channel metal oxide semiconductor transistor P1 and P2 in the pre-charge circuit PU, its source electrode is coupled to operating voltage V, drain electrode is coupled to routine at node d1 and d2 respectively and writes bit line WBL (n) and WBLB (n), and the grid of two transistor P1/P2 just can be considered the pair of control end.Accordingly, then be provided with a pair of n channel metal oxide semiconductor transistor N1 and N2 among the write driver circuit WU, the drain electrode of transistor N1 and N2 is coupled to routine at node d1 and d2 respectively and writes bit line WBL (n) and WBLB (n), two grids also can be regarded as the pair of control end, and the source electrode of two transistor then is coupled to Node B CC (n) together with the bias terminal as write driver circuit WU.Select to be provided with among the circuit SU two and door (AND Gate) A1 and A2 and a phase inverter i1, two are respectively coupled to the grid (control end of pre-charge circuit PU and write driver circuit WU just) of transistor P1/N1 and P2/N2 with the output terminal of door A1 and A2, with the input end of door A1 and A2 in node d4 reception write control signal RTI (n).On the other hand, select circuit SU to receive and write data Di (n), write data Di (n) and can input to another input end with door A2 at node d3, and via another input end that inputs to after phase inverter i1 anti-phase with door A1.In other words, select circuit SU to be coupled to the control end of pre-charge circuit PU and write driver circuit WU, write the bit line so that write driver circuit WU can write the routine that selection will drive among bit line WBL (n) and the WBLB (n) in two routines according to writing data Di (n); Under the control of write control signal RTI (n), pre-charge circuit PU and write driver circuit WU then can complementally drive routine and write bit line WBL (n)/WBLB (n).

In conventional write circuit WDa (n), negative pulse voltage supply circuit NBL is coupled to the bias terminal of write driver circuit WU, switches with the negative pulse voltage control signal NEGY (n) that transmits according to emulation transmission circuit Ts1 to make this bias terminal conducting to one of them of an operating voltage G and a negative pulse voltage; This negative pulse voltage and operating voltage G are different.Be provided with a capacitor C nb and commutation circuit Sw1 and Sw2 in the negative pulse voltage supply circuit NBL of the present invention.Capacitor C nb has one first end and one second end.In the embodiment in figure 1, be provided with a phase inverter i2 and impact damper b1 and b2 among the commutation circuit Sw1 (can be considered first commutation circuit); Phase inverter i2 is anti-phase after be coupled to node ACC (n) by impact damper b2 with negative pulse voltage control signal NEGY (n), commutation circuit Sw1 is promptly through node ACC (n) (with impact damper b1) thus and be coupled to first end of capacitor C nb, to control the current potential of this first end according to the current potential of negative pulse voltage control signal NEGY (n).Commutation circuit Sw2 (second commutation circuit) then can be realized by a n channel metal oxide semiconductor transistor N3, the drain electrode of this transistor N3 is coupled to the bias terminal of write driver circuit WU and second end of capacitor C nb in Node B CC (n), whether grid then is coupled to node ACC (n), to select according to negative pulse voltage control signal NEGY (n) the bias terminal conducting of the write driver circuit WU ground end operating voltage G to its source electrode.Under the control of negative pulse voltage control signal NEGY (n), when commutation circuit Sw2 with the bias terminal conducting of Node B CC (n) during to the ground end operating voltage G of electronegative potential, commutation circuit Sw1 then can be maintained at node ACC (n) noble potential of logical one via impact damper b1, and between first end of capacitor C nb and second end, charge into electric charge, make first end (node ACC (n)) and second end (Node B CC (n)) that a positive electricity pressure reduction be arranged.After negative pulse voltage control signal NEGY (n) changed current potential, commutation circuit Sw2 stopped operating voltage G is extremely held in the bias terminal conducting of Node B CC (n), and commutation circuit Sw1 then can hold node ACC (n) electronegative potential of operating voltage G with being maintained at; At this moment, because the positive electricity pressure reduction that forms because of the electric charge accumulation between first end and second end, second end of capacitor C nb just can provide the negative pulse voltage of end operating voltage G to the bias terminal of write driver circuit WU via Node B CC (n) with being lower than.

On the other hand, be similar to each conventional write circuit WDa (0) to WDa (n), emulation of the present invention (dummy) write circuit DD also writes bit line DWBL corresponding at least one emulation, have emulation pre-charge circuit DPU and emulation write driver circuit DWU equally, to drive the current potential change that emulation writes bit line DWBL.Emulation writes bit line DWBL also is coupled to same row via the emulation bit line DBL of correspondence emulation storage unit (not shown); But, these emulation storage unit needn't be used for storing actual data, also can not be counted in the storage space of storer 10a.Circuit structure and layout that emulation storage unit/emulation bit line/emulation writes the bit line are that each storage unit/bit line/routine writes duplicating of bit line under the conventional write circuit, so that the equivalent capacity ohmic load RC that emulation writes on the bit line DWBL is identical with the equivalent capacity ohmic load RC that routine writes on bit line WBL (n) or the WBLB (n); And emulation pre-charge circuit DPU/ emulation write driver circuit DWU also is matched with the pre-charge circuit PU/ write driver circuit WU among the conventional write circuit WDa (n) respectively, make emulation write current potential on the bit line DWBL change response (speed) can and routine write current potential on bit line WBL (n) or the WBLB (n) and change and respond (speed) and mate mutually and identical.

Though only being shown among Fig. 1, an emulation writes bit line DWBL, but still can being provided with a pair of emulation among the storer 10a of the present invention, to write the bit line (for example be a similar storage unit ce (m, differential memory location n)) with the emulation storage unit that is coupled to same row via a pair of emulation bit line; Write fashionable, because having only among the conventional write circuit WDa (n) single routine to write the bit line can be written into driver element WU and drive that to change current potential (be that routine writes one of them of bit line WBL (n) and WBLB (n), by writing data Di (n) decision), duplicate the current potential that single routine writes the bit line and change response so the present invention can be only write bit line DWBL with single emulation, and also illustrate this emulation is write the driving of bit line DWBL among emulation pre-charge circuit DPU among Fig. 1 and the emulation write driver circuit DWU with a p channel metal oxide semiconductor transistor Pd and a n channel metal oxide semiconductor transistor Nd.Transistor Pd/Nd can be respectively with pre-charge circuit PU/ write driver circuit WU in transistor P1/N1 (with P2/N2) coupling; Wherein, the grid of transistor Pd receives character line clock signal WLE, makes emulation pre-charge circuit DPU select whether emulation to be write bit line DWBL conducting according to character line clock signal WLE and changes to drive its current potential to operating voltage V.The source electrode of transistor Nd then can be considered the bias terminal of emulation write driver circuit DWU, end operating voltage G with being coupled to; Its grid then is controlled by write control signal RT.Negative pulse voltage control circuit Tr of the present invention then is coupled to emulation and writes bit line DWBL, produces aforesaid negative pulse voltage control signal NEGY with the current potential that writes bit line DWBL according to emulation.Negative pulse voltage control circuit Tr can comprise a phase inverter i0, and it is anti-phase for being the negative pulse voltage control signal NEGY of digital form among the emulation transmission circuit Ts1 to be used for that emulation is write the current potential of bit line DWBL.

In the present invention, via the setting of impact damper bs and bs1 and suitable allocation plan, the signal path resistance capacitance load RCx of conventional transmission circuit Ts transmission write control signal RTI can mate mutually with the signal path resistance capacitance load RCx of emulation transmission circuit Tr1 transmission negative pulse voltage control signal NEGY, is followed the trail of (tracking) write control signal RTI to the propagation delay of WDa (n) and transfers to the propagation delay of each conventional write circuit WDa (0) to WDa (n) so that negative pulse voltage control signal NEGY transfers to each conventional write circuit WDa (0).

The embodiment of continuity Fig. 1 please refer to Fig. 2; What Fig. 2 illustrated is the waveform sequential of each coherent signal among Fig. 1, with this operation logic of the present invention is described; The transverse axis of each waveform is the time, and the longitudinal axis is signal potential (as a voltage potential).As previously mentioned, the mechanism of the sequential control among the storer 10a can produce character line clock signal WLE and write control signal RT according to a time clock CK.When storer 10a will begin to write fashionable, character line clock signal WLE can change into noble potential (current potential of operating supply voltage V) by electronegative potential (as the current potential of ground end operating voltage G), write control signal RT also changes noble potential into by electronegative potential jointly, shown in arrow A A1.The noble potential of write control signal RT can make the transistor Nd conducting among the emulation write driver circuit DWU, begin to copy and write bit line DWBL and be discharged to electronegative potential by precharge noble potential, be exactly to change response in the equivalence, as arrow A A2 indication at the conventional current potential that writes the bit line of simulation.Change when emulation writes bit line DWBL current potential, negative pulse voltage control circuit Tr will make negative pulse voltage control signal NEGY change to noble potential by the electronegative potential of correspondence jointly, shown in arrow A A3; Just as discussed earlier, after current potential that routine writes the bit line changes electronegative potential into, be only the preferable opportunity that imports negative pulse voltage, thus the liter of write control signal RT/ negative pulse voltage control signal NEGY along between the opportunity that just can reflect negative pulse voltage importing mistiming.

Write control signal RT and negative pulse voltage control signal NEGY can be via conventional transmission circuit Ts and emulation transmission circuit Ts1 and are transferred to write driver circuit WU and the negative pulse voltage supply circuit NBL of each conventional write circuit WDa (0) to the WDa (n) respectively.In the example of Fig. 1, because conventional write circuit DWa (0) is nearer apart from emulation write circuit DD, and the distance of conventional write circuit DWa (n) is far away, so both have one section propagation delay by the received write control signal RTI (0) of conventional transmission circuit Ts with RTI (n); As shown in Figure 2, can be poor for some time between the liter of write control signal RTI (0) and RTI (n) edge.In like manner, also can be poor for some time between the negative pulse voltage control signal NEGY (0) that received by emulation transmission circuit Ts1 of conventional write circuit WDa (0) and WDa (n) and the NEGY (n).But, as previously mentioned, because conventional transmission circuit Ts and emulation transmission circuit Ts1 are couplings mutually, thus the mistiming between write control signal RT/ negative pulse voltage control signal NEGY, write control signal RTI (0)/negative pulse voltage control signal NEGY (0) and even between mistiming write control signal RTI (n)/negative pulse voltage control signal NEGY (n) between mistiming can mutual tracking and reach unanimity.That is to say, writing bit line DWBL from emulation begins current potential and changes (by write control signal RT control) and can copy to each conventional write circuit WDa (0) one by one to WDa (n) as ripple via the operation of conventional transmission circuit Ts and emulation transmission circuit Ts1 to the mistiming of finishing electric potential change (being reflected in negative pulse voltage control signal NEGY), making conventional write circuit WDa (0) can write bit line WBL (0) or WBLB (0) in the routine of correspondence finishes current potential and changes the back and import negative pulse voltage, conventional write circuit WDa (n) waits until that then routine writes bit line WBL (n) or WBLB (n) finishes current potential change back importing negative pulse voltage, optimizes the opportunity that negative pulse voltage imports with this.

In conventional write circuit WDa (n), after negative pulse voltage control signal NEGY (n) changed to noble potential by electronegative potential, the current potential of node ACC (n) can be changed into electronegative potential by noble potential; Before this current potential changed, node ACC (n) noble potential originally can make the transistor N3 conducting among the commutation circuit Sw2, the current potential of Node B CC (n) was held with being maintained at the electronegative potential of operating voltage G.But, after current potential changed, commutation circuit Sw1 can make the current potential of node ACC (n) change into electronegative potential, and the transistor N3 among the commutation circuit Sw2 then becomes not conducting; Between its two ends, keep voltage difference dv originally because the electric charge of capacitor C nb can be inclined to, be rendered as so the voltage of Node B CC (n) will be held operating voltage G with being lower than a negative pulse voltage-| dv|, indicated as arrow A A4; And this negative pulse voltage will be coupled to one of them that routine writes bit line WBL (n) or WBLB (n) via the bias terminal (source electrode of transistor N1 and N2) of write driver circuit WU.For example, if will (m writes logical one in n), and then write driver circuit WU can select to drive routine and write bit line WBLB (n), and makes it be discharged to electronegative potential by precharge noble potential under the control of write control signal RTI (n) at storage unit ce; After its current potential was discharged to electronegative potential, negative pulse voltage control signal NEGY (n) can start negative pulse voltage mechanism in good time, makes negative pulse voltage can be coupled to routine and writes among the bit line WBLB (n), shown in arrow A A5.Via the coupling of bit line BLB (n), this negative pulse voltage can be strengthened the conducting degree of gate groove transistor gb, reduces the conducting resistance between its source electrode-drain electrode.Thus, make even the circuit structure of gate groove transistor ga/gb and topological design comparatively are partial to the demand that reads that conducting resistance increases between its source electrode-drain electrode, but writing fashionablely, negative pulse voltage still can be enough to compensate the demand that writes.

In Fig. 2, for convenience of description, be to represent Node B CC among the conventional write circuit WDa (0), and represent Node B CC among the conventional write circuit WDa (n) with BCC (n) with BCC (0).Because negative pulse voltage control signal NEGY (n) postpones in negative pulse voltage control signal NEGY (0), the current potential on the Node B CC (n) changes the current potential that also can postpone on Node B CC (0) and changes; But, just as described above, these propagation delays can be followed the trail of mutually, guarantee that the opportunity of negative pulse voltage importing is correct.By the explanation of Fig. 2 as can be known, the present invention changes according to the current potential that emulation writes bit line DWBL to control negative pulse voltage and be directed into the opportunity that routine writes bit line WBL (n) or WBLB (n); Even routine writes the response variation to some extent with technology/operating voltage/temperature that discharges and recharges on the bit line, the time point that negative pulse voltage imports still can be followed current potential that routine writes the bit line adaptively and be changed and adjust, and effectively brings into play the due function of negative pulse voltage.In addition, it is many groups of conventional write circuits in the may command storer of the present invention that the present invention also only needs single one group of emulation write circuit DD, can reduce the layout burden (overhead) because of realizing that negative pulse voltage mechanism is caused in each conventional write circuit.

When write finish after, character line clock signal WLE can change electronegative potential into by noble potential; Jointly, the emulation pre-charge circuit DPU among the emulation write circuit DD is switched on and emulation is write bit line DWBL and is precharged to noble potential again, shown in arrow A B1.The current potential that emulation writes the bit line changes makes negative pulse voltage control signal NEGY (0) change to the current potential of NEGY (n) thereupon, shown in arrow A B2.The current potential that receives among the negative pulse voltage control signal NEGY (n) as conventional write circuit WDa (n) changes, commutation circuit Sw1 switches to noble potential with node ACC (n) again, and commutation circuit Sw2 then makes node BCC (n) get back to ground auspicious operating voltage G (shown in arrow A B3) again.Meanwhile, commutation circuit Sw1 charges to first end of capacitor C nb via node ACC (n) and impact damper b1, and it is charged to noble potential.On the other hand, change current potential with character line clock signal WLE, and even write control signal RT RTI (n) also can change electronegative potential into by noble potential one by one; In the control of the electronegative potential of write control signal RTI (n) down, the pre-charge circuit PU among the conventional write circuit WDa (n) can conducting and routine that script is discharged writes bit line WBL (n) or WBLB (n) is precharged to noble potential again.Routine is write the bit line, and to carry out precharge again promptly be to carry out the bit line to recover (bit-line recovery), allows routine write bit line WBL (n) and can be charged to noble potential again with WBLB (n), prepares to carry out writing or reading next time.

Please refer to Fig. 3, its demonstration be the circuit diagram of the storer second embodiment 10b of the present invention.Be similar to the embodiment among Fig. 1, in the storer 10b of Fig. 3, also be provided with the storage unit of arranged, same array storage unit writes the bit line via bit line, the routine of correspondence and is coupled to each conventional write circuit among the writing system 12b, to realize the writing mechanism of storer 10b; In addition, storer 10b also is provided with emulation bit line DBL/ emulation and writes bit line DWBL and corresponding emulation write circuit DD.The negative pulse voltage control signal NEGY that cooperates character line clock signal WLE, write control signal RT and negative pulse voltage control circuit Tr, add the operation of conventional transmission circuit Ts/ emulation transmission circuit Ts1, just can control the sequential that writes of each conventional write circuit.For example, storage unit ce (m, n) promptly be to write bit line WBL (n)/WBLB (n) via bit line BL (n)/BLB (n) with routine to be coupled to corresponding conventional write circuit WDb (n), make conventional write circuit WDb (n) can under the sequential control of write control signal RTI (n)/negative pulse voltage control signal NEGY (n), will write data Di (n) write to storage unit ce (m, n).

On the other hand, be similar to the conventional write circuit WDa (n) among Fig. 1, to WDb (n), also be respectively equipped with pre-charge circuit PU, write driver circuit WU and select circuit SU at each conventional write circuit WDb (0) of Fig. 3; But, the difference to some extent then of the negative pulse voltage supply circuit NBLb among Fig. 3.In negative pulse voltage supply circuit NBLb, also be provided with capacitor C nb and commutation circuit Sw1b and Sw2; In addition, also between node ACC (n) and commutation circuit Sw2, be provided with a delay circuit DU among the negative pulse voltage supply circuit NBLb of Fig. 3 in addition.Be similar to the commutation circuit Sw1 among Fig. 1, the commutation circuit Sw1b among Fig. 3 also is provided with a phase inverter i2 and impact damper b1, to come first end of control capacitance Cnb and the voltage of node ACC (n) according to negative pulse voltage control signal NEGY (n) anti-phase; Commutation circuit Sw2 can utilize a transistor N3 to realize equally.Then can be provided with in the delay circuit DU one with door A3 and impact damper b2 and b3; This input end with door A3 directly is coupled to node ACC (n), and another input end then is coupled to node ACC (n) again via impact damper b2/b3; Then couple the grid of transistor N3 with the output terminal of door A3, with the conducting of oxide-semiconductor control transistors N3.When the bit line begins to recover, delay circuit DU can postpone the sequential control of negative pulse voltage control signal NEGY (n) to commutation circuit Sw2, makes commutation circuit Sw2 be able to select whether operating voltage G extremely to be held in bias terminal (Node B CC (the n)) conducting of write driver circuit WU according to the negative pulse voltage control signal NEGY (n) after postponing.

The embodiment of continuity Fig. 3, the operation situation of storer 10b can be illustrated with the waveform sequential of Fig. 4 signal.As discussing among Fig. 1/Fig. 2, when writing to finish the time, character line clock signal WLE can change into electronegative potential by noble potential, emulation writes bit line DWBL and is charged to noble potential again, and make each negative pulse voltage control signal NEGY (0) change into electronegative potential by noble potential to NEGY (n), shown in arrow A B2.But, circuit structure by delay circuit DU can be found out, when the current potential of negative pulse voltage control signal NEGY (n) is changed into electronegative potential by noble potential and when making the current potential of node ACC (n) change into noble potential by electronegative potential, the grid potential of transistor N3 can not changed into noble potential by electronegative potential simultaneously immediately; Because the delay period td that impact damper b2/b3 imports, the signal that wait impact damper b2/b3 output also after electronegative potential is changed into noble potential, just can make the grid potential of transistor N3 change noble potential into by electronegative potential with door A3.That is to say, when commutation circuit Sw1 again with node ACC (n) (first end of capacitor C nb just) when charging to noble potential, commutation circuit Sw2 can wait one section to postpone just again operating voltage G extremely to be held in Node B CC (n) (second end of capacitor C nb) conducting after the period td again, shown in arrow A B3.And postpone among the period td at this, the current potential that the voltage difference that is formed by electric charge accumulation in the noble potential of node ACC (n) and the electric capacity will make node BCC (n) by the voltage of holding operating voltage G originally with being lower than-| the dv| one section voltage difference dV that rises, and being coupled to routine via write driver circuit WU, the current potential rising meeting on the Node B CC (n) writes bit line WBL (n) or WBLB (n), shown in arrow A B4.Under this coupling is arranged, write the bit line and can be charged to noble potential quickly again writing the routine that is discharged to negative pulse voltage during carrying out originally, quicken the conventional bit line that writes the bit line and recover (bit-line recovery).The size of voltage difference dV can depend on the voltage difference between operating voltage V and the ground end operating voltage G, reaches the ratio that capacitor C nb and bit line BL (n) or BLB (n) go up electric capacity.

Please refer to Fig. 5; The embodiment of extension bitmap 1, what Fig. 5 illustrated is the circuit of the another embodiment 10c of storer of the present invention.Be similar to the embodiment among Fig. 1, in the storer 10c of Fig. 5, also be provided with the storage unit of arranged, same array storage unit writes the bit line via bit line, the routine of correspondence and is coupled to each conventional write circuit among the writing system 12c, to realize the writing mechanism of storer 10c.In addition, storer 10c also is provided with emulation bit line DBL/ emulation and writes bit line DWBL and corresponding emulation write circuit DD; Cooperate the negative pulse voltage control signal NEGY of character line clock signal WLE, write control signal RT, negative pulse voltage control circuit Tr, add the operation of conventional transmission circuit Ts/ emulation transmission circuit Ts1, with regard to the sequential that writes of each conventional write circuit of may command.For example, conventional write circuit WDc (n) writes bit line WBL (n)/WBLB (n), bit line BL (n)/BLB (n) via routine to be coupled to storage unit ce (m, n), so that under the sequential control of write control signal RTI (n)/negative pulse voltage control signal NEGY (n), will write data Di (n) write to storage unit ce (m, n).

In Fig. 5 embodiment, the conventional write circuit WDc of the present invention (n) also has pre-charge circuit PU, write driver circuit WU, negative pulse voltage supply circuit NBL and selects circuit SUc.First three circuit can adopt identical circuit structure with negative pulse voltage supply circuit NBL with pre-charge circuit PU, the write driver circuit WU among Fig. 1.But, in Fig. 5, select the circuit structure of circuit SUc then different.In selecting circuit SUc, p channel metal oxide semiconductor transistor P1 ', n channel metal oxide semiconductor transistor N1 ' form a phase inverter, the output terminal of this phase inverter is coupled to the control end (grid of transistor P1 just) of pre-charge circuit PU at node Z0 (n), input end then is coupled to the output terminal of Sheffer stroke gate (NAND Gate) nA1 in node d6, with Sheffer stroke gate nA1 form one with the door; This function with door just be similar among Fig. 1 select circuit SU with door A1, write the anti-phase of data Di (n) at an input end receiving node d3, and receive write control signal RTI (n) at node d4.But, among Fig. 1 and door A1 operate between operating voltage V and the ground end operating voltage G; But in Fig. 5, the source electrode of transistor N1 ' then is coupled to Node B CC (n) with the bias terminal (source electrode of transistor N1/N2) of write driver circuit WU.

In like manner, select p channel metal oxide semiconductor transistor P2 ', n channel metal oxide semiconductor transistor N2 ' among the circuit SUc to form another phase inverter, output terminal is coupled to another control end (grid of transistor P2) of pre-charge circuit PU at node Z1 (n), input end then is coupled to the output terminal of Sheffer stroke gate nA2 in node d7, form another and door with Sheffer stroke gate nA2, its function just be similar among Fig. 1 select circuit SU with door A2, write data Di (n) at an input end receiving node d3, and receive write control signal RTI (n) at node d4.But, the source electrode of transistor N2 ' equally is that bias terminal with write driver circuit WU is coupled to Node B CC (n) together.

In other words, in Fig. 5 embodiment, whether the selection circuit SUc of the conventional write circuit WDc of the present invention (n) can be separately be coupled in the bias terminal of write driver circuit WU, make to select circuit SUc can also be further to select the bias terminal conducting of Node B CC (n) control end (node Z0 (n) and Z1 (n)) to pre-charge circuit PU according to the current potential of write control signal RTI (n).Please in the lump with reference to figure 6, its signal be the waveform sequential of each coherent signal among the storer 10c.When the bit line begins to recover, when write control signal RTI (n) changes into electronegative potential by noble potential and makes write driver circuit WU stop to drive, and when making pre-charge circuit PU begin to drive routine to write bit line WBL (n)/WBLB (n), select circuit SUc can be further with the control end conducting of pre-charge circuit PU bias terminal to Node B CC (n), make negative pulse voltage that negative pulse voltage supply circuit NBL provides to Node B CC (n) equally also can conducting to the control end of node Z0 (n) with Z1 (n), allow the current potential of control end hold operating voltage G, shown in arrow A B5 with being lower than.Thus, in pre-charge circuit PU, the conducting degree of its p channel metal oxide semiconductor transistor P1/P2 will be enhanced, and improves its driving force, quickens the bit line recovery (bit-line recovery) that routine writes the bit line.With regard to the potential change sequential of node Z0 (n) with Z1 (n), to write bit line WBLB (n) discharge if write data Di (n) to routine for logical one, what then illustrate among Fig. 6 is the waveform of node Z1 (n).If writing data Di (n) is logical zero, what then illustrate among Fig. 6 then is the waveform of node Z0 (n).In addition, also represent n the node among the conventional write circuit WDc (n) among Fig. 6, so Z0 (0)/Z1 (0) is the node among the conventional write circuit WDc (0) with Z0 (n)/Z1 (n).

Expand the embodiment of Fig. 1, that illustrate among Fig. 7 is an embodiment 10d again of storer of the present invention.In the writing system 12d of the storer 10d of Fig. 7, each conventional write circuit WDd (n) writes bit line WBL (n)/WBLB (n), bit line BL (n)/BLB (n) via routine and is coupled to storage unit ce (m, n), so that under the sequential control of write control signal RTI (n)/negative pulse voltage control signal NEGY (n), will write data Di (n) write to storage unit ce (m, n).Among the embodiment of Fig. 7, can adopt the conventional write circuit WDa (n) among Fig. 1 to realize each conventional write circuit WDd (n).

On the other hand, except emulation bit line DBL/ emulation writes bit line DWBL and corresponding emulation write circuit DDd, also set up an emulation negative pulse voltage supply circuit DNBL, an auxiliary circuit AD and among the writing system 12d and write finishing control circuit WTEU, and on emulation bit line DBL, adopted an emulation storage unit Dce to be used as a representational index storage unit.In Fig. 7, storer 10d can be a static RAM that is formed by 6 transistors (6T) storage unit, so emulation storage unit Dce also is one 6 transistor cells, it includes pair of phase inverters id1 and id2, and a pair of as gate groove transistorized n channel metal oxide semiconductor transistor gad and gbd: transistor gad is coupled between node k4 and the k2, the end of transistor gbd is coupled to phase inverter id1 and id2 in node k1, and the other end then is coupled to emulation bit line DBL in node k3; But, these two transistorized grids of gate groove all directly are coupled to operating voltage V.In emulation write circuit DDd, p channel metal oxide semiconductor transistor Pd in the emulation pre-charge circuit DPU is controlled by character line clock signal WLE at its grid, n channel metal oxide semiconductor transistor Nd in the emulation write driver circuit DWUd then is controlled by write control signal RT at grid, its source electrode then can be considered a bias terminal, is coupled to the node DBCC of emulation negative pulse voltage supply circuit DNBL.

Emulation negative pulse voltage supply circuit DNBL can be duplicating of the middle negative pulse voltage supply circuit NBL of conventional write circuit WDd (n), so also be provided with commutation circuit Sw1d, Sw2d and capacitor C dnb among the emulation negative pulse voltage supply circuit DNBL.Be provided with impact damper b1d to b3d among the commutation circuit Sw1d, be used for simulating the effect of impact damper b1/b2 and phase inverter i2 and phase inverter i0 among the commutation circuit Sw1; N channel metal oxide semiconductor transistor N3d among the commutation circuit Sw2d then can mate with the transistor N3 among the commutation circuit Sw2.Be similar to the operation situation of negative pulse voltage supply circuit NBL, emulation negative pulse voltage supply circuit DNBL is coupled to the bias terminal (node DBCC) that emulation writes bit line DWBL and emulation write driver circuit DWUd, switches one of them that an operating voltage G and an emulation negative pulse voltage are extremely held in the bias terminal conducting that makes emulation write driver circuit DWUd with the current potential that writes bit line DWBL according to emulation.The emulation negative pulse voltage that emulation negative pulse voltage supply circuit DNBL provides can be identical with the negative pulse voltage that negative pulse voltage supply circuit NBL provides, and the both holds operating voltage G with being lower than.In other words, emulation negative pulse voltage supply circuit DNBL can write that to duplicate negative pulse voltage supply circuit NBL on the bit line DWBL be that routine writes bit line WBL (n)/WBLB (n) operation of negative pressure is provided in emulation, makes emulation write current potential on the bit line DWBL and changes situation and more level off to the current potential that routine writes WBL on the bit line (n)/WBLB (n) and change.

In writing system 12d, auxiliary circuit AD can realize with a phase inverter i0d and a n channel metal oxide semiconductor transistor Nd2; Phase inverter i0d exports character line clock signal WTE after anti-phase to the grid of transistor Nd2, makes auxiliary circuit AD be able to select whether the node k4 conducting of emulation storage unit Dce extremely to be held operating voltage G according to character line clock signal WTE.When character line clock signal WLE was electronegative potential, the transistor Nd2 meeting conducting among the auxiliary circuit AD stored the electronegative potential logical zero at the node k2 of emulation storage unit Dce, and makes node k1 store the noble potential logical one; Just in emulation storage unit Dec, store a primary data in the equivalence.Write the then available phase inverter i3 of finishing control circuit WTEU and realize, its current potential with node k2 is anti-phase to be one to write end signal WTE.Except providing character line clock signal WLE and write control signal RT with negative pulse voltage control signal NEGY via negative pulse voltage control circuit Tr, the write control signal RTI (n) of conventional transmission circuit Ts and the negative pulse voltage control signal NEGY (n) of emulation transmission circuit Ts1 control the sequential that writes of conventional write circuit WDd (n), sequential control mechanism (not shown) among the storer 10d also can change according to the current potential that writes end signal WTE comes control character line clock signal WLE/ write control signal RT to change its current potential, and changes with this current potential and to finish to write flow process.Please continue with reference to figure 8, what it was illustrated is the waveform sequential of each coherent signal current potential among Fig. 7 storer 10d.

Described as the front, as character line clock signal WLE when still being electronegative potential, auxiliary circuit AD can write the primary data of logical one at the node k1 of emulation storage unit Dce, and emulation writes bit line DWBL and also is precharged to noble potential.The node DACC of emulation negative pulse voltage supply circuit DNBL is a noble potential, then conducting and the current potential that makes node DBCC is ground end operating voltage G of commutation circuit Sw2d.When writing flow process and begin, WLE changes into noble potential by electronegative potential along with character line clock signal, and write control signal RT also can change into noble potential by electronegative potential.At this moment, the emulation write driver circuit DWUd among the emulation write circuit DDd will begin to drive the current potential that emulation writes on the bit line DWBL and change, and the emulated data of a logical zero will be write to the node k1 of emulation storage unit Dce in the equivalence exactly.The current potential that emulation is write bit line DWBL be discharged to by noble potential electronegative potential with write emulated data during, in case emulation writes the potential drop of bit line DWBL be low to moderate electronegative potential after, the current potential of node DACC also can decrease to electronegative potential, and close commutation circuit Sw2d, make capacitor C dnb provide the emulation negative pulse voltage of end operating voltage G, shown in arrow A D2, AD3 and AD4 at node DBCC with being lower than.This emulation negative pulse voltage can strengthen cross-pressure between the gate-to-source of gate groove transistor gbd, strengthens its conducting degree, reduces the conducting resistance between its drain electrode-source electrode, makes the electrical potential energy of node k1 correctly change into logical zero by logical one apace.

On the other hand, when write control signal RT changes into noble potential by electronegative potential, this current potential change also can trigger via the write control signal RTI (n) of conventional transmission circuit Ts transmission conventional write circuit WDd (n) begin with correspondence write data Di (n) write to conventional storage unit ce (m, n); After emulation writes bit line DWBL and changes electronegative potential into, negative pulse voltage control circuit Tr also can change into noble potential by electronegative potential with negative pulse voltage control signal NEGY, make the negative pulse voltage control signal NEGY (n) of emulation transmission circuit Ts1 transmission can control the opportunity that conventional write circuit WDd (n) imports negative pulse voltage, shown in arrow A D1.

When emulation storage unit Dce when the logical one primary data of node k1 changes the logical zero emulated data into, representative writes flow process and finishes smoothly, and the present invention just can finish to write flow process according to this situation: write finishing control circuit WTEU and can make and write end signal WTE and change into electronegative potential by noble potential, and the sequential control of storer 10d mechanism just can be changed into electronegative potential with character line clock signal WLE by noble potential in view of the above, impel to write flow process and finish as early as possible, shown in arrow A D5.So, just can effectively shorten and write required time of flow process, the time sequential routine of speeds up memory.In Fig. 8, period tu is used for representing to write the time that flow process is saved; Because the emulation storage unit Dce/ emulation write circuit DDd as the index storage unit can represent conventional storage unit ce (m among the storer 10d, n)/behavior of conventional write circuit WDd (n), utilize the embodiment of the present invention in Fig. 7, write and opportunity that flow process finishes just can dynamically follow the operation of storer and adjust, needn't prolong for the variation of resisting process/operating voltage/temperature and write flow process.

WLE changes into electronegative potential by noble potential along with character line clock signal, and storer 10d also begins to carry out the bit line and recovers (bit-line recovery); Each write control signal RT and RTI (0) can begin to change into electronegative potential (arrow A D6) by noble potential to RTI (n) one by one, emulation writes bit line DWBL and is precharged to noble potential (arrow A D7) again, node DACC among the emulation negative pulse voltage supply circuit DNBL is switched to noble potential (arrow A D8), and node DBCC then is switched on to ground end operating voltage G (arrow A D9).WLE comes back to electronegative potential along with character line clock signal, and auxiliary circuit AD can write the primary data of logical one again again on the node k1 of emulation storage unit Dce, also can change noble potential into and write end signal WTE, shown in arrow A D10 thereupon.

In summary, the present invention is based on the emulation storage unit/emulation of duplicating and writes bit line/emulation write circuit (with emulation negative pulse voltage supply circuit) and simulate response and behavior that conventional storage unit/routine writes bit line/conventional write circuit (and negative pulse voltage supply circuit), come dynamically to determine to import the opportunity of negative pulse voltage in view of the above, can also utilize the negative pulse voltage supply circuit to quicken the bit line and recover (bit-line recovery), and can dynamically adjust the opportunity that flow process finishes that writes further, quicken the whole flow process that writes, shorten the operating cycle of storer, accelerate the operating frequency of storer.Because the present invention can only control the negative pulse voltage sequential of many conventional write circuits with an emulation write circuit, so can reduce the burden (overhead) that realizes negative pulse voltage mechanism.In addition, the present invention in the embodiment of Fig. 3 and/or Fig. 5 also can with Fig. 7 embodiment combination; For example, emulation negative pulse voltage supply circuit DNBL among Fig. 7 and conventional negative pulse voltage supply circuit NBL can both change into the negative pulse voltage supply circuit NBLb among Fig. 3, with the advantages of Fig. 3 and Fig. 7 together.Though the embodiment of Fig. 1, Fig. 3, Fig. 5 and Fig. 7 is to be that example illustrates with the static RAM, technical spirit of the present invention may extend to other various storeies, for example is register or the like.

In sum; though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any those of ordinary skills; without departing from the spirit and scope of the present invention; when can doing various changes and retouching, so protection scope of the present invention is as the criterion when looking appended the scope that claim defined.

Claims (16)

1. a writing system is applied to a storer, and this writing system includes:

One emulation write circuit writes the bit line corresponding at least one emulation, to drive the current potential change that this emulation writes the bit line;

One negative pulse voltage control circuit is coupled to this emulation and writes the bit line, and its current potential that writes the bit line according to this emulation produces the negative pulse voltage control signal of a correspondence; And

At least one conventional write circuit, each conventional write circuit writes the bit line corresponding at least one routine, and each conventional write circuit includes:

One write driver circuit, it has a bias terminal; This write driver circuit writes bit line conducting to the current potential of this bias terminal with matching convention and changes with the current potential that drives this routine and write the bit line; And

One negative pulse voltage supply circuit is coupled to this bias terminal, and its current potential according to this negative pulse voltage control signal switches one of them that makes this bias terminal conducting to an operating voltage and a negative pulse voltage; Wherein this operating voltage and this negative pulse voltage inequality.

2. writing system as claimed in claim 1, wherein this emulation write circuit is selected whether to drive the current potential change that this emulation writes the bit line according to a write control signal, and this writing system includes in addition:

One conventional transmission circuit, be coupled to each conventional write circuit, be used for this write control signal is transferred to each conventional write circuit, and the write control signal that the write driver circuit in each conventional write circuit transmits according to this routine transmission circuit is selected whether matching convention will to be write bit line conducting to this bias terminal and is changed with the current potential that drives this routine and write the bit line; And

One emulation transmission circuit is coupled to each conventional write circuit, is used for this negative pulse voltage control signal is transferred to negative pulse voltage supply circuit in each conventional write circuit;

Wherein, this routine transmission circuit transmits the signal path load of this write control signal and signal path load that this emulation transmission circuit transmits this negative pulse voltage control signal is mated mutually, so that the propagation delay that this negative pulse voltage control signal transfers to each conventional write circuit is followed the trail of the propagation delay that this write control signal transfers to each conventional write circuit.

3. writing system as claimed in claim 1, wherein, the negative pulse voltage supply circuit in each conventional write circuit includes:

One electric capacity, it has one first end and one second end;

One first commutation circuit is coupled to this first end, and it is according to the current potential of this first end of control of Electric potentials of this negative pulse voltage control signal; And

One second commutation circuit is coupled to bias terminal and this second end of this write driver circuit, and whether it selects this bias terminal conducting to this operating voltage according to this negative pulse voltage control signal; When this second commutation circuit not with this bias terminal conducting during to this operating voltage, provide this negative pulse voltage by second end of this electric capacity to this bias terminal.

4. writing system as claimed in claim 3, wherein, the negative pulse voltage supply circuit in each conventional write circuit includes in addition:

One delay circuit is coupled to this second commutation circuit; Whether the current potential that this delay circuit is used for postponing this negative pulse voltage control signal changes, make this second commutation circuit be able to select this bias terminal conducting to this operating voltage according to the negative pulse voltage control signal after postponing.

5. writing system as claimed in claim 1, wherein, each conventional write circuit writes the bit line corresponding to a pair of routine, and includes in addition in each conventional write circuit:

One selects circuit, is coupled to this write driver circuit, is used for receiving one and writes data, makes this write driver circuit be able to write data and by this routine is write and to select a routine in the bit line and write the bit line and drive this routine of selecting and write the bit line according to this.

6. writing system as claimed in claim 1 wherein, includes in each conventional write circuit in addition:

One pre-charge circuit is coupled to the pairing routine of each conventional write circuit and writes the bit line, and has a control end; This pre-charge circuit writes bit line conducting to one second operating voltage according to the current potential of this control end with the routine of correspondence and changes with the current potential that drives this routine and write the bit line; And

One selects circuit, is coupled between this control end and this bias terminal, and whether its current potential according to this write control signal is selected this control end conducting to this bias terminal.

7. writing system as claimed in claim 1, wherein, this emulation write circuit is selected whether to drive the current potential change that this emulation writes the bit line according to the current potential of a character line clock signal, and this writing system includes in addition:

One emulation storage unit is coupled to this emulation via an emulation bit line and writes the bit line; This emulation storage unit can store the emulated data of a correspondence according to the current potential that this emulation writes the bit line; And

One writes the finishing control circuit, and it produces one according to this emulated data and writes end signal, and the current potential that makes this character line clock signal be able to write according to this end signal changes current potential.

8. writing system as claimed in claim 7 wherein includes in this emulation write circuit:

One emulation write driver circuit is coupled to this emulation and writes the bit line; This emulation write driver circuit has a bias terminal, and it writes bit line conducting to the bias terminal of this emulation write driver circuit with this emulation and changes with the current potential that drives this emulation and write the bit line;

And this writing system includes in addition:

One emulation negative pulse voltage supply circuit, be coupled to the bias terminal of this emulation write driver circuit, its current potential that writes the bit line according to this emulation switches one of them to this operating voltage and the emulation negative pulse voltage of the bias terminal conducting that makes this emulation write driver circuit; Wherein this operating voltage and this emulation negative pulse voltage are different.

9. storer includes:

One emulation write circuit writes the bit line corresponding at least one emulation, to drive the current potential change that this emulation writes the bit line;

One negative pulse voltage control circuit is coupled to this emulation and writes the bit line, and its current potential that writes the bit line according to this emulation produces the negative pulse voltage control signal of a correspondence; And

At least one conventional write circuit, each conventional write circuit writes the bit line corresponding at least one routine, and each conventional write circuit includes:

One write driver circuit, it has a bias terminal; This write driver circuit writes bit line conducting to the current potential of this bias terminal with matching convention and changes with the current potential that drives this routine and write the bit line; And

One negative pulse voltage supply circuit is coupled to this bias terminal, and its current potential according to this negative pulse voltage control signal switches one of them that makes this bias terminal conducting to an operating voltage and a negative pulse voltage; Wherein this operating voltage and this negative pulse voltage inequality.

10. storer as claimed in claim 9, wherein this emulation write circuit is selected whether to drive the current potential change that this emulation writes the bit line according to a write control signal, and this storer includes in addition:

One conventional transmission circuit, be coupled to each conventional write circuit, be used for this write control signal is transferred to each conventional write circuit, and the write control signal that the write driver circuit in each conventional write circuit transmits according to this routine transmission circuit is selected whether matching convention will to be write bit line conducting to this bias terminal and is changed with the current potential that drives this routine and write the bit line; And

One emulation transmission circuit is coupled to each conventional write circuit, is used for this negative pulse voltage control signal is transferred to negative pulse voltage supply circuit in each conventional write circuit;

Wherein, this routine transmission circuit transmits the signal path load of this write control signal and signal path load that this emulation transmission circuit transmits this negative pulse voltage control signal is mated mutually, so that the propagation delay that this negative pulse voltage control signal transfers to each conventional write circuit is followed the trail of the propagation delay that this write control signal transfers to each conventional write circuit.

11. storer as claimed in claim 9, wherein, the negative pulse voltage supply circuit in each conventional write circuit includes:

One electric capacity, it has one first end and one second end;

One first commutation circuit is coupled to this first end, and it is according to the current potential of this first end of control of Electric potentials of this negative pulse voltage control signal; And

One second commutation circuit is coupled to bias terminal and this second end of this write driver circuit, and whether it selects this bias terminal conducting to this operating voltage according to this negative pulse voltage control signal; When this second commutation circuit not with this bias terminal conducting during to this operating voltage, provide this negative pulse voltage by second end of this electric capacity to this bias terminal.

12. storer as claimed in claim 11, wherein, the negative pulse voltage supply circuit in each conventional write circuit includes in addition:

One delay circuit is coupled to this second commutation circuit; Whether the current potential that this delay circuit is used for postponing this negative pulse voltage control signal changes, make this second commutation circuit be able to select this bias terminal conducting to this operating voltage according to the negative pulse voltage control signal after postponing.

13. storer as claimed in claim 9, wherein, each conventional write circuit writes the bit line corresponding to a pair of routine, and includes in addition in each conventional write circuit:

One selects circuit, is coupled to this write driver circuit, is used for receiving one and writes data, makes this write driver circuit be able to write data and by this routine is write and to select a routine in the bit line and write the bit line and drive this routine of selecting and write the bit line according to this.

14. storer as claimed in claim 9 wherein, includes in each conventional write circuit in addition:

One pre-charge circuit is coupled to the pairing routine of each conventional write circuit and writes the bit line, and has a control end; This pre-charge circuit writes bit line conducting to one second operating voltage according to the current potential of this control end with the routine of correspondence and changes with the current potential that drives this routine and write the bit line; And

One selects circuit, is coupled between this control end and this bias terminal, and whether its current potential according to this write control signal is selected this control end conducting to this bias terminal.

15. storer as claimed in claim 9, wherein, this emulation write circuit is selected whether to drive the current potential change that this emulation writes the bit line according to the current potential of a character line clock signal, and this storer includes in addition:

One emulation storage unit is coupled to this emulation via an emulation bit line and writes the bit line; This emulation storage unit can store the emulated data of a correspondence according to the current potential that this emulation writes the bit line; And

One writes the finishing control circuit, and it produces one according to this emulated data and writes end signal, and the current potential that makes this character line clock signal be able to write according to this end signal changes current potential.

16. storer as claimed in claim 15 wherein includes in this emulation write circuit:

One emulation write driver circuit is coupled to this emulation and writes the bit line; This emulation write driver circuit has a bias terminal, and it writes bit line conducting to the bias terminal of this emulation write driver circuit with this emulation and changes with the current potential that drives this emulation and write the bit line;

And this storer includes in addition:

One emulation negative pulse voltage supply circuit, be coupled to the bias terminal of this emulation write driver circuit, its current potential that writes the bit line according to this emulation switches one of them to this operating voltage and the emulation negative pulse voltage of the bias terminal conducting that makes this emulation write driver circuit; Wherein this operating voltage and this emulation negative pulse voltage are different.

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