CN103971729B - Bias provides circuit, storage compartments controller and memory circuitry - Google Patents

Abstract

The invention discloses the present invention and provide circuit, storage compartments controller and memory circuitry for one bias.Bias provides circuit to be positioned at storage compartments controller, and storage compartments controller is for accessing a storage compartments in memory circuitry.Bias provides circuit to comprise: the first switch, and it is to maintain conducting state；First current path, comprises: second switch, and it is to turn on according to the first Dc bias；And, the second current path, comprise: the 3rd switch, it is to turn on according to one second Dc bias；And, the 4th switch, it is to select the control of signal to turn on according to a storage compartments.Wherein the level of wordline bias changes according to level and the conducting state of this second current path of operation voltage.

Description

Bias provides circuit, storage compartments controller and memory circuitry

Technical field

The invention relates to that a kind of bias provides circuit and storage compartments controller and memory circuitry, and particularly It is related to a kind of bias through word line driving voltage access memorizer and circuit, storage compartments controller and memorizer electricity are provided Road.

Background technology

The control signal of memory circuitry operates according to running voltage Vdd (such as: 1.8 volts or 3 volts).But Be, if memory array be in reading, program, the operator scheme such as erasing time, then must additionally use operation voltage Vpp (such as: 5 Volt or 10 volts etc.).

Although, for different types of memorizer, control mode also can some difference.But, with regard to address decoding and because of Operator scheme is answered to select the consideration of different operating voltage Vpp the most substantially similar.For purposes of illustration only, following citing be with or non- Door flash memory (NOR flash) is main.

Refer to Fig. 1, it illustrates the basic framework schematic diagram of memory circuitry.It is, in general, that memory circuitry to be accessed Time, need to consider two control towards, the first chooses correct storage address；It second must be for selected memorizer Address, in response to the type of operator scheme, it is provided that suitable operation voltage Vpp.

First, for the addressing of memorizer, memory circuitry first can receive to access through address buffering circuit 14 Storage address.Afterwards, then pass through array decoding circuit, row decoder15 and row decoding circuit (column decoder) The decoding of 16, becomes binary address decoding in the address of memory array 17.

It is, in general, that memory array 17 can divide into multiple storage compartments (sector).Wherein, each storage compartments Each self-contained a plurality of wordline (wordline driver, referred to as WL), each wordline is used further to drive corresponding son storage Device array.

On the other hand, for the offer of operation voltage Vpp, overall situation bias circuit (Global Wordline Bias, letter It is referred to as GWLBS) 13 can be according to the control of mode setting circuit 11, the high voltage that high-pressure generator 12 is provided, be converted to operation Voltage Vpp.

In order to make memory circuitry carry out correct operation, wordline must be by the control to operation voltage Vpp, could be right Word line driving voltage should be produced in the operator scheme of storage address.So, selected storage address can be allowed certain Be read out or write, erasing etc. operates.

Therefore, high-pressure generator 12, the overall situation bias circuit 13 and memory array 17 between, if can be at correct time point Handover operation voltage Vpp, becomes as considerable ring during design memory circuitry.

Along with the difference of memory span Yu application, the quantity of the storage compartments that memory circuitry is comprised and wordline is the most not Identical.For purposes of illustration only, it is assumed hereinafter that memory array comprises 64 storage compartments, the most each storage compartments comprises by 4 4 sub-memory arrays that wordline drives.

When accessing memory element (memory cell), first memory circuitry can select storage compartments.Its After, in further the most selected storage compartments, select a wherein wordline.Wordline, after receiving word line driving voltage, will be taken It is coordinated line and memory element is controlled.Wherein, the level of word line driving voltage can be according to the operator scheme of memory element Change.

Referring to Fig. 2, it is the memory circuitry of prior art, controls through overall situation bias circuit and the 0th storage compartments Device, the schematic diagram of access the 0th storage compartments.

It is assumed herein that storage address to be accessed is positioned at the 0th storage compartments (SEC0) 29, and the 0th storage compartments 29 district It is divided into four sub-memory arrays (not painting formula).These four sub-memory arrays respectively by the 0th wordline WL0, the first wordline WL1, Second wordline WL2, the 3rd wordline WL3 drive.

By in graphic it can be seen that the low level exported by high-pressure generator 12 operates voltage AVXRD operates with high level Voltage AVXHV, can be respectively sent to overall situation bias circuit 21 and the 0th storage compartments controller 20.

Overall situation bias circuit 21 can operate voltage AVXHV according to low level operation voltage AVXRD with high level, produces further Raw read operation bias WLBSRD chooses bias WLBS with high pressure.Thereafter, then read operation is biased WLBSRD to choose with high pressure Bias WLBS voltage is sent to the 0th storage compartments controller 20.

0th storage compartments controller 20 comprises: bias provides circuit (BIASDEC) 25, operation voltage selecting circuit (AVXP) 23, word line selection circuit (WLDEC) 27 and four wordline 28.

Wherein, operation voltage selecting circuit 23 is used for receiving low level operation voltage AVXRD and high level operation voltage AVXHV, and select person therein as the operation voltage Vpp being supplied to word line selection circuit 27.

Additionally, bias provides circuit 25 can choose bias WLBS voltage according to read operation bias WLBSRD with high pressure, produce New word line bias Vbias is to word line selection circuit 27.

Therefore, word line selection circuit 27 automatic bias respectively provides circuit 25 to receive wordline bias Vbias, and certainly operates electricity Pressure selection circuit receives operation voltage Vpp.Afterwards, word line selection circuit 27 further produces word line driving voltage to chosen Wordline 28.

Refer to Fig. 3, it illustrates the schematic diagram of word line selection circuit of prior art.

When, in the 0th storage compartments 29 corresponding to word line selection circuit 27, there is no any storage address being selected Time, represent the 0th storage compartments 29 and be in standby mode.Therefore it provides select to the 0th storage compartments of nmos pass transistor MB0 Signal PreB0, and be supplied to nmos pass transistor MB1 first storage compartments select signal PreB1 be 0V.Now, NMOS Transistor MB0, MB1 all present off state, and the word line selection circuit 27 of Fig. 3 can't operate.

When the 0th storage compartments 29 is selected, it is provided that select signal to the 0th storage compartments of nmos pass transistor MB0 PreB0, and be supplied to nmos pass transistor MB1 first storage compartments select signal PreB1 be 1.8V.Now, NMOS is brilliant Body pipe MB0 is the most switched on nmos pass transistor MB1.Related, the 0th section chooses the voltage of node Ssec0 also because NMOS is brilliant The reason that body pipe MB0, MB1 and ground voltage (Gnd=0V) turn on, and it is 0 volt.

As it was previously stated, after the 0th storage compartments 29 is selected, wordline need to be further transmitted through and drives the 0th storage compartments 29 Interior quantum memory array.Accordingly, it would be desirable to select signal PreA0 to select the 0th wordline WL0, the first character through null character again Signal PreA1 is selected to select the first wordline WL1, the second character to select signal PreA2 to select the second wordline WL2, the 3rd character choosing Select signal PreA3 and select the 3rd wordline WL3.As for unselected quantum memory array, then it is still maintained at standby mode.

When selected to control the 0th quantum memory array through the 0th wordline WL0 time, only null character selects signal PreA0 is 1.8 volts, and remaining character selects signal (PreA1, PreA2, PreA3) to be 0 volt.Now, nmos pass transistor MA0 turns on.On the other hand, nmos pass transistor MA1, MA2, MA3 is turned off.

Refer to Fig. 4, it illustrates word line selection circuit and selects signal through null character, selects to provide word line driving voltage Give the schematic diagram of the 0th wordline.This sentences the transistor that the dotted line formula of painting is not turned on.

Holding, through the conducting of nmos pass transistor MA0, nmos pass transistor MB0 Yu MB1 will reversely input joint to the 0th wordline Point Swl0, it is provided that the pulling force declined towards ground voltage Gnd.

Assume initially that and the 0th quantum memory array is read.Now, operation voltage selecting circuit 23 carry The operation voltage Vpp=5V of confession, the wordline bias Vbias being provided circuit 25 to provide by bias are 1.8V.

At the same time, PMOS transistor MPU also because grid be electrically connected to wordline bias Vbias and be 1.8V, source electrode electricity It is connected to operate voltage Vpp and is the reason conducting of 5V.Therefore, PMOS transistor MPU will be to the 0th reverse input node of wordline Swl0, it is provided that the pulling force risen towards operation voltage Vpp (5V).

In other words, the voltage of the 0th reverse input node Swl0 of wordline, simultaneously by nmos pass transistor MB0, MB1 by under it It is pulled to ground voltage Gnd, and PMOS transistor MPU is pulled to the impact of 5V.

But, the exhaustion region of PMOS transistor MPU is relatively wide, and the thickness of passage is the most relatively thin.Therefore, PMOS transistor MPU Thered is provided is relatively weak toward pulling up the strength put forward.In comparison, nmos pass transistor MB0 Yu MB1 the drop-down power provided The strongest.Therefore, through the dividing potential drop between transistor, the voltage resulting from the 0th reverse input node Swl0 of wordline is about 100mV。

Owing to the voltage of the 0th reverse input node Swl0 of wordline is 100mV, related, the conducting of PMOS transistor P1, Nmos pass transistor N1 closes.Now, it is provided that be equivalent to operate the voltage of voltage Vpp to the word line driving voltage of the 0th wordline WL0 (5V)。

Secondly assume the 0th quantum memory array to be programmed operation.

If during the 0th quantum memory array data to be written into, representing operation voltage Vpp is 10V.Now, transistor MPU Grid voltage (be equivalent to wordline bias Vbias) be also required to and then operate voltage Vpp and change, control PMOS that could be suitable is brilliant The conducting state of body pipe MPU.

Otherwise, if wordline bias Vbias is when remaining within 1.8V, PMOS transistor MPU is probably because grid and leakage The voltage difference of pole is excessive and is damaged.If during it is here supposed that wordline to perform programming, corresponding wordline bias Vbias is 6.8V。

Same, the reverse input voltage of wordline will be pulled down to ground voltage by nmos pass transistor MB0, MB1 simultaneously Gnd, and PMOS transistor MPU is pulled to the impact of 10V.Therefore, through the dividing potential drop relation between transistor, the 0th word The voltage of reverse input node Swl0 of line is about 5.1V.

Owing to the voltage of the 0th reverse input node Swl0 of wordline is about 5.1V, related, the conducting of PMOS transistor P1, Nmos pass transistor N1 closes.Now, it is provided that be equivalent to operate the voltage of voltage Vpp to the word line driving voltage of the 0th wordline WL0 (10V)。

On the other hand, it is assumed that selection be other wordline (WL1～WL3) time, represent null character and select signal PreA0 Voltage be 0V.Now, nmos pass transistor MA0 closes because grid is 0V.

At the same time, PMOS transistor MPU still because grid wordline bias Vbias be 1.8V, source electrode be 5V And turn on.Now because nmos pass transistor MB0, MB1 are open circuit, only the conducting of PMOS transistor MPU can be anti-to the 0th wordline Impact is produced to the voltage of input node Swl0.Therefore, the voltage to the 0th reverse input node Swl0 of wordline is 5V.

Owing to being 5V to the voltage of the 0th reverse input node Swl0 of wordline, related, PMOS transistor P1 is closed, NMOS Transistor then turns on.Owing to nmos pass transistor P1 turns on, word line selection circuit 27 is supplied to the wordline of the 0th wordline WL0 and drives electricity Pressure is equivalent to ground voltage (Gnd=0V).

According to preceding description it is known that change except the level meeting basis operator scheme to be carried out of operation voltage Vpp Outside change, the level of wordline bias Vbias is also required to change according to operator scheme.So, word line selection circuit 27 could corresponding be produced Raw word line driving voltage is to selected wordline.

Explanation according to earlier figures 2, it is known that the wordline that bias provides circuit 25 to be provided biases Vbias, is in fact There is provided read operation bias WLBSRD to choose bias WLBS with high pressure according to overall situation bias circuit 21 and produce.

If it is to say, will be in response to the change of operator scheme, it is provided that when corresponding word line driving voltage is to wordline, also Need read operation bias WLBSRD and high pressure are chosen and bias the generation of WLBS and be controlled.

But, it is again to bias according to read operation that read operation bias WLBSRD and high pressure choose the generation of bias WLBS WLBSRD and high pressure choose the generation of bias WLBS.Therefore, overall situation bias circuit 21 operates voltage AVXRD to low level Operating voltage AVXHV with high level, it is provided that suitable control signal, the wordline bias Vbias that can provide suitable selects to wordline Select circuit 27.

Referring to Fig. 5, it is the schematic diagram of the storage compartments controller further illustrating prior art.

How this graphic left side explanation overall situation bias circuit 51 operates with low level according to high level operation voltage AVXHV Voltage AVXRD, produces read operation bias WLBSRD and chooses bias WLBS with high pressure.Although it is noted that the most only painting formula 0th storage compartments controller 50, but overall situation bias circuit 51 must provide for organizing read operation bias WLBSRD with high equally Pressure chooses bias WLBS to each storage compartments controller.

This graphic right side, then as a example by the 0th storage compartments controller 50, illustrates to operate how voltage selecting circuit 53 carries For operation voltage Vpp to word line selection circuit 57；And, bias provides how circuit 55 provides wordline bias Vbias to wordline Selection circuit 57.

First the overall bias circuit 51 on the left of explanatory diagram 5.

Overall situation bias circuit 51 comprises: bias generator 511, high pressure mode current path, low-voltage current path, drive Streaming current path and multiplexing's multiplexer 512.Wherein, bias generator 511 exports bias voltage signal NBIAS, by bias voltage signal NBIAS It is supplied to high pressure mode current path and low-voltage current path.

Multiplexing's multiplexer 512 biases WLBSHV according to the operation with high pressure that high pressure mode current path exports and drives electric current road Footpath and export high pressure choose bias WLBS.The read operation bias that low-voltage current path is produced by overall situation bias circuit 51 again WLBSRD, and the high pressure that multiplexing's multiplexer 512 exports is chosen bias WLBS output to bias offer circuit 55.

High pressure mode current path comprises PMOS transistor P1, P2, and, nmos pass transistor N1.Wherein, PMOS transistor The source electrode of P1 is electrically connected to high level operation voltage AVXHV；The drain electrode of PMOS transistor P1 is electric with the source electrode of PMOS transistor P2 Connect；The grid of PMOS transistor P2 and drain electrode, and the drain electrode electrical connection of nmos pass transistor N1；The source electrode of nmos pass transistor N1 It is electrically connected to ground voltage Gnd；And, the bias letter that the grid of nmos pass transistor N1 provides for receiving bias generator 511 Number NBIAS.Additionally, the grid of PMOS transistor P2 is used for exporting operation with high pressure bias WLBSHV to multiplexing's multiplexer 512.

Low-voltage current path comprises PMOS transistor P3, P4, and nmos pass transistor N2, N3.Wherein, PMOS crystal The source electrode of pipe P3 is electrically connected to low level operation voltage AVXRD；The grid of PMOS transistor P3, drain electrode, and nmos pass transistor The grid of N2, drain electrode are electrically connected；The source electrode of PMOS transistor P4 is electrically connected to the source electrode of nmos pass transistor N2；PMOS is brilliant The grid of body pipe P4 is electrically connected to drain electrode, and the drain electrode of nmos pass transistor N3；And, the grid electrical connection of nmos pass transistor N3 It is electrically connected to ground voltage Gnd in bias generator 511, source electrode.Additionally, PMOS transistor P4 is the most electric with nmos pass transistor N2 The node connected, being used for exporting read operation bias WLBSRD provides circuit 55 to bias.

Current path is driven to comprise PMOS transistor P5, and nmos pass transistor N4, N5.Wherein, nmos pass transistor N4 Drain electrode is electrically connected to low level operation voltage AVXRD；The grid of nmos pass transistor N4 is electrically connected to low-voltage current path The drain electrode of PMOS transistor P3；The drain electrode of nmos pass transistor N4 is electrically connected to the source electrode of PMOS transistor P5；PMOS transistor P5 Grid be electrically connected to the drain electrode of PMOS transistor P4 of low-voltage current path；The drain electrode of PMOS transistor P5 is electrically connected to The drain electrode of nmos pass transistor N5；And, the source electrode of nmos pass transistor N5 is electrically connected to ground voltage Gnd.Wherein, nmos pass transistor The node that N4 and PMOS transistor P5 are electrically connected to each other, for output to multiplexing's multiplexer 512.

As seen from Figure 5, the electric current Istd flowing through low-voltage current path can be operated voltage AVXRD by low level Level affected；And, the electric current Iop flowing through high pressure mode current path can be by the electricity of high level operation voltage AVXHV Flat affected.

It is said that in general, the change in voltage of low level operation voltage AVXRD is less, but high level operation voltage AVXHV Variation may be reduced to 3V because being in erasing mode, or because to be programmed and to be promoted to 10V.Related, stream Produce in metastable mode through the electric current Istd of low-voltage current path, and read operation bias WLBSRD can persistently carry Supply bias provides circuit 55.

But, because the electric current Istd flowing through low-voltage current path fairly small (such as: 1uA), thus again through driving The offer in streaming current path, produces the promotion electric current Idr of auxiliary further.On the other hand, high pressure mode current path is flowed through Electric current Iop relatively big (such as: 10uA), the voltage of the operation with high pressure bias WLBSHV of generation is the biggest.Therefore, high pressure is chosen partially Pressure WLBS is mainly affected by operation with high pressure bias WLBSHV.

Electricity is provided to bias when overall situation bias circuit 51 provides read operation bias WLBSRD and high pressure to choose bias WLBS During road 55, it is necessary to according to the operator scheme that the quantum memory array in storage compartments is selected, and then switch reality dynamically Output provides the voltage of circuit 55 to bias.

Then the 0th storage compartments controller 50 on the right side of explanatory diagram 5.

First, operation voltage selecting circuit 53 is one and operates for receiving low level operation voltage AVXRD and high level Multiplexing's multiplexer of voltage AVXHV.When the sub-memory array in storage compartments is to be read, operation voltage selecting circuit 53 is defeated Go out low level operation voltage AVXRD as operation voltage Vpp；Or, when group memory array is to be programmed, operation voltage choosing Select circuit AVXP output high level operation voltage AVXHV as operation voltage Vpp.

Secondly, bias provides circuit 55 to use multiplexing's multiplexer, bias provide the circuit BIASDEC wordline produced Bias Vbias can select the read operation bias WLBSRD that output voltage is relatively low according to the difference of operator scheme, or voltage be relatively High high pressure is chosen bias WLBS and is biased Vbias as wordline.

About the operation of word line selection circuit 57, refer to the explanation of Fig. 3, here is omitted.

During actual application, operation voltage Vpp must in response to the accessing operation of memory circuitry with velocity variations quickly, And wordline bias Vbias is also required to coordinate the speed of this kind of conversion.But, bias the wordline providing circuit 55 to be exported is inclined Pressure Vbias, in addition it is also necessary to first through overall situation bias circuit, high level operation voltage AVXHV, read operation bias WLBSRD are turned Change, after generation read operation bias WLBSRD, high pressure choose bias WLBS, further choosing through bias offer circuit 55 Draw.Therefore, the mode of this kind of generation wordline bias Vbias seems the most roundabout.

According to preceding description it is known that either by the operation operation voltage Vpp that produces of voltage selecting circuit 53, or The wordline providing circuit 55 to produce via overall situation bias circuit 51, bias biases Vbias, and the source that its signal produces is low electricity Flat operation voltage AVXRD operates voltage AVXHV with high level.

Conducting based on PMOS transistor MPU considers, further provide for operating voltage Vpp and wordline bias Vbias to When word line selection circuit 57 uses, between operation voltage Vpp and wordline bias Vbias, need to maintain certain voltage difference.But, word The generation process of line bias Vbias necessarily depends upon again the internal high pressure that produces of overall situation bias circuit 51 and chooses cutting of bias WLBS Change.

Therefore, low level operation voltage AVXRD, high level operation voltage AVXHV, operation voltage Vpp bias with wordline Between Vbias, define phenomenon all linked with one another.But, considering based on following two, wordline bias Vbias switch speed is necessary Promote.

A kind of consideration is different wordline need to be provided to bias in response to the change of the operator scheme corresponding to wordline.Reading During access to memory array, often read in the way of in proper order.Accordingly, it is possible to it is necessary to then after the 0th wordline WL0 has read Read WL1.Now, the 0th wordline WL0 will carry out cancellation and choose the action of (deselect).The action that this kind of cancellation is chosen, For word line selection circuit 57, being equivalent to the reverse input voltage of wordline needed within the shortest time (us grade), by 100mV rises to 5.1V.

According to preceding description it is known that the generation speed of the reverse input voltage of wordline, depend on operating voltage Vpp and word The pace of change of line bias Vbias.Assume that memory array comprises 64 storage compartments (SEC0～SEC63), the most relatively In requisition for providing 64 storage compartments controllers.It follows that when the storage compartments that flash array is comprised is the most, entirely The consideration that office bias circuit GWLBS controls for different sections wordline bias Vbias needed for different time points is the most.Cause This, the load (loading) forming overall situation bias circuit 51 also becomes much larger.

In other words, when storage compartments quantity increases, overall situation bias circuit 51 must also be taken into account at all of storage compartments In, the pass between low level operation voltage AVXRD, high level operation voltage AVXHV, operation voltage Vpp and wordline bias Vbias System.Therefore, overall situation bias circuit 51 produces the speed of wordline bias Vbias, may not catch up with the switching speed of operation voltage Vpp Degree.

Then, under the guiding of high memory span, multiple field stores (multilevel cell, abbreviation in another kind of consideration For MLC) technology is more and more universal.For the application of MLC, even if the operator scheme of same wordline does not change, wordline is selected Selecting circuit still needs to provide different word line driving voltage to wordline.Can be shorter consequently, it is possible to word line driving voltage is required Change is produced in time (ns grade).

Such as: in the case of being similarly in read operation, it is provided that must be very to the word line driving voltage of the 0th wordline WL0 In the short time, in 20ns, first it is changing into 5V by 3V, the most further in 15ns, is risen to 7V by 5V.It is to say, Operation voltage Vpp needs in a short period of time, rising (stepping) several times.

In sum, along with needing the storage compartments quantity controlled to increase, and word line driving voltage must be able to quickly cut Getting demand in return, the overall bias circuit of prior art must use the most complicated logic control (logic control).This Outward, for the application of MLC, word line driving voltage must be able to quickly switch (fast switching).Now, through the overall situation partially Volt circuit 51 produces the way of wordline bias Vbias indirectly, just cannot meet (catch up) this kind of requirement.

Summary of the invention

An aspect of of the present present invention provides circuit for one bias, is electrically connected between an operation voltage and a ground voltage, should Bias provides circuit to be to export a wordline bias through a bias output node, and this bias provides circuit to comprise: one first opens Closing, be electrically connected between this operation voltage and this bias output node, it is to maintain conducting state；One first current path, is electrically connected Being connected between this bias output node and this ground voltage, comprise: a second switch, it is to lead according to one first Dc bias Logical；And, one second current path, it is electrically connected between this bias output node and this ground voltage, comprises: one the 3rd switch, Being electrically connected to this ground voltage, it is to turn on according to one second Dc bias；And, one the 4th switch, be electrically connected to this Between three switches and this bias output node, it is to select the control of signal to turn on according to a storage compartments, and wherein this wordline is inclined The level of pressure be level according to this operation voltage with the conducting state of this second current path and change.

Another aspect of the invention is a kind of storage compartments controller, comprise: an operation voltage selecting circuit, it is to provide One operation voltage；One bias provides circuit, is electrically connected between this operation voltage selecting circuit and a ground voltage, and it is according to being somebody's turn to do Operating voltage and export a wordline bias in a bias output node, this bias provides circuit to comprise: one first switch, and it is electric It is connected between this operation voltage and this bias output node, and this first switch keeping conducting state；One first current path, electricity Being connected between this bias output node and this ground voltage, it is to turn on according to one first Dc bias；And, one second electricity Flow path, is electrically connected between this bias output node and this ground voltage, and it is the control selecting signal according to a storage compartments And turn on, wherein this wordline bias is to change according to this operation voltage and the conducting state of this second current path；One wordline Selection circuit, is electrically connected to this operation voltage selecting circuit and partially provides circuit with this, and it is according to this wordline bias and this operation Voltage and export a word line driving voltage；And, one first wordline, it is electrically connected to this word line selection circuit, it is to receive this word Line driving voltage.

Another aspect of the invention is a kind of memory circuitry, comprises: an overall situation bias circuit, it is straight that it is to provide one first Stream bias and one second Dc bias；One first storage compartments, comprises multiple quantum memory array；And,

One first storage compartments controller, is electrically connected to this overall situation bias circuit and this first storage compartments, comprises: a behaviour Making voltage selecting circuit, it is to provide an operation voltage；One bias provides circuit, is electrically connected to this overall situation bias circuit, this behaviour Make, between voltage selecting circuit and a ground voltage, to comprise: one first switch, be electrically connected to this operation voltage and this bias output joint Between point, it is to maintain conducting state；One first current path, is electrically connected between this bias output node and this ground voltage, its It is to turn on according to this first Dc bias；And, one second current path, it is electrically connected to this bias output node and this ground connection Between voltage, it is to select the control of signal to turn on according to a storage compartments, and wherein this wordline bias is according to this operation voltage Change with the conducting state of this second current path；One word line selection circuit, be electrically connected to this operation voltage selecting circuit with This provides circuit partially, and it is to export a word line driving voltage according to this wordline bias and this operation voltage；And, one first word Line, is electrically connected to this word line selection circuit and one first quantum memory array in such quantum memory array, and it is according to being somebody's turn to do Word line driving voltage and drive this first quantum memory array.

More preferably understand in order to the above-mentioned and other aspect of the present invention is had, special embodiment below, and coordinate institute's accompanying drawing Formula, is described in detail below:

Accompanying drawing explanation

Fig. 1, it illustrates the basic framework schematic diagram of memory circuitry.

Fig. 2, it is the memory circuitry of prior art, through overall situation bias circuit and the 0th storage compartments controller, deposits Take the schematic diagram of the 0th storage compartments.

Fig. 3, it illustrates the schematic diagram of word line selection circuit of prior art.

Fig. 4, it illustrates word line selection circuit and selects signal through null character, selects to provide word line driving voltage to give the 0th The schematic diagram of wordline.

Fig. 5, it is the schematic diagram of the storage compartments controller further illustrating prior art.

Fig. 6, its be the present invention storage compartments control circuit collocation the overall situation bias circuit schematic diagram.

Fig. 7 A, it is the bias offer circuit of the present invention, produces the schematic diagram of wordline bias through the first current path.

Fig. 7 B, it is the bias offer circuit of the present invention, produces the schematic diagram of wordline bias through the second current path.

Fig. 8, it is to the present invention is directed to an other storage compartments to provide wordline bias, is in standby in storage compartments controller The schematic diagram of pattern.

Fig. 9, it is the storage compartments controller of the present invention, for individual other storage compartments, it is provided that wordline bias is read The schematic diagram of extract operation pattern.

Figure 10, it is the storage compartments controller of the present invention, for individual other storage compartments, it is provided that wordline bias is compiled The schematic diagram of journey operator scheme.

[main element symbol description]

Overall situation bias circuit 13,21,51,61

Mode setting circuit 11 high-pressure generator 12

Address buffering circuit 14 array decoding circuit 15

Row decoding circuit 16 memory array 17

0th storage compartments controller 20,50,60a

Operation voltage selecting circuit 23,53,63a, 63b

Bias provide circuit 25,55,65a, 65b

Word line selection circuit 27,57,67a, 67b

Wordline 28,68a, 68b

0th storage compartments 29,69a

0th storage compartments selects signal PreB0

First storage compartments selects signal PreB1

Bias generator 511 multiplexing's multiplexer 512

63rd storage compartments 69b

63rd storage compartments controller 60b

Read operation bias WLBSRD

High pressure chooses bias WLBS

Operation with high pressure bias WLBSHV

Word line selection signal PreA0, PreA1, PreA2, PreA3

Low level operation voltage AVXRD

High level operation voltage AVXHV

2nd 55 storage compartments 69b

First Dc bias NBIAS1

Second Dc bias NBAIAS2

Bias output node Sbias

Wordline bias Vbias

Storage compartments selects signal SECTOR

Wordline enable signal WLEN

Detailed description of the invention

According to preceding description it is known that the quantity for storage compartments increases the switch of operator scheme derived, with And the demand such as repeatedly voltage switching during MLC application, multiple storage compartments with overall situation bias circuit GWLBS, it is provided that each The practice of the word line driving voltage that wordline in storage compartments is corresponding seems the most complicated and is difficult to realize.

To this end, the present invention proposes the memory circuitry of a kind of complexity that can significantly simplify overall situation bias circuit.Letter Yan Zhi, this kind of way is to provide circuit through the bias in storage compartments controller, provides exclusiveization to individual other storage compartments The handoff functionality of word line driving voltage.When using this kind of way, overall situation bias circuit need not switch dynamically and should export reading Extract operation bias WLBSRD or high pressure choose bias WLBS.

Refer to Fig. 6, its be the present invention storage compartments control circuit collocation the overall situation bias circuit schematic diagram.At this figure In formula, overall situation bias circuit 61 is for producing the first Dc bias NBIAS1 and the second Dc bias NBIAS2 signal to each Storage compartments controller.Wherein, each storage compartments controller is respectively used to control a corresponding storage compartments.

Such as: it is assumed herein that memory array comprises 64 storage compartments altogether.The 0th storage compartments controller in graphic 60a is for controlling the 0th storage compartments 69a, the 63rd storage compartments controller 60b for controlling the 63rd storage compartments 69b。

Inside each storage compartments controller, each self-contained operation voltage selecting circuit 63a, 63b；Bias provides circuit 65a、65b；Word line selection circuit 67a, 67b, and a plurality of wordline 68a, 68b.

In figure 6, due to the first Dc bias of overall situation bias circuit 61 output to bias offer circuit 65a, 65b The voltage of NBIAS1 and the second Dc bias NBIAS2 all remains unchanged.Compare with Fig. 5 it is apparent that the overall situation bias circuit The 61 required control logics used can significantly simplify.

Additionally, the low level provided by high voltage generator operates voltage AVXRD operates voltage AVXHV with high level, and Need not be sent to overall situation bias circuit 61, and be provided only to operate voltage selecting circuit 63a, 63b.

According to the conception of the present invention, operation voltage selecting circuit 63a, 63b are in receiving low level operation voltage AVXRD with high After level operation voltage AVXHV, output function voltage Vpp to bias provide circuit 65a, 65b and word line selection circuit 67a, 67b。

Bias through the present invention provides circuit 65a, 65b wordline bias Vbias produced, equally can be in response to operation voltage The change of Vpp and change.Therefore, for word line selection circuit 67, its control signal and voltage received still with prior art Identical.Related, word line selection circuit 67a, 67b still can maintain and wordline is chosen control mode.About word line selection circuit Selection between 67a, 67b and wordline 68a, 68b, and the quantum memory battle array that wordline 68a, 68b are corresponding with in storage compartments The control mode of row, the most no longer describes in detail.

On the other hand, bias provides the first Dc bias that circuit 65a, 65b can be provided according to overall situation bias circuit 61 NBIAS1 (such as: 0.4V) and the second Dc bias NBIAS2 (such as: 0.8V), and operation voltage selecting circuit 63a, 63b The operation voltage Vpp provided, produces wordline bias Vbias to word line selection circuit 67a, 67b.

There is provided how circuit 65a, 65b produce wordline bias Vbias's in response to the change of operation voltage Vpp about bias The practice, please referring further to Fig. 7 A, the explanation of Fig. 7 B.

Referring to Fig. 7 A, it is the bias offer circuit of the present invention, produces showing of wordline bias through the first current path It is intended to.

The bias of the present invention provides circuit 65a to comprise: be electrically connected to bias output node Sbias and ground voltage Gnd it Between provide the first current path, the second current path, and be electrically connected to operate voltage Vpp with bias output node Sbias Between first switch M1.

In bias provides circuit 65a, the first switch M1 is PMOS transistor, and its body is electrically connected to source electrode.First opens The source electrode of the PMOS transistor closed is electrically connected to operate voltage Vpp, grid is electrically connected to bias output node with drain electrode Sbias.No matter the operator scheme residing for storage compartments why, and the first switch M1 all maintains conducting state.

Additionally, the first current path comprises the second switch M2 turned on according to the first Dc bias NBIAS1.Second electricity Flow path comprises: the second Dc bias NBIAS2 and turn on the 3rd switch M3；And, select signal according to storage compartments The control of SECTOR and the 4th switch M4 that turns on.

In the first current path, second switch M2 is nmos pass transistor, and its drain electrode is electrically connected to bias output node Sbias, grid are electrically connected to the first Dc bias NBIAS1, source electrode is electrically connected to ground voltage Gnd.First Dc bias The more general transistor threshold voltage of NBIAS1 (threshold voltage, usually 0.7V) is lower slightly.Such as: about 0.3V or 0.4V。

The bias of relative weak is only had so that represent second and open owing to representing the grid of the nmos pass transistor of second switch M2 Close the electric current relatively small (such as: 10nA) of the nmos pass transistor conducting of M2.Owing to the first Dc bias NBIAS1 persistently provides Reason, this less electric current also can maintain.If storage compartments is in standby mode, bias offer circuit 65a will be such as figure Shown in 7A, produce wordline bias Vbias through the first current path.

On the other hand, if storage compartments is in reading or the operator scheme such as able to programme, will as shown in Figure 7 B, through second Current path and produce wordline bias Vbias.Need to be noted that, no matter whether storage compartments is in operator scheme, the first electric current Path all maintains conducting because of the first Dc bias NBIAS1 of second switch M2 grid.

Referring to Fig. 7 B, it is the bias offer circuit of the present invention, produces showing of wordline bias through the second current path It is intended to.

In the second current path, the 3rd switch M3 and the 4th switch M4 is nmos pass transistor.Represent the 3rd switch M3 Nmos pass transistor, source electrode is electrically connected to ground voltage Gnd, grid is electrically connected to the second Dc bias NBIAS2.On the other hand, Representing the nmos pass transistor of the 4th switch M4, its source electrode is electrically connected to the 3rd switch M3, grid receives storage compartments and selects signal SECTOR, drain electrode are electrically connected to bias output node Sbias.

When storage compartments is in operator scheme, the first current path and the second current path will simultaneously turn on.Only, now Because the electric current that the second current path is turned on is relatively big, wordline bias Vbias is affected the biggest by the second current path.

Compare the first current path and the second current path further it is found that no matter which kind of operation storage compartments is in Pattern, the first current path all can be stablized and lasting one small electric current of generation.Therefore, the first current path can be considered one The current path that individual normality exists.

On the other hand, when storage compartments selects signal SECTOR not produce, be equivalent to storage compartments and be in standby mode. Now, the second current path will present open circuit.Owing to the second current path can select signal SECTOR to determine according to storage compartments Whether determine to turn on, therefore, the second current path can be considered a current path just dynamically existed under non-standby pattern.

If during according to preceding description it is known that storage compartments is in standby mode and accesses, bias provides electricity Road BIASDEC only provides the first current path that electric current is less.Otherwise, when storage compartments to access, bias provides electricity Road BIASDEC provides the second current path and the first of the electric current less (such as: 10nA) of electric current relatively big (such as: 30uA) simultaneously Current path.

As it was previously stated, storage compartments controller comprises: operation voltage selecting circuit, the overall situation bias circuit for, bias carry For circuit, character selection circuit, a plurality of wordline.Then, utilize Fig. 8, Fig. 9, be described separately the storage compartments controller of the present invention, When using aforesaid bias to provide circuit, its internal circuit situation when standby mode and operator scheme respectively.

Referring to Fig. 8, it is to the present invention is directed to an other storage compartments to provide wordline bias, at storage compartments controller Schematic diagram in standby mode.Formula of herein painting the 0th wordline WL0 therein and the first wordline WL1.

In some applications, when each storage compartments in memory array is standby mode, array decoding circuit The corresponding storage compartments selected still may rest on the result of last output.Now, what this was finally used deposits Storage area paragraph controller, it would still be possible to select signal SECTOR to make the second current path conducting because receiving storage compartments.

Therefore, the second current path also can comprise: the 5th switch turned on according to wordline enable signal (WLEN).Its In, the 5th switch M5 uses nmos pass transistor, drain electrode to be electrically connected to bias output node Sbias, source electrode is electrically connected to the 4th and opens Close, grid turns on according to the control of wordline enable signal WLEN.

Wherein, the purposes of wordline enable signal (WLEN) is, when all standby modes of memory array, it is ensured that will not Any storage compartments is had to be chosen.Certainly, if the storage compartments being supplied to segment controller has selected signal SECTOR signal When so the operation of each storage compartments of consideration all will not produce misoperation with standby mode, then the 5th switch M5 is not necessarily required to.

For operation voltage selecting circuit 63, the operation voltage Vpp now exported is 5V.For overall situation bias circuit 61, maintain output the first Dc bias NBIAS1 and the second Dc bias NBIAS2.

For bias provides circuit 65, when storage compartments is in standby mode (standby mode), although each All wordline (WL) of individual storage compartments are all automatically switched off (turn off).Therefore, wordline enable signal is 0V (WLEN= 0).Now, the second current path does not turns on.Therefore, bias provides circuit 65 to only transmit M1 and the first current path conducting Vpp With ground voltage Gnd.Now, the wordline bias produced at bias output node is 1V.

For character selection circuit 67b, because not having wordline to be selected, nmos pass transistor MB0 with MB1 is all without leading Logical.And, by the nmos pass transistor M7 of the 0th word line selection signal PreA0 control, controlled by the first word line selection signal PreA1 Nmos pass transistor M21 also all without conducting.

PMOS transistor M1 biases Vbias=1V according to the wordline of grid and turns on, and now, the 0th wordline reversely inputs joint The voltage of some Swl0 is equal with operation voltage Vpp because of the conducting of PMOS transistor M1.For PMOS transistor M8 and NMOS For the reverser that transistor M9 is formed, the voltage of the 0th reverse input node Swl0 of wordline of input is 5V, thus defeated Go out the word line driving voltage of 0V to the 0th wordline WL0.

Same, PMOS transistor M20 biases Vbias=1V according to the wordline of grid and turns on, and now, the first wordline is anti- Equal with operation voltage Vpp because of the conducting of PMOS transistor M20 to the voltage of input node Swl1.For PMOS transistor For the reverser that M22 and nmos pass transistor M23 is formed, the voltage of the first reverse input node Swl1 of wordline of input is 5V, thus the word line driving voltage of output 0V gives the first wordline WL1.

Therefore, when storage compartments is in standby mode, word line selection circuit 67a will export 0V to storage compartments controller Interior all wordline.Related, the storage compartments corresponding with storage compartments controller just will not be accessed.That is, through stable The first current path produced, produces the word line driving voltage of 0V to wordline WL all corresponding to standby mode.

Referring to Fig. 9, it is the storage compartments controller of the present invention, for individual other storage compartments, it is provided that wordline biases It is read the schematic diagram of pattern.

For operation voltage selecting circuit 63, the operation voltage Vpp now exported operates voltage AVXRD phase with low level Deng (Vpp=AVXRD=5V).Overall situation bias circuit 61 still maintains output the first Dc bias NBIAS1 and the second Dc bias NBIAS2。

For bias provides circuit 65, when storage compartments is in read mode, simultaneously through the first electric current road Footpath and the second current path conducting Vpp and ground voltage Gnd.Now, the wordline produced at bias output node biases Vbias about For 1.8V.

For character selection circuit 67b, nmos pass transistor MB0 with MB1 is both turned on, and the 0th section chooses the electricity of Ssec0 Pressure is 0V.It is assumed herein that storage address to be read is positioned at the quantum memory array corresponding with the first wordline WL1, therefore, First word line selection signal PreA1 is by turn on NMOS transistor M21.

Therefore, between operation voltage Vpp and ground voltage Gnd, by formation through PMOS transistor M20, NMOS crystal The electric current of pipe M21, MB0, MB1 conducting.Now, the voltage of the first reverse input node Swl1 of wordline is about 0.1V.

For the reverser that PMOS transistor M22 and nmos pass transistor M23 are formed, the first wordline of input is anti- It is about 0.1V to the voltage of input node Swl1, thus turns on PMOS transistor M22, and the wordline that output level is 5V drives electricity Pressure is to the first wordline WL1.

Referring to Figure 10, it is the storage compartments controller of the present invention, for individual other storage compartments, it is provided that wordline biases It is programmed the schematic diagram of operator scheme.

If the quantum memory array in storage compartments is to be programmed, the conducting state of each transistor of Figure 10 and figure 9 is similar, and the voltage level that difference is on node can produce change.

Now, by the operation voltage Vpp of operation voltage selecting circuit 63a output, be equivalent to high level operation voltage AVXHV, i.e. Vpp=AVXHV=10V.Same, the first current path and the second current path are both turned on.Related, pass through The dividing potential drop of transistor so that the wordline bias Vbias=6.8V on bias output node.

In word line selection circuit 67a, by operation voltage Vpp via PMOS transistor M10, nmos pass transistor M11, MB0, MB1 is conducted to ground voltage Gnd, thus making the voltage of the first reverse input node Swl1 of wordline is 5.1V.Therefore, the first wordline The word line driving voltage that WL1 is received is 10V.

According to preceding description it is known that work as storage compartments to be changed into Fig. 8 by any one operator scheme of Fig. 9, Figure 10 Standby mode time because first current path maintain constant conduction state, wordline bias Vbias can rapidly by script The voltage provided through the second current path produces through the first current path for being transformed into.Therefore, if to cancel When choosing, the bias of the present invention provides the circuit can the conversion of quick compounding practice pattern.

Furthermore, for the application of MLC, the bias of the present invention provides circuit to be directly to produce through operation voltage Vpp Wordline bias Vbias.Therefore, when operation voltage Vpp produces the moment of change, and the generation that wordline bias Vbias can synchronize becomes Change, needn't could produce the wordline bias Vbias corresponding with operation voltage Vpp through other control circuit.

In sum, providing circuit through the bias in storage compartments controller, the present invention can be in response to each storage compartments Operation, it is provided that with operation voltage synchronous change wordline bias.This kind of way not only can simplify overall situation bias circuit GWLBS's Logical design, moreover it is possible to coordinate wordline bias Vbias to need the demand being switched fast.

According to aforesaid embodiment it can also be seen that either standby mode and operator scheme switching, choose and cancel Level change when choosing, or the demand of word line driving voltage need to be switched fast in response to the application of MLC, the storage of the present invention Segment controller all quickly can provide suitable word line driving voltage to corresponding storage compartments with quantum memory array.

Subsidiary one is mentioned that, only manages different types of memorizer, the controlling party of the voltage conversion when providing wordline to drive Formula is incomplete same with NOR gate flash memory, but may all there is similar problem.That is, voltage conversion and control is the most complicated, and The phenomenon that conversion speed is the slowest.Therefore, although aforesaid embodiment is as a example by NOR gate flash memory, but the application of the present invention is not As limit.

In sum, although the present invention is disclosed above with all embodiment, and so it is not limited to the present invention.This Bright art has usually intellectual, without departing from the spirit and scope of the present invention, when making various changes With retouching.Therefore, protection scope of the present invention is when depending on being as the criterion that appended claims scope is defined.

Claims (15)

1. bias provides a circuit, is electrically connected between an operation voltage (Vpp) and a ground voltage, and this bias offer circuit is Exporting wordline bias (Vbias) through bias output node (Sbias), this bias provides circuit to comprise:

One first switch, is electrically connected between this operation voltage and this bias output node, and it is to maintain conducting state；

One first current path (weak path), is electrically connected between this bias output node and this ground voltage, comprises:

One second switch, it is to turn on according to one first Dc bias (W_NBIAS)；And,

One second current path (strong path), is electrically connected between this bias output node and this ground voltage, comprises:

One the 3rd switch, is electrically connected to this ground voltage, and it is to turn on according to one second Dc bias；And,

One the 4th switch, is electrically connected between the 3rd switch and this bias output node, and it is to select letter according to a storage compartments The control of number (SECTOR) and turn on, wherein the level of this wordline bias is the level according to this operation voltage and this second electric current The conducting state in path and change.

Bias the most according to claim 1 provides circuit, wherein equal with this second current path when this first current path During conducting, flow through the electric current of this first current path less than the electric current flowing through this second current path.

Bias the most according to claim 1 provides circuit, wherein this first Dc bias and this second Dc bias be by One overall situation bias circuit (GWLBS) provides, and this first Dc bias is less than this second Dc bias.

Bias the most according to claim 1 provides circuit, and wherein this second current path further includes:

One the 5th switch, is electrically connected to this bias output node and the 4th switch room, and it is according to a wordline enable signal (WLEN) turn on.

5. a storage compartments controller, comprises:

One operation voltage selecting circuit, it is to provide an operation voltage；

One bias provides circuit, is electrically connected between this operation voltage selecting circuit and a ground voltage, and it is according to this operation electricity Pressing and export a wordline bias in a bias output node, this bias provides circuit to comprise:

One first switch, it is electrically connected between this operation voltage and this bias output node, and the conducting of this first switch keeping State；

One first current path, is electrically connected between this bias output node and this ground voltage, and it is inclined according to one first direct current Press and turn on；And,

One second current path, is electrically connected between this bias output node and this ground voltage, and it is according to a storage compartments choosing Selecting the control of signal and turn on, wherein this wordline bias is according to this operation voltage and the conducting state of this second current path Change；

One word line selection circuit, is electrically connected to this operation voltage selecting circuit and provides circuit with this bias, and it is according to this wordline Bias with this operation voltage and export a word line driving voltage；And,

One first wordline, is electrically connected to this word line selection circuit, and it is to receive this word line driving voltage.

Storage compartments controller the most according to claim 5, wherein this first current path comprises:

One second switch, turns on according to one first Dc bias.

Storage compartments controller the most according to claim 5, wherein this second current path comprises:

One the 3rd switch, is electrically connected to this ground voltage, and it is to turn on according to one second Dc bias；And,

One the 4th switch, is electrically connected between the 3rd switch and this bias output node, and it is to select letter according to a storage compartments Number control and turn on.

Storage compartments controller the most according to claim 5, wherein when this first current path and this second current path When being both turned on, flow through the electric current of this first current path less than the electric current flowing through this second current path.

Storage compartments controller the most according to claim 7, wherein this first Dc bias with this second Dc bias is Thered is provided by an overall situation bias circuit, and this first Dc bias is less than this second Dc bias.

Storage compartments controller the most according to claim 7, wherein this second current path further includes:

One the 5th switch, is electrically connected to this bias output node and the 4th switch room, and it is according to a wordline enable signal Conducting.

11. storage compartments controllers according to claim 5, wherein this operation voltage selecting circuit is multiplexing's multiplexing Device, and this operation voltage is low level operation voltage (AVXRD) and one of high level operation voltage (AVXHV).

12. 1 kinds of memory circuitries, comprise:

One overall situation bias circuit, it is to provide one first Dc bias and one second Dc bias；

One first storage compartments, comprises multiple quantum memory array；And,

One first storage compartments controller, is electrically connected to this overall situation bias circuit and this first storage compartments, comprises:

One operation voltage selecting circuit, it is to provide an operation voltage；

One bias provides circuit, is electrically connected to this overall situation bias circuit, between this operation voltage selecting circuit and a ground voltage, wraps Contain:

One first switch, is electrically connected between this operation voltage and a bias output node, and it is to maintain conducting state；

One first current path, is electrically connected between this bias output node and this ground voltage, and it is inclined according to this first direct current Press and turn on；And,

One second current path, is electrically connected between this bias output node and this ground voltage, and it is according to a storage compartments choosing Selecting the control of signal and turn on, wherein a wordline bias is according to this operation voltage and the conducting state of this second current path Change；

One word line selection circuit, is electrically connected to this operation voltage selecting circuit and provides circuit with this bias, and it is according to this wordline Bias with this operation voltage and export a word line driving voltage；And,

One first wordline, is electrically connected to this word line selection circuit and one first quantum memory battle array in the plurality of quantum memory array Row, it is to drive this first quantum memory array according to this word line driving voltage.

13. memory circuitries according to claim 12, wherein this first current path comprises:

One second switch, turns on according to this first Dc bias.

14. memory circuitries according to claim 12, wherein this second current path comprises:

One the 3rd switch, is electrically connected to this ground voltage, turns on according to this second Dc bias；And,

One the 4th switch, is electrically connected between the 3rd switch and this bias output node, and it is to select letter according to a storage compartments Number control and turn on.

15. memory circuitries according to claim 14, wherein this second current path further includes:

One the 5th switch, is electrically connected to this bias output node and the 4th switch room, and it is according to a wordline enable signal Conducting.