CN101807422B - Readout amplifying circuit - Google Patents
Readout amplifying circuit Download PDFInfo
- Publication number
- CN101807422B CN101807422B CN 201010133575 CN201010133575A CN101807422B CN 101807422 B CN101807422 B CN 101807422B CN 201010133575 CN201010133575 CN 201010133575 CN 201010133575 A CN201010133575 A CN 201010133575A CN 101807422 B CN101807422 B CN 101807422B
- Authority
- CN
- China
- Prior art keywords
- transistor
- circuit
- reading
- amplifying circuit
- node
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Amplifiers (AREA)
Abstract
The invention relates to a readout amplifying circuit which comprises a differential amplifying circuit and a bandgap current compensation circuit, wherein the bandgap current compensation circuit is provided with an input node and an output node; an input current source of the bandgap current compensation circuit is a bandgap reference current source IBGR; electric current IBGR is fed back to the output node through the bandgap current compensation circuit; readout data of a selected storage unit are compensated by the bandgap reference current IBGR provided by the bandgap current compensation circuit, then fed back to a readout node through the differential amplifying circuit and compared with reference current Iref, and a corresponding output signal is output according to a comparison result. The readout amplifying circuit effectively compensates the bandgap current caused by a long-channel effect at the same time that the limitation to the use range of a power voltage for ensuring the normal working of the readout amplifying circuit is overcome, ensures that the readout data of the selected storage unit are more accurate and further guarantees the reliability of the readout result at the same time of effectively improving the readout speed of the readout amplifying circuit.
Description
Technical field
The present invention relates to the storer read structure, be specifically related to a kind of sensor amplifier structure, belong to the memory technology field.
Background technology
Many electronic circuits are all used sensor amplifier.Electrical differential reading-out amplifying receives the two-way input signal, and generation is the output signal of feature to close between input signal.Along with reducing of ordinary electronic device working power voltage, existing read amplifying circuit and begin to run into bottleneck.
Fig. 1 is the existing amplifying circuit synoptic diagram of reading.As shown in Figure 1, Ym is selected storage unit, and it has stray capacitance Cb1.At this moment, V falls in the storage unit Ym word line pressure of being expert at
WLBe high voltage, by the gating circuit conducting that MOS transistor Y1, Y2, Y3 form, namely gating signal YA, YB, YC are high-voltage signal, and the storage signal on the storage unit Ym is read.Transistor Ms and amplifier I
1Form voltage control circuit, the source of transistor Ms is connected with the source of transistor M1, transistor M1 and transistor M2 form a differential amplifier circuit, the electric current of the storage unit of flowing through Ym is as the input current of this differential amplifier circuit, and show as the output current that flows out via transistor M2, compare via B point and reference current Iref, according to comparative result, export corresponding output signal DOUT.In this sensing circuit, the voltage V that differential amplifier circuit input end A is ordered
A=V
DD-Vth (m1)-Vdssat, wherein, V
DDBe supply voltage, V th (m1) is the threshold voltage of transistor M1, and Vdssat is for leaking saturation voltage.Hence one can see that, and the A point voltage is storage unit Ym bit-line voltage of living in, and this voltage is subject to the restriction of transistor M1 threshold voltage.Because the bit line of storer will guarantee certain read current, therefore bit-line voltage must reach specific magnitude of voltage, want so that read the amplifying circuit normal operation, then the A point voltage can not be lower than this specific voltage value, as the above analysis, the A point voltage is subject to the restriction of transistor M1 threshold voltage, along with reducing of supply voltage, thisly reads the usable range that amplification circuit structure has seriously limited supply voltage.
In order to overcome this problem, proposed to adopt the threshold voltage method of clamping down on to replace the High Gain Feedback method to control the thinking of bit-line voltage in the prior art, thereby reduce the restriction of transistor threshold voltage pairs of bit line voltage, Fig. 2 is modified and reads amplification circuit structure figure.As shown in Figure 2, transistor M1 and transistor M2 form differential amplifier circuit 201, and its input current source is the bandgap reference electric current I
BGR, the voltage transfer that A is ordered in the effect by differential amplification electric current 201 is to the B point, and the B point voltage is storage unit bit-line voltage of living in, and the electric current of the transistor M2 that flows through is the bandgap reference electric current I
BGR, transistor M3 plays the bit-line voltage control action, the electric current I of the transistor M3 that flows through
3=I
Cell-I
BGR, wherein, I
CellBe the output current of storage unit Ym, I
BGRBe the bandgap reference electric current, namely under the effect of differential amplifier circuit 201, the band gap electric current of storage unit Ym is by filtering, and reading flow is through the current value of storage unit Ym more accurately.Transistor M4 is the converter transistor, the storage unit Ym reading current of the M3 that flows through is converted to the input current of the differential amplifier circuit 202 of transistor M5 and transistor M6 composition, and export via transistor M6, the C point of flowing through, Iref compares with reference current, according to comparative result, export corresponding output signal DOUT.Read in the amplification circuit structure at this, because the voltage of transistor M2 can be less than threshold voltage, transistor threshold voltage obtains certain alleviation to the restriction of supply voltage, yet, also there is following shortcoming in this structure: (1) has introduced more Self-bias Current, so that the storage unit reading current increases, thereby affect the reliability of reading result; (2) because transistor M2 must operate at the saturation region, the voltage that B is ordered (being bit line voltage) still is subject to the restriction of the leakage saturation voltage Vdssat of transistor M2, along with further reducing of conventional semiconductor devices operating voltage, the required supply voltage of this circuit normal operation is restricted; (3) adopting the threshold voltage method of clamping down on to replace the High Gain Feedback method to control bit-line voltage might cause that precharge overcharges phenomenon, reduce the memory cell data reading speed; (4) owing to channel-length modulation, the bandgap reference electric current I
BGRCan not be shown as accurately by transistor M3 the image current of transistor M4, thereby affect the reliability of reading result.
Summary of the invention
The technical problem to be solved in the present invention is, a kind of amplifying circuit of reading is provided, overcome to have now and read amplifying circuit to the restriction of supply voltage usable range, so that the operating voltage of storage unit is able to further reduction, and further improve the accuracy of reading out data, improve the circuit reading speed, guaranteeing the reliability of reading result.
For solving the problems of the technologies described above, the amplifying circuit of reading provided by the invention comprises differential amplifier circuit 100 and band gap current compensation circuit 200, wherein band gap current compensation circuit 200 has input node A and output node B, and the input current source of band gap current compensation circuit 200 is bandgap reference current source I
BGR, electric current I
BGRFeed back to its output node B through band gap current compensation circuit 200, the reading out data of selected storage unit is after 200 compensation of band gap current compensation circuit, feed back to via differential amplifier circuit 100 and to read node C, Iref compares with reference current, judges Output rusults.
Provided by the invention reading in the amplifying circuit, differential amplifier circuit 100 comprise the first transistor M301 and transistor seconds M302, and the output terminal of differential amplifier circuit 100 with read node C and be connected; Band gap current compensation circuit 200 then comprises: (1) image current source circuit 200a, comprise the 3rd transistor M303 and the 4th transistor M304, and this image current source circuit 200a also has the first input node D and the second input node E; (2) first operational amplifier I
301, its in-phase input end and inverting input connect respectively the first input node D and the second input node E of image current source circuit 200a; (3) the 5th transistor M305 are connected between the output node B of the second input node E and band gap current compensation circuit 200 grid of the 5th transistor M305 and the first operational amplifier I
301Output terminal link to each other; (4) the 6th transistor M306 are connected between the input node A of the first input node D and band gap current compensation circuit 200, and the grid of the grid of the 6th transistor M306 and the 3rd transistor M303 and the 4th transistor M304 links together.
The amplifying circuit of reading provided by the invention also comprises voltage control circuit 300, and this voltage control circuit 300 comprises the 7th transistor M307 and the second operational amplifier I
302, wherein, the 7th transistor M307 is connected to band gap current compensation circuit 200 output node B, and the second operational amplifier I
302Defeated in-phase input end and inverting input connect respectively source electrode and the reference voltage source Vref of described the 7th transistor M307, its output terminal connects the grid of the 7th transistor M307.
The amplifying circuit of reading provided by the invention also comprises the 8th transistor M308 and the 9th transistor M309, and wherein, the 8th transistor M308 is connected to the output node B place of band gap current compensation circuit 200, and it is used to play bit-line voltage control; The 9th transistor M309 is connected to the input end of differential amplifier circuit 100, is the converter transistor, and its grid and the 8th transistor M308 grid link together.
Provided by the invention reading in the amplifying circuit, the first transistor M301～the 6th transistor M306 is the PMOS transistor, and the 7th transistor M307, the 8th transistor M308 and the 9th transistor M309 then are nmos pass transistor.
Provided by the invention reading in the amplifying circuit, the first operational amplifier I
301So that the 3rd transistor M303, the 4th transistor M304 and the 5th transistor M305 all are operated in linear zone, and the pressure drop on the 4th transistor M304 and the 5th transistor M305 is all less than 200mV.
Technique effect of the present invention is, by introducing band gap current compensation circuit 200, and introduces a high gain operational amplifier I between the two input Nodes of image current source circuit 200a and the 5th transistor M305
301, so that the first input node D of image current source circuit 200a and the second input node E have identical voltage, and the 3rd transistor M303 has identical electric current with the 4th transistor M304, thereby with the bandgap reference electric current I
BGRFeed back to accurately the output node B of band gap current compensation circuit, improved the accuracy to selected storage unit reading out data.Again because at high gain operational amplifier I
301Effect under, the 3rd transistor M303, the 4th transistor M304 and the 5th transistor M305 all are operated in linear zone, pressure drop on the 4th transistor M304 and the 5th transistor M305 is very little, usually less than 200mV, this is just so that the voltage of band gap current compensation circuit 200 output node B and supply voltage are very approaching, has overcome will guarantee to read amplifying circuit and work to the restriction of supply voltage usable range.In addition, because the first operational amplifier I
301The high-gain effect, the output impedance of the 4th transistor M304 and the 5th transistor M305 is less, has prevented the generation of channel-length modulation, thus Effective Raise is read the reading speed of amplifying circuit, further guarantees the reliability of its reading result.
Description of drawings
Fig. 1 is the existing amplifying circuit synoptic diagram of reading;
Fig. 2 improves synoptic diagram for the existing amplifying circuit of reading;
Fig. 3 is the amplifying circuit synoptic diagram of reading provided by the invention.
Concrete body embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with accompanying drawing.
Fig. 3 is the amplifying circuit synoptic diagram of reading provided by the invention.
As shown in Figure 3, reading amplifying circuit comprises:
(1) differential amplifier circuit 100, comprise the first transistor M301 and transistor seconds M302, its output terminal with read node C and be connected;
(2) the band gap current compensation circuit 200, have input node A and output node B, and it is input as bandgap reference current source I
BGR, electric current I
BGRFeed back to its output node B through band gap current compensation circuit 200, this band gap current compensation circuit 200 comprises:
(a) image current source circuit 200a comprises the 3rd transistor M303 and the 4th transistor M304, and this image current source circuit 200a also has the first input node D and the second input node E;
(b) the first operational amplifier I
301, its in-phase input end and inverting input connect respectively the first input node D and the second input node E of image current source circuit 200a;
(c) the 5th transistor M305 is connected between the output node B of the second input node E and band gap current compensation circuit 200 grid of the 5th transistor M305 and the first operational amplifier I
301Output terminal link to each other;
(d) the 6th transistor M306 is connected between the input node A of the first input node D and band gap current compensation circuit 200, and the grid of the grid of the 6th transistor M306 and the 3rd transistor M303 and the 4th transistor M304 links together.
Wherein, the first transistor M301, transistor seconds M302, the 3rd transistor M303, the 4th transistor M304, the 5th transistor M305, the 6th transistor M306 are the PMOS transistor.
Further, reading amplifying circuit also comprises and is connected to reference current source Iref and the voltage control circuit 300 of reading node C.This voltage control circuit 300 comprises the 7th transistor M307 and the second operational amplifier I
302, wherein, the 7th transistor M307 is connected to band gap current compensation circuit 200 output node B, and the second operational amplifier I
302In-phase input end and inverting input connect respectively source electrode and the reference voltage source Vref of described the 7th transistor M307, its output terminal connects the grid of the 7th transistor M307.
Further, this is read amplifying circuit and also comprises the 8th transistor M308 and the 9th transistor M309, and wherein, the 8th transistor M308 is connected to the output node B place of band gap current compensation circuit 200, and it is used to play bit-line voltage control; The 9th transistor M309 is connected to the input end of differential amplifier circuit 100, is the converter transistor, and its grid and the 8th transistor M308 grid link together.
Wherein, the 7th transistor M307, the 8th transistor M308 and the 9th transistor M309 are nmos pass transistor.
In this embodiment, the first operational amplifier I
301Selection, guarantee that the 3rd transistor M303, the 4th transistor M304 and the 5th transistor M305 all are operated in linear zone, at this moment, the pressure drop on the 4th transistor M304 and the 5th transistor M305 is all less than 200mV.
Further, in this embodiment, the first transistor M301 is identical with the grid voltage of transistor seconds M302, and the 3rd transistor M303 is identical with the grid voltage of the 4th transistor M304, its grid voltage V
GScope is 0V～V
DD-Vt, wherein, V
DDBe supply voltage, Vt is transistor threshold voltage.
In this embodiment, as shown in Figure 3, Ym is selected storage unit, and it has stray capacitance Cb1.V falls in the word line pressure that storage unit Ym is expert at
WLDuring for high voltage, selected storage unit Ym is in conducting state, meanwhile, the gating circuit conducting that is formed by MOS transistor Y1, Y2, Y3, be that gating signal YA, YB, YC are high-voltage signal, storage unit Ym is chosen, and the storage signal on the storage unit Ym is read.
This embodiment provides when reading the amplifying circuit normal operation, the image current source circuit 200a that the 3rd transistor M303 and the 4th transistor M304 form, and its input current source is the bandgap reference electric current I
BGR, and pass through the effect of image current source circuit 200a with voltage transfer to the second input node E of the first input node D, and at this moment, because the first operational amplifier I
301Effect, the magnitude of voltage of the magnitude of voltage of the first input node D and the second input node E equates, and the current value of the 3rd transistor M303 that flows through also equates with the current value of the 4th transistor M304 that flows through, is I
BGR, effectively overcome the impact that channel-length modulation brings.
When reading the storage signal on the selected storage unit Ym, electric current on the selected storage unit Ym flow to the output node B of band gap current compensation circuit 200 via the 7th transistor M307, at this moment, via the storage signal direction of current of voltage control circuit 300 outputs and the current opposite in direction of band gap current compensation circuit 200 outputs, the output current I of band gap current compensation circuit 200
BGREffective compensation in the output storage signal because the band gap electric current that causes of channel-length modulation, electric current after compensation feeds back to the input end of differential amplifier circuit 100 through the 8th transistor M308 and conversioning transistor (the 9th transistor) M309, and show as the electric current of the transistor seconds M302 that flows through, this electric current is directly flowed through and is read node C, that is: the current signal of selected storage unit Ym is behind the band gap current compensation, shows as the flow through electric current of transistor seconds M302 of differential amplification electric current 100.Reading in the amplifying circuit that this embodiment provides, reference current source Iref provides a reference current Iref, the flow through electric current of transistor seconds M302 and this reference current Iref compares reading node C, and according to comparative result, exports corresponding output signal DOUT.
As optimum implementation, the first operational amplifier I
301Be high gain operational amplifier, its in-phase input end connects the first input node D of image current source circuit 200a, and its inverting input connects the second input node E of image current source circuit 200a.
As another embodiment, the first operational amplifier I
301Be common operational amplifier, its in-phase input end connects the second input node E of image current source circuit 200a, and its inverting input connects the first input node D of image current source circuit 200a.
What this embodiment provided reads in the amplifying circuit, because the 3rd transistor M303, the 4th transistor M304 and the 5th transistor M305 all are operated in linear zone, when reading the amplifying circuit normal operation, pressure drop on the 4th transistor M304 and the 5th transistor M305 is all very little, usually less than 200mV, therefore, voltage and the supply voltage of band gap current compensation circuit 200 output node B are very approaching, have successfully overcome will guarantee to read the amplifying circuit normal operation to the restriction of supply voltage usable range.
In addition, because the first operational amplifier I
301The high-gain effect, the output impedance of the 4th transistor M304 and the 5th transistor M305 is less, has prevented the generation of channel-length modulation, thus Effective Raise is read the reading speed of amplifying circuit, further guarantees the reliability of its reading result.
In situation without departing from the spirit and scope of the present invention, can also consist of many very embodiment of big difference that have.Should be appreciated that except as defined by the appended claims, the invention is not restricted at the specific embodiment described in the instructions.
Claims (9)
1. read amplifying circuit for one kind, for the data of reading selected storage unit (Ym), it is characterized in that, the described amplifying circuit of reading comprises differential amplifier circuit (100) and band gap current compensation circuit (200), described band gap current compensation circuit (200) has input node (A) and output node (B), described band gap current compensation circuit (200) be input as bandgap reference current source (I
BGR), and feeding back to output node (B) through described band gap current compensation circuit (200), reading out data feeds back to via described differential amplifier circuit (100) and to read node (C) after described band gap current compensation circuit (200) compensation;
Wherein, described band gap current compensation circuit (200) comprising:
(1) image current source circuit (200a) comprises the 3rd transistor (M303) and the 4th transistor (M304), and described image current source circuit (200a) has the first input node (D) and the second input node (E);
(2) first operational amplifier (I
301), its in-phase input end and inverting input connect respectively the first input node (D) and second of described image current source circuit and input node (E);
(3) the 5th transistors (M305) are connected between described the second input node (E) and the described output node (B), and the grid of described the 5th transistor (M305) connects described the first operational amplifier (I
301) output terminal;
(4) the 6th transistors (M306), be connected between the input node (A) of described the first input node (D) and described band gap current compensation circuit (200), the grid of the grid of described the 6th transistor (M306) and described the 3rd transistor (M303) and described the 4th transistor (M304) links together.
2. the amplifying circuit of reading according to claim 1, it is characterized in that, described differential amplifier circuit (100) comprises the first transistor (M301) and transistor seconds (M302), and the output terminal of described differential amplifier circuit (100) with read node (C) and be connected.
3. the amplifying circuit of reading according to claim 2, it is characterized in that described the first transistor (M301), transistor seconds (M302), the 3rd transistor (M303), the 4th transistor (M304), the 5th transistor (M305) and the 6th transistor (M306) are the PMOS transistor.
4. the amplifying circuit of reading according to claim 3 is characterized in that, the described amplifying circuit of reading also comprises voltage control circuit (300), and described voltage control circuit (300) comprises the 7th transistor (M307) and the second operational amplifier (I
302), wherein, described the 7th transistor (M307) is connected to described band gap current compensation circuit (200) output node (B), and described the second operational amplifier (I
302) in-phase input end and inverting input connect respectively source electrode and the reference voltage source (Vref) of described the 7th transistor (M307), its output terminal connects the grid of described the 7th transistor (M307).
5. the amplifying circuit of reading according to claim 4, it is characterized in that, the described amplifying circuit of reading also comprises the 8th transistor (M308) and the 9th transistor (M309), wherein, the 8th transistor (M308) is connected to the output node (B) of described band gap current compensation circuit (200) and locates, and it is used to play bit-line voltage control; The 9th transistor (M309) is connected to the input end of described differential amplifier circuit (100), is the converter transistor, and its grid and described the 8th transistor (M308) grid link together.
6. according to claim 4 or the 5 described amplifying circuits of reading, it is characterized in that described the 7th transistor (M307), the 8th transistor (M308) and the 9th transistor (M3090) are nmos pass transistor.
7. the amplifying circuit of reading according to claim 1 is characterized in that, the described amplifying circuit of reading also comprises and is connected to the described reference current source (Iref) of reading node (C).
8. the amplifying circuit of reading according to claim 2 is characterized in that, described the first operational amplifier (I
301) so that described the 3rd transistor (M303), the 4th transistor (M304) and the 5th transistor (M305) all are operated in linear zone.
9. the amplifying circuit of reading according to claim 8 is characterized in that, the pressure drop of described the 4th transistor (M304) and described the 5th transistor (M305) is all less than 200mV.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010133575 CN101807422B (en) | 2010-03-26 | 2010-03-26 | Readout amplifying circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010133575 CN101807422B (en) | 2010-03-26 | 2010-03-26 | Readout amplifying circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101807422A CN101807422A (en) | 2010-08-18 |
| CN101807422B true CN101807422B (en) | 2013-03-20 |
Family
ID=42609177
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201010133575 Active CN101807422B (en) | 2010-03-26 | 2010-03-26 | Readout amplifying circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101807422B (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101937702B (en) * | 2010-09-10 | 2015-11-25 | 上海华虹宏力半导体制造有限公司 | With the sensor amplifier that bit line capacitance detects |
| US8362807B2 (en) * | 2010-10-13 | 2013-01-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Offset compensation for sense amplifiers |
| CN103106916B (en) * | 2012-12-21 | 2016-09-28 | 上海华虹宏力半导体制造有限公司 | Memorizer and reading circuit, a kind of comparison circuit |
| CN103117080B (en) * | 2013-02-01 | 2017-08-08 | 上海华虹宏力半导体制造有限公司 | Reading circuit |
| US8929168B2 (en) * | 2013-02-28 | 2015-01-06 | Freescale Semiconductor, Inc. | Sense amplifier voltage regulator |
| CN107958688B (en) * | 2016-10-17 | 2020-04-17 | 旺宏电子股份有限公司 | Sensing circuit and method for nonvolatile memory device |
| CN113946178B (en) * | 2020-07-15 | 2023-04-28 | 上海江波龙微电子技术有限公司 | Memory and bias voltage generating circuit and method thereof |
| CN116301423B (en) * | 2023-02-28 | 2024-02-09 | 湖南锐阳电子科技有限公司 | Touch array reading circuit and method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0479098A2 (en) * | 1990-10-01 | 1992-04-08 | Nec Corporation | Random access memory device having high-speed sense amplifier circuit implemented by bipolar transistors |
| US6392943B2 (en) * | 1999-11-18 | 2002-05-21 | Stmicroelectronics S.A. | Reading device and method for integrated circuit memory |
| CN101027730A (en) * | 2004-07-30 | 2007-08-29 | 斯班逊有限公司 | Semiconductor device and method for generating sense signal |
| CN101630532A (en) * | 2008-07-17 | 2010-01-20 | 上海华虹Nec电子有限公司 | Sensitive amplifier used for electrically erasable read only memory and realization method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100223849B1 (en) * | 1996-10-24 | 1999-10-15 | 구본준 | Semiconductor memory device |
-
2010
- 2010-03-26 CN CN 201010133575 patent/CN101807422B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0479098A2 (en) * | 1990-10-01 | 1992-04-08 | Nec Corporation | Random access memory device having high-speed sense amplifier circuit implemented by bipolar transistors |
| US6392943B2 (en) * | 1999-11-18 | 2002-05-21 | Stmicroelectronics S.A. | Reading device and method for integrated circuit memory |
| CN101027730A (en) * | 2004-07-30 | 2007-08-29 | 斯班逊有限公司 | Semiconductor device and method for generating sense signal |
| CN101630532A (en) * | 2008-07-17 | 2010-01-20 | 上海华虹Nec电子有限公司 | Sensitive amplifier used for electrically erasable read only memory and realization method thereof |
Non-Patent Citations (1)
| Title |
|---|
| JP特开平10-134574A 1998.05.22 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101807422A (en) | 2010-08-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101807422B (en) | Readout amplifying circuit | |
| CN101630532B (en) | Sensitive amplifier used for electrically erasable read only memory and realization method thereof | |
| CN102681582A (en) | Linear voltage stabilizing circuit with low voltage difference | |
| CN105486912A (en) | High precision rapid over-current detection circuit for low dropout regulator | |
| CN107092295B (en) | A kind of high Slew Rate fast transient response LDO circuit | |
| US7642815B2 (en) | Sense amplifier | |
| CN108153360A (en) | A kind of bandgap voltage reference | |
| CN104216455B (en) | For the low-power consumption reference voltage source circuit of 4G communication chip | |
| CN106328552A (en) | Ultra-low voltage temperature threshold detector | |
| CN108717158A (en) | A kind of detection of negative pressure circuit suitable for Power MOSFET | |
| CN102495654A (en) | Low-dropout regulator and integrated circuit system | |
| CN101800068B (en) | Readout amplifying circuit | |
| CN106067822A (en) | A kind of cmos latch comparator of high-speed, high precision | |
| CN103873044A (en) | Low voltage difference signal LVDS composition circuit | |
| CN203491978U (en) | Output stage circuit, class AB amplifier and electronic device | |
| US9099167B2 (en) | Current detector allowing a large supply voltage range | |
| CN101853037A (en) | Energy-saving voltage stabilizer | |
| CN105242735B (en) | A kind of asymmetric mu balanced circuit for NAND FLASH | |
| CN108255223A (en) | Ldo circuit | |
| CN108762361A (en) | Low pressure difference linear voltage regulator | |
| CN109391234A (en) | Differential amplifier circuit | |
| CN204517765U (en) | The rail-to-rail operational amplifier of the wide amplitude of oscillation | |
| US9437258B2 (en) | Data readout circuit of a storage device for read-out operation for preventing erroneous writing into a data storage element and reading out of the data correctly | |
| CN101840724B (en) | Signal receiver and related voltage compensation method thereof | |
| CN103390420A (en) | Sense amplifier circuit and semiconductor device using the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140506 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20140506 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |