CN101802989A - Method and apparatus for forming arbitrary structures for integrated circuit devices - Google Patents

Method and apparatus for forming arbitrary structures for integrated circuit devices Download PDF

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Publication number
CN101802989A
CN101802989A CN200880106804A CN200880106804A CN101802989A CN 101802989 A CN101802989 A CN 101802989A CN 200880106804 A CN200880106804 A CN 200880106804A CN 200880106804 A CN200880106804 A CN 200880106804A CN 101802989 A CN101802989 A CN 101802989A
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mechanical structure
electric
electric device
interconnection
design document
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克里斯托弗·怀兰德
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Koninklijke Philips NV
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Koninklijke Philips Electronics NV
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
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    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
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    • H05K3/1241—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by ink-jet printing or drawing by dispensing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4664—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P80/00—Climate change mitigation technologies for sector-wide applications
    • Y02P80/30—Reducing waste in manufacturing processes; Calculations of released waste quantities

Abstract

A method of implementing arbitrary structures to provide electrical interconnection and mechanical fixturing for integrated circuits is provided. According to exemplary embodiments of the invention said arbitrary structures are manufactured using three dimensional manufacturing processes employing only additive steps for all materials within the arbitrary structure. Accordingly the arbitrary structure is provided in a single step incorporating mechanical, electrical, and thermal elements as required by the design incorporating simultaneously dielectric and metallic materials. The arbitrary structures may be manufactured directly in association with the integrated circuits or separately for subsequent assembly to the integrated circuits. Arbitrary structures ranging from a fraction of to all of the structural and electrical elements required for packaging the integrated circuit(s) being provided by the arbitrary structures according to the design boundary established.

Description

Be formed for the method and apparatus of the arbitrary structures of integrated circuit (IC)-components
Technical field
The present invention relates to integrated circuit, more specifically, relate to the arbitrary structures that is formed for forming interface and encapsulated integrated circuit with integrated circuit.
Background technology
Half a century only after beginning development, integrated circuit (IC) just becomes ubiquitous.Computer, cell phone and other digital devices are parts indispensable in the structure in modern society.That is to say that modern computing, communication, manufacturing and transfer system comprise the Internet, all depend on the existence of IC.Along with the complexity of integrated circuit, the consumerization of electronic device and the function of consumption electronic product improve constantly, the consumption of the whole world of IC constantly increases fast.Since calendar year 2001 Mo, annual IC delivering amount from 68,500,000,000 of calendar year 2001 risen to 2006 1,374 hundred million, increased more than 100%.Correspondingly, come from 17,000,000,000 dollars of the worldwide monthly income average out to that IC sells during this period of time 2004 to 2006.
At present, in IC, from be operated in DC to being operated in 40GHz and Geng Gao, from discrete transistor to (for example, comprising about fifty-five million transistor at interior microprocessor
Figure GPA00001052750300011
Pentium 4), and from the tube core of square millimeter to the integrated prototype of wafer-scale (as, the array microprocessor of Intel, comprise 80 microprocessors, the processing that each microprocessor can independently be handled and share), such IC adopts multiple semi-conducting material, comprises silicon, GaAs, indium phosphide, SiGe.The terminal stage that the integrated circuit encapsulating face is made to the semiconductor device of the IC of such different range (wherein, at wafer-level process and manipulation IC).
The step that is called for short " encapsulation " in the IC industry comprises one group of operation, and this group is operated and comprised die attachment or tube core placement, IC joint, as, by line bonding, upside-down mounting solder projection, TAB etc., seal, make marks, lead trimming and lead forming.According to the needs of packaged type, carry out the whole sequence formed by these steps or predetermined subclass at each discrete IC.Thereby encapsulation typically accounts for about 80% to 90% of IC cost.Therefore, the influence of encapsulation is substantial in discrete IC, and along with the trend that encapsulates (MCP) and stacked chip-scale encapsulation (S-CSP) recently about the multicore sheet, the influence of encapsulation has increased, wherein in described MCP and S-CSP, a plurality of IC are united be packaged together,, or be perpendicular to one another and pile up as separated tube core in the single layer.Along with reducing cost, reduce area occupied (footprint), reducing to encapsulate the demand of section, this encapsulation format (as, MCP and S-CSP) become more and more general, and continue aspect this external function and the performance (not only on the speed but also on power efficiency) to improve simultaneously.
Summary of the invention
In in the past about 30 years, nearly 20 kinds of different encapsulation format have reached " industrial standard " state, every kind of encapsulation format is supported in the specific balance of above-mentioned improvement aspect, and changes for every kind of encapsulation format provides the many kinds at aspects such as size, number of pins.Among these encapsulation format many, electrical interconnection is a kind of specific format, as, the line bonding in the dip (DIP), this may limit the performance of IC.Therefore, apparently, advantageously provide a kind of and provide the method for electrical interconnection with any encapsulation format in the different encapsulation format, wherein electrical interconnection adapts to the demand of IC.In addition advantageously, the electrical interconnection that provides the electrical interconnection that allows arbitrary format to make this electrical interconnection adapt to the particular demands of IC and be not limited in described " industrial standard " encapsulation, adopt usually.
Also will be advantageously, reduce the interior required independent process of " single " encapsulation step of IC.Advantageously be, or to provide electrical interconnection and heat management as single step with the synthetic single step of electrical interconnection and seal group.In essence, advantageously, provide a kind of method, this method at random provides electrical interconnection, heat interconnection, encapsulation etc. in the mode of reinforcement cost-performance tradeoff rather than to select the mode of " optimum in the worst condition " from " industrial standard ".Advantageously, thus the many-sided this integrated of IC encapsulation reduced the complicated operation degree, improved reproducibility, improved performance and reduced cost.Also will be advantageously, the use interpolation manufacture process rather than the manufacture process that reduces realize the manufacturing operation to any encapsulating structure, so that by only using the raw material of aequum necessary for forming part, make raw-material consumption minimize, cut the waste, reduce environmental impact, reduce the electric power consumption of finished parts and spend lower cost.
According to the present invention, a kind of method for packing is provided, comprise: provide to relate to the design document (design file) that is used for forming with at least one electric device the mechanical structure at interface, described design document comprises at least two in the following project: the electricity input of described mechanical structure and electric output coordinate (coordinate), electricity input and electricity exported the mechanical attributes and the list of materials of the power path information in the path that interconnects, the mechanical attributes of semiconductor element, described mechanical structure.This method also comprises: utilize three-dimensional manufacturing system to carry out described design document; Described three-dimensional manufacturing system produces described mechanical structure by in a plurality of sequential system manufacturing operations at least one as single monolithic unit, and each in described a plurality of sequential system manufacturing operations comprises that interpolation is from any material described list of materials, that thickness is littler than the thickness of any element in the described mechanical structure.
According to another embodiment of the present invention, a kind of method for packing is provided, this method comprises: provide to relate to the design document that is used for forming with at least one electric device the mechanical structure at interface, described design document comprises at least two in the following project: the electricity input and the electric output coordinate of described mechanical structure, the power path information in the path that interconnects is exported in electricity input and electricity, the mechanical attributes of semiconductor element, the mechanical attributes of described mechanical structure, and list of materials, described design document relates to the three-dimensional manufacturing system of control, described three-dimensional manufacturing system can produce described mechanical structure as single monolithic unit by in a plurality of sequential system manufacturing operations at least one, and described sequential system manufacturing operation comprises that interpolation is from described list of materials, any material that thickness is littler than the thickness of any element in the described mechanical structure.
According to another embodiment of the present invention, a kind of method for packing is provided, this method comprises at least one electric device that a plurality of electric devices are provided and mechanical structure is provided, described mechanical structure is used for forming the interface with the predetermined portions at least of at least one electric device of described a plurality of electric devices, described mechanical structure is to adopt three-dimensional manufacturing system to produce described mechanical structure by in a plurality of sequential system manufacturing operations at least one as single monolithic unit to make, and each in described a plurality of sequential system manufacturing operations comprises adds the thickness any material littler than the thickness of any element in the described mechanical structure.This method also comprises: with at least one the electric device interconnection in described mechanical structure and the described a plurality of electric device.
According to another embodiment of the present invention, provide a kind of method for packing, this method comprises: at least one electric device in a plurality of electric devices is provided; And the mechanical structure that is associated with described at least one electric device in described a plurality of electric devices of generation, described mechanical structure is used for forming the interface with the predetermined portions at least of at least one electric device of described a plurality of electric devices, described mechanical structure is to adopt three-dimensional manufacturing system to produce described mechanical structure by in a plurality of sequential system manufacturing operations at least one as single monolithic unit to make, and each in described a plurality of sequential system manufacturing operations comprises adds the minimum thickness little material of thickness than any element in the described mechanical structure.
Description of drawings
Now example embodiment of the present invention will be described in conjunction with the accompanying drawings, in the accompanying drawing:
The evolution that the industrial standard IC that Fig. 1 was shown over 30 years encapsulates.
Fig. 2 shows the prior art pin configuration from 2116 pin package of auspicious Sa technology (Renesas Technology).
Fig. 3 A shows the art methods of the electrical interconnection from tube core to encapsulation of LTCC substrate with the form of cross-sectional view.
Fig. 3 B shows the technological process of the LTCC substrate of shop drawings 3A.
Fig. 4 shows the art methods of the electrical interconnection of stacked IC structure in the stacked chip-scale encapsulation (S-CSP).
Fig. 5 shows the art methods according to the three-dimensional electrical interconnection of Kunishi.
Fig. 6 A shows to provide between two elements and scatters the example embodiment of the present invention that is electrically connected.
Fig. 6 B shows the electrical interconnection that the example structure according to Fig. 6 A provides.
Fig. 7 shows the cross section of the example embodiment of the present invention that any electrical interconnection is provided.
Fig. 8 shows the cross section of the illustrated embodiments of the invention that any encapsulation that comprises electrical interconnection, mechanical structure and heat management is provided.
Fig. 9 A shows the plane cross section that the example embodiment of the present invention of heat management and electrical interconnection is provided for IC.
Fig. 9 B shows the first cross section Y-Y of the example embodiment of Fig. 9 A.
Fig. 9 C shows the first cross section Y-Y of the example embodiment of Fig. 9 A.
Figure 10 shows the example embodiment of the present invention that any encapsulation is provided, wherein shown in arbitrarily many sides of encapsulation have electrical interconnection.
Embodiment
Have in the last thirty years near 20 kinds of different encapsulation format to have reached " industrial standard " state shown in encapsulation target Figure 100 as passing through among Fig. 1." industrial standard " encapsulation scheme at the eighties in 130,20th century seventies in 20th century nineties 150 in 140,20th century and the 00's of 21 century 160 has been shown in encapsulation target Figure 100 respectively.In 130 to 160 per ten years, each " industrial standard " is to design for following 2 balance according to it: satisfy for the I/O quantity and the high performance needs (by representing with the degree of closeness of X-axis 110) that increase, and satisfy for the needs (by with the degree of closeness of Y-axis 120 represent) of the cost that reduces with the area occupied that reduces.
Like this, in seventies 130 in 20th century, show single " industrial standard " dip DIP 131.To eighties 140 in 20th century, encapsulation has been evolved into following " industrial standard " is provided: pin grid array (PGA) 141, four side pin flat packaging (QFP) 142, leaded chip carrier (LCC) 143 and little outline packages (SOP) 144.These are respectively away from pin number/performance and moved on to lower cost and area occupied.In nineties 150 in 20th century, these " industrial standards " are able to evolution, because technological improvement provides the improved reproducibility of narrow electric structure, and provide soldered technology so that ball grid array (BGA) 151, thin four side pin flat packaging (TQFP) 152, little spacing four side pin flat packaging (FQFP) 153, the little outline packages of scaled-down version (SSOP) 154 and thin little outline packages (TSOP) 155 to be provided.
To the 00's of 21 century 160, these trend continue, and provide little spacing ball grid array (FPGA) 163, leadless chip carrier (LLCC) 166 and four sides not to have flat (QFN) 167 of pin.Yet, the new demand that is driven by the further consumerization of many electronic equipments has also driven new encapsulation " industrial standard ", these electronic equipments are such as being laptop computer, PDA(Personal Digital Assistant), cell phone, portable media player etc., these electronic equipments combine with the multiple international standard of radio infrastructure etc., this requires circuit element is realized twice, three times even four times (as, cellular four frequency range global roamings) in identical device.These new encapsulation " industrial standard " are multicore sheet encapsulation (MCP) 161, system in package (SIP) 162, wafer-level package (CSP) 164, stacked chip-scale encapsulation (S-CSP) 165 and wafer-class encapsulation (WLP) 166.
The pin configuration 200 of the 2116 contact FPGA 163 that Rui Sa technology company by Japan shown in Figure 2 provides shows the example of the convergent-divergent of the encapsulation that since the eighties 140 in 20th century from PGA 141 its evolution provide by FPGA 163 in the 00's 160 21 century up to now.Define this pin configuration 200 by row 210 and row 220, wherein, row 210 is at a distance of industrial standard spacing d y240, row 220 are similarly at a distance of industrial standard interval d x230.In the pin configuration 200 of the FPGA 162 of 2116 contacts (auspicious Sa technical components PRBG2116FA-A), d x230 and d yThe 240th, 1.0mm.Like this, provide 2116 pin requirements, 46 row 210 (being labeled as) and 46 row (being labeled as from 1 to 46) from A to BF.d x230 and d yOther industrial standard spacing of 240 is 0.50mm, 0.65mm, 1.27mm and 2.54mm.Although d typically x230 and d y240 equate in the encapsulation such as FPGA 163, yet such was the case with for situation, and as under the situation of DIP 131, for example row 210 can be d x=7.62mm, row 220 d y=2.54mm is referring to 14 pin DIP.
Typically, the encapsulation such as FPGA 163 need be from IC to pin is connected electrically in a plurality of interconnection layers wirings, and these interconnection layers are to use the electric pathway structure to come perpendicular interconnection.The sandwich construction 350 of Fig. 3 A shows the example cross-section of the prior art substrate that forms FPGA 163 mounting bases.In Fig. 3 B below show the technological process of the sandwich construction 350 that typically uses LTCC (LTCC) and make.
As directed, sandwich construction 350 comprises 6 LTCC layers 321 to 325, each LTCC layer utilization metallization is patterned in various degree, for example respectively referring to upper surface metallide 331 and 332 on the LTCC layer 321 and 322, metallide 333 on the upper surface of LTCC layer 326, and the bottom surface metallide 334 on the lower surface of LTCC layer 326.Determine these metallide patterns about circuit design, wherein, sandwich construction 350 has been designed to meet the particular electrical circuit of assembling with this sandwich construction 350, perhaps alternatively determine from the aspect of standard packaging geometry, grid array position and inner bonding welding pad (for the sake of clarity all these does not illustrate in the drawings), for the sake of clarity, all do not illustrate.
Can patterning passive electrical structure in sandwich construction 350, comprise capacitor 363, three-dimensional resistance device 362, embedded-resistor 361 and pass one or more layers electric pathway 370 in the LTCC layer 321 to 326.Supplementary features can comprise cavity and heat passage 380, and described cavity can be a cavity 385 for example, are used for holding the photodetector that is coupled with the optical fiber 390 that inserts the cavity of LTCC layer 323.With the electrical interconnection of sandwich construction 350 can comprise solder reflow, the flip-chip die 351 of mounted on surface resistor 341 solder projection, epoxy attached wafer 353 engage 352 and the solder reflow of flip-chip carrier 354.In addition, can adopt installation elements in the both sides of sandwich construction, as 355 illustrations of solder projection tube core of below, yet this is uncommon for encapsulating structure, and more common for LTCC circuit board and carrier structure.
With reference to figure 3B, show and form LTCC the structure technological process 300 and the schematic flow 350 of (as, the sandwich construction 350 that above Fig. 3 A provides).First step 301 comprises blank (blanking), and wherein, plate forms a plurality of LTCC layers 311 (for the sake of clarity not shown) " to give birth to band (green tape) " by cutting.When mentioning " give birth to band ", term " lifes " refers to the characteristic of not firing of film of the organic material of the inorganic material that comprises about 85-90% and about 10-15%." band " refers to and makes used continuous material plate similarly.Typically, described inorganic material is silicon dioxide, aluminium oxide, aluminium nitride, but comprises borosilicate according to the needs of LTCC.Next in step 302, form electric pathway and heat passage in each plate (for example, the LTCC plate 312 to 315).In step 303 these electric pathways are carried out plating to fill them then.Each LTCC plate 312 to 315 all has the pattern of electric pathway and heat passage, provides necessary wiring to need such pattern between each conductive layer, wherein in final sandwich construction 350 between each phase adjacency pair between each conductive layer of qualification.
Next in step 304, print each LTCC plate 312 to 315 with suitable electric structure.Next in step 305, to these LTCC plates 312 to 315 orientations and pile up the lamination of not firing to form 316.In step 306, the lamination of not firing 315 is carried out lamination, and typically under about 900 ℃ of temperature, LTCC plate 312 to 315 is carried out common burning, thereby remove " giving birth to band " interior organic substance, and they are fused together to form common burning lamination 317.In this,, carry out additional printing,, thereby produce completed lamination 318 on the outer surface that burns lamination 317 altogether for example so that thick film and film passive electrical structure (as, resistor) to be provided in step 307.All remaining operations are that completed lamination 318 is carried out electrical testing in step 309, and cut into final size, thereby LTCC substrate 319 is provided.Common this cutting is that a plurality of LTCC substrates of making simultaneously 319 are separated with single plate.
Typically, each LTCC plate 312 to 315 has a standard thickness scope, as by
Figure GPA00001052750300071
The Green Tape that provides TM, wherein, the thickness of LTCC plate 312 to 315 is 51 μ m, 114 μ m, 165 μ m and 254 μ m.Therefore, obviously, any electric trace of being realized forms by the electric trace series on every layer, and vertical passage is passed each layer interconnection electric trace of " giving birth to band ".Like this, all electrical wirings and structure must meet the vertical quantification of this " path " and horizontal trace.Therefore, provide the general type of the LTCC substrate 319 of sandwich construction 350 to provide the bonding welding pad of single series or the LTCC substrate of projection series.Yet except the design limit forced by the numbers of plies in the sandwich construction 350 and wiring restriction, evolution package requirements such as stacked chip-scale encapsulation (S-CSP) 165, Fig. 4 also shows exemplary chip lamination 400.
As directed, LTCC substrate 470 has been assembled first semiconductor element 410, first dielectric spacer 450, second semiconductor element 430, second dielectric spacer 400, the 3rd semiconductor element 450 and the 4th semiconductor element 460.Upper surface at LTCC substrate 470 is signal bonding welding pad 486, power supply bonding welding pad 482 and ground pad 484.First bonding welding pad 492 is from 486 beginnings of signal bonding welding pad and 410 interconnection of first semiconductor element, and the second line bonding 494 and second semiconductor element 430 interconnect, and three- way bonding 496 and 450 interconnection of the 3rd semiconductor element.As directed, power supply bonding welding pad 482 and 460 interconnection of the 4th semiconductor element, ground pad 484 also is like this.Show suture bonding 498 in addition, this suture bonding 498 is routed to the 5th semiconductor element (for the sake of clarity also not shown) from the 4th semiconductor element 460, also is installed on the 3rd semiconductor element 450.
Noticed about the LTCC method that electrical interconnection is provided to semiconductor element that as above the three-dimensional interconnection that provided specifically is not provided this method, and the three-dimensional electrical wiring in the structure also is limited.Alternative prior art solution is illustrated as the three-dimensional interconnect structure 500 of Fig. 5 and corresponding electrical interconnection 550.Form the electrical interconnection 550 that proposes as Kunishi by mold pressing (stamping).Three-dimensional interconnect structure 500 comprises body 510, breech lock 506 and the electrical interconnection 550 that fits together.Corresponding body 510 has hole 504, and hole 504 has sidewall 504a and 504b, allows suitably location electrical interconnection 550 and breech lock, with this three-dimensional interconnect structure 500 other element interconnections as its a part of device.Therefore, breech lock 506 stretches out by hole 504, and interconnection tab 502b and 502c also are like this.Edge connector contact 502a passes another hole array and stretches out (for the sake of clarity also not shown).
With reference now to electrical interconnection 550,, can clearly see a plurality of electrical leads 502, each electrical lead 502 is from edge connector contact 502a, and the other end ends among big interconnection tab 502b or the little interconnection tab 502c.It is evident that, although this allow three-dimensional interconnection and be suitable for multiple systems (as, automobile-used), yet this method is expensive and do not meet the demand of the structure stacked chip-scale encapsulation (S-CSP) 165 in the exemplary chip lamination 400 of Fig. 4.
Correspondingly, show the example embodiment of the present invention that is used between first device 610 and second device 620, providing any interconnection structure 600 with reference to figure 6A.In Fig. 6 B, show the electrical interconnection that in this any interconnection structure 600, realizes by connecting mapping graph 690.Like this, first pad 615 (being represented by A to F) of first device 610 is according to pairing (A-6), (B-5), (C-2), (D-4), (E-1) with (F-3) be connected to second pad 625 (representing by 1 to 6 respectively) of second device 620.
Arrange interconnection 630 arbitrarily between first device 610 and second device 620, this interconnects arbitrarily and 630 comprises a plurality of electric conductors disposed therein 640 to 665.First electric conductor 640 provides wiring (A-6), and second electric conductor 645 provides wiring (B-5), and the 3rd electric conductor 650 is realized connecting (C-2), and the 4th electric conductor provides (D-4), and the 5th electric conductor provides (E-1), and the 6th electric conductor provides connection (F-3).The end view of any interconnection structure 600 has been shown in Fig. 6 C, wherein, has shown the electric conductor 640 to 665 with arbitrary shape, each electric conductor 640 to 665 is realized with its horizontal or vertical transition, provides required electrical interconnection to adopt smoothed curve.In the prior art, as provide the LTCC substrate 319 of sandwich construction 350, only horizontal transition may be implemented as full curve.
The advantage that the full curve electric conductor is provided be device or the encapsulation between electrical interconnection in transmit high-speed signals.Like this, can be according to the purpose that minimizes abrupt change, rather than typically minimize the purpose of the number of plies in the structure, realize wiring.Can use such as interpolation manufacturing technologies such as stereolithography (stereolithography) and three dimensional printings and realize described any interconnection 630.
With reference now to Fig. 7,, shows the cross-sectional view of the arbitrary structures 700 of another example embodiment according to the present invention.As directed, semiconductor element 720 is installed on the carrier 710, between semiconductor element 720 and carrier 710, need serial electrical interconnection.Correspondingly, utilizing arbitrarily, interconnection 730 realizes described electrical interconnection.On the upper surface of semiconductor element 720, show first electrical bonding pads and second electrical bonding pads 776 and 778 respectively, and on the upper surface of carrier 710, show first electric trace and second electric trace 772 and 774 respectively.First electric trace 772 is electrically connected to first interconnection 781 arbitrarily, described first any interconnection 781 comprises vertical transition, be the transition outside cross sectional planes after described vertical transition, indicated as conductor ⊙ 742, first arbitrarily interconnection 781 connect up towards the observer.
Second electric trace 774 is electrically interconnected to second interconnection 782 arbitrarily of vertical transition, and then via the interconnection 786 that has formalized and the 3rd interconnection 785 and second electrical bonding pads 778 interconnection arbitrarily.Obviously, along with the interconnection 786 that has formalized and semiconductor element 720 and carrier 710 separate fartherly, the interconnection 786 that has formalized not only provides the vertical transition of inclination, and reducing gradually of metallide thickness also is provided.The interconnection 786 that has formalized also is implemented as super material (meta-material) structure, wherein, the metallide structure 765 of design isolated and embedded grounding electrode 760, so that the signals in the interconnection that formalized 786 work in such a way: it is different with permeability with real component (real component) dielectric constant of the insulator that is used to provide any interconnection 730 bodies to make that the shape of this signal shows as dielectric constant (permittivity) and permeability (permeability).Because embedded grounding electrode 760 must interconnect with earth potential, every end of this embedded grounding electrode 760 comprises left conductor ⊙ 744 and right conductor ⊙ 746, and they are routed to earth potential and connect (for the sake of clarity also not shown).
With two electrical interconnections 783 and 784 first electrical bonding pads 776 has been described respectively.First pad 783 transits to outlying observation person and the conductor that connects up
Figure GPA00001052750300091
Second electrical interconnection 784 transits to the conductor ⊙ 748 towards the observer.The most coaxial connection 750 embeds in the upper left corner of interconnection 730 arbitrarily.Coaxial connection 750 comprises central signal line 750C, external ground ring 750B and dielectric 750A.Alternatively, dielectric 750A is different with the dielectric of the body that forms any interconnection 730.
With reference to figure 8, show compound arbitrary structures 800, wherein,, that top arbitrary structures 830 and bottom arbitrary structures 810 is combined providing to semiconductor element 820 in encapsulation and the electrical interconnection.Different with previous semiconductor element, utilize the semiconductor element 820 of 825 couples of Fig. 8 of layer to carry out back metallization, to improve the capacity of heat transmission and the ground connection of semiconductor element 820 is provided.This ground connection is to be provided by the bottom conductor in the bottom arbitrary structures 810 880, this bottom conductor 880 is connected to first pad 812, and thereby be connected to first upper conductor 832 in the top arbitrary structures 830, wherein as by the ⊙ indication, this first upper conductor 832 connects up towards the observer.
Also be embedded in data/address bus array 870 at bottom arbitrary structures 810, this data/address bus array 870 comprises the conductor 874 in the dielectric 872, and the characteristic of described dielectric 874 is different with the characteristic of bottom arbitrary structures 810.In addition, also in bottom arbitrary structures 810, form thermal liquid cooling element 880, thermal liquid cooling element 880 is to be made by the another kind of material different with the material of bottom arbitrary structures 810 and dielectric 872, and thermal liquid cooling element 880 comprises a series of liquid conduits 885, in described liquid conduits 885, can inhale cooling fluid by pump, liquid reservoir, heat exchange, pump etc. for the sake of clarity are not shown.
Second pad 814 on the upper surface of bottom arbitrary structures 810 is electrically connected to the top electric conductor that is formed by element 852,854 and 856, is routed to second pipe core welding disc 824 respectively.First and three element 852 and 854 outlying observation person transition, have the thickness of variation and separate with semiconductor element 820, connect them by second element 854.The person's that needs the outlying observation described transition is implemented in the top electric conductor of wiring around the coaxial configuration 865, and this top electric conductor vertically is coupled away from first pipe core welding disc 822.This coaxial configuration 865 is equivalent to the coaxial connection 750 of Fig. 7.Yet as directed, coaxial configuration ends at the cavity 860 in the top arbitrary structures 830.The size of cavity 860 is set to allow the insertion of coaxial connector, and is for the sake of clarity also not shown.The 3rd pipe core welding disc 826 directly is coupled through the body of top arbitrary structures 830 via the power supply bar 864 that stops in contact 862.In addition, as directed, be embedded in coplanar waveguide structure 840 at top arbitrary structures 830.
As given, bottom arbitrary structures 810 is included in the multiple material that deposits simultaneously when making three-dimensional structure, also comprises the embedded cavity structure of non-rectangle cross section.Similarly, top arbitrary structures 830 comprises mechanical fixation (referring to cavity 860) and electric structure.Alternatively, according to semiconductor element 820, top arbitrary structures 810 and bottom arbitrary structures 830 can be manufactured to single monolithic unit respectively, make semiconductor element 820 is inserted in the cavity.
With reference to figure 9A, utilize the plane cross section of encapsulation 900, provided the alternative approach of the heat management of semiconductor element 910.Different with traditional semiconductor element, on all four sidewalls, semiconductor element 910 is metallized, metallide is illustrated as top metal 910A, left side metal 910B, right side metal 910C and lower metal 910D.Fin (thermal slug) 950 contacts with among four metallized wall 910A to 910D each, six fin 950 form the interface on each respectively in upper metal and lower metal 910A and 910D, and two fin 950 form the interface on each respectively in left side metal and right side metal 910B and 910C.Around encapsulation 900 peripheries, 920A to 920D is deposited on each sidewall with radiator (heat sink), radiator 920A to 920D and fin 950 thermo-contacts.Array electric trace 930 is deposited between the fin 950, simultaneously second trace array 940 is deposited in two angles of encapsulation 900.
In Fig. 9 B, illustrated and encapsulated 900 the first cross section Y=Y, shown electric trace 930, top heat sink and the bottom heat spreader 920A and 920D and the cap 970 that pass through encapsulation 900 and in solder sphere 960, stop downwards.Encapsulating this in 970 is electric trace 972 to 976, and electric trace 972 to 976 is routed to electric trace 930 from the upper surface contact of semiconductor element 910.As directed, in cross section Y=Y, upper metallization thing and lower metal thing 910A and 910D are present on the semiconductor element respectively.Show the cross section X=X of encapsulation 900 in Fig. 9 C, these upper metallization thing 910A and lower metal thing 910D are connected to fin 950 respectively, and fin 950 is thermally coupled to top heat sink and bottom heat spreader 920A and 920D again respectively.
Like this, encapsulation 900 comprises during manufacture the multiple material of deposition simultaneously, and these materials are: the main dielectric of encapsulation 900, the metallide (copper, gold or aluminium typically) of electric trace 930, the metal (for example can be molybdenum, copper or copper-tungsten) and the metal heat sink (aluminium typically) of fin.In addition, for example can during the single manufacturing step in the three dimensional printing step that forms encapsulation 900, deposit tin-silver-copper SnAgCu, so that no wire bonds to be provided.Alternatively, fin can be a beryllium oxide.
The current encapsulation scheme that more than is called " industrial standard " provides electrical interconnection on an only side/one surface of encapsulation.Yet in many cases, it can be favourable providing electrical interconnection on many sides/a plurality of surfaces of encapsulation.This method allows stacked package for example horizontal or vertically, makes directly to realize electrical interconnection from being encapsulated into encapsulation ground, rather than via intermediate circuit plate or movable interconnection.Figure 10 illustrates this exemplary distributed interconnection encapsulation 1000.Distributed interconnection encapsulation 1000 comprises 26 surfaces, and its similar is cut in jewel, adopts to have the rectangular configuration on inclined-plane on each angle.As directed, upper surface 1010 comprises the first electrical interconnection array 1015, and sidewall 1030 provides the second electrical interconnection array 1035, provides the 3rd to be electrically connected array 1035 at upper surface 1010 with inclined-plane 1020 between the sidewall 1030.End wall 1040 has DC interconnection 1045 (as, ground connection), and inclined-plane, angle 1050 provides the 2nd DC interconnection 1055.Alternatively, use three dimensional printing, can be respectively distributed interconnection encapsulation 1000 pin or socket are provided at each shown electrical interconnection 1015,1025,1035,1045 and 1055.Thereby these pins and socket form supporting half part of electric connector.In addition, the three dimensional printing of distributed interconnection encapsulation 1000 can comprise mechanical features, as installing hole, screw thread plug-in part etc., make distributed interconnection encapsulation 1000 can physically interconnect to other interconnect package 1000, AN connector or circuit board, device panel etc.
Under the premise without departing from the spirit and scope of the present invention, can expect many other embodiment.

Claims (23)

1. method comprises:
(a) provide and relate to the design document that is used for forming with at least one electric device the mechanical structure at interface, described design document comprises at least two in the following project: the electricity input of described mechanical structure and electric output coordinate, electricity input and electricity exported the mechanical attributes and the list of materials of the power path information in the path that interconnects, the mechanical attributes of semiconductor element, described mechanical structure; And
(b) utilize three-dimensional manufacturing system to carry out described design document; Described three-dimensional manufacturing system produces described mechanical structure by in a plurality of sequential system manufacturing operations at least one as single monolithic unit, and each in described a plurality of sequential system manufacturing operations comprises that interpolation is from any material described list of materials, that thickness is littler than the thickness of any element in the described mechanical structure.
2. method according to claim 1, wherein,
(b) carrying out design document also comprises: described at least one electric device is installed in the mechanical structure of partly finishing at the executory predetermined point place of design document.
3. method according to claim 1, wherein,
Interpolation thickness comprises than the little material of thickness of any element in the described mechanical structure: add thickness less than 1/2nd of the thinnest electric device thickness in the described structure.
4. method according to claim 1, wherein,
Provide power path information to comprise: providing at least, its first derivative is continuous power path.
5. method according to claim 1, wherein,
Provide mechanical structure to comprise to provide at least one in the following project: install with electrical interconnection, heat management and the machinery of described at least one electric device.
6. method according to claim 1, wherein,
(b) carrying out design document also comprises: at least one operating period in a plurality of sequential system manufacturing operations, the diverse location in described mechanical structure adds at least two kinds of materials from described list of materials simultaneously with same levels.
7. method according to claim 1, wherein,
Carrying out design document forms along except when described mechanical structure axle in addition spool mechanical structure of making vertical with the first type surface of electric device when being assembled together with electric device.
8. method according to claim 1, wherein,
Provide mechanical attributes to comprise: data are provided, described data are for each the quantification position in the described mechanical structure, indicate the existence of every kind of material in the described list of materials, do not exist and percentage at least one, described quantification position is to determine according in described design document and the three-dimensional manufacturing system at least one.
9. method according to claim 1, described design document the term of execution do not remove any material from described mechanical structure.
10. method comprises:
Provide and relate to the design document that is used for forming the mechanical structure at interface with at least one electric device, described design document comprises at least two in the following project: the electricity input and the electric output coordinate of described mechanical structure, the power path information in the path that interconnects is exported in electricity input and electricity, the mechanical attributes of semiconductor element, the mechanical attributes of described mechanical structure, and list of materials, described design document relates to the three-dimensional manufacturing system of control, described three-dimensional manufacturing system can produce described mechanical structure as single monolithic unit by in a plurality of sequential system manufacturing operations at least one, and described sequential system manufacturing operation comprises that interpolation is from described list of materials, any material that thickness is littler than the thickness of any element in the described mechanical structure.
11. method according to claim 10, wherein:
Provide described design document by at least one item in the following project: the physical printed output of electric transmission, computer-readable recording medium, design document and convert cad documents to described three-dimensional manufacturing system compatibility form.
12. a method comprises:
(a) provide at least one electric devices of a plurality of electric devices;
(b) provide mechanical structure, described mechanical structure is used for forming the interface with the predetermined portions at least of at least one electric device of described a plurality of electric devices, described mechanical structure is to adopt three-dimensional manufacturing system to produce described mechanical structure by in a plurality of sequential system manufacturing operations at least one as single monolithic unit to make, and each in described a plurality of sequential system manufacturing operations comprises adds the minimum thickness little material of thickness than any element in the described mechanical structure; And
(c) with described at least one the electric device interconnection in described mechanical structure and the described a plurality of electric device.
13. method according to claim 12, wherein,
(c) mechanical structure interconnection is comprised at least one that provides in the following project: with machinery installation, electrical interconnection and the heat interconnection of described at least one electric device in described a plurality of electric devices.
14. method according to claim 12, wherein,
(a) provide at least one electric device to comprise: to provide described at least one electric device in a plurality of electric devices as first mechanical component; And (c) mechanical structure interconnection is comprised: the predetermined portions at least of mechanical structure and described first mechanical component is interconnected.
15. method according to claim 14, wherein,
(c) mechanical structure interconnection is comprised: provide described at least one electric device from a plurality of electric devices to the electrical interconnection of the predetermined portions of described first mechanical component.
16. method according to claim 12, wherein,
(c) the mechanical structure interconnection is comprised only with described at least one electric device in a plurality of electric devices and at least one electrical interconnection in the following project: this electric device itself, and another electric device in described a plurality of electric device.
17. method according to claim 12, wherein,
Provide at least one electric device to comprise to provide at least one in the following project: semiconductor element, be installed to carrier semiconductor element, above deposit substrate, the encapsulation of electric trace, the predetermined portions and the discrete electric element of semiconductor wafer.
18. method according to claim 12, wherein,
Described mechanical structure comprises at least one in the following project: metal material, dielectric substance and super material.
19. method according to claim 12, wherein,
Described mechanical structure provides at least one in the following project: electric tab connection, solder projection, line bonding welding pad, packaging pin, the socket that is used for electric connector, the socket that is used to insert electric connector, threaded area, space, the permission securing member that is used to hold the coupling screw thread of securing member insert hole, the installation surface that is used for integrated circuit, the installing rack that is used for optical fiber, the installing rack that is used for optoelectronic component, cavity, the pipeline that passes.
20. method according to claim 12, wherein,
Provide mechanical structure to comprise to provide at least one power path in a plurality of power paths, each power path is at least one in the following project: discrete conductor, co-planar waveguide, coaxial waveguide, coplane band, transmission line section, the transmission line section with super material elements, level face and continuous conductor series of elements.
21. method according to claim 20, wherein, each power path comprises provides at least one the power path that meets in the following project: at least one order derivative of this power path is continuous, and this power path comprises approximate abrupt tranaition on direction.
22. a method comprises:
(a) provide at least one electric device in a plurality of electric devices; And
(b) produce the mechanical structure that is associated with described at least one electric device in described a plurality of electric devices, described mechanical structure is used for forming the interface with the predetermined portions at least of at least one electric device of described a plurality of electric devices, described mechanical structure is to adopt three-dimensional manufacturing system to produce described mechanical structure by in a plurality of sequential system manufacturing operations at least one as single monolithic unit to make, and each in described a plurality of sequential system manufacturing operations comprises adds the minimum thickness little material of thickness than any element in the described mechanical structure.
23. method according to claim 22, wherein,
(b) producing mechanical structure comprises: the predetermined portions of described mechanical structure is directly produced on the fate of described at least one electric device of described a plurality of electric devices.
CN200880106804A 2007-09-14 2008-09-12 Method and apparatus for forming arbitrary structures for integrated circuit devices Pending CN101802989A (en)

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US9818665B2 (en) 2014-02-28 2017-11-14 Infineon Technologies Ag Method of packaging a semiconductor chip using a 3D printing process and semiconductor package having angled surfaces
EP3216690B1 (en) 2016-03-07 2018-11-07 Airbus Operations GmbH Method for manufacturing a lining panel
DE102018104144B4 (en) 2018-02-23 2022-12-15 Technische Universität Chemnitz Process for contacting and packaging a semiconductor chip

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US5278442A (en) * 1991-07-15 1994-01-11 Prinz Fritz B Electronic packages and smart structures formed by thermal spray deposition
US5779833A (en) * 1995-08-04 1998-07-14 Case Western Reserve University Method for constructing three dimensional bodies from laminations

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CN104485416B (en) * 2013-11-22 2018-11-27 北京大学 A kind of resistance-variable storing device and preparation method thereof using Meta Materials electrode structure
CN111640842A (en) * 2020-07-02 2020-09-08 江文涛 Packaging structure for packaging LED flip chip and packaging method thereof

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