CN101794713A - Thin film transistor and manufacturing method thereof - Google Patents
Thin film transistor and manufacturing method thereof Download PDFInfo
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- CN101794713A CN101794713A CN 201010143282 CN201010143282A CN101794713A CN 101794713 A CN101794713 A CN 101794713A CN 201010143282 CN201010143282 CN 201010143282 CN 201010143282 A CN201010143282 A CN 201010143282A CN 101794713 A CN101794713 A CN 101794713A
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Abstract
The invention discloses a thin film transistor and a manufacturing method thereof. The thin film transistor comprises a channel layer, an ohmic contact layer, a dielectric layer, a source electrode, a drain electrode, a grid electrode and a grid insulation layer, wherein the channel layer has an upper surface and a side face; the ohmic contact layer is arranged on partial area of the upper surface of the channel layer; the dielectric layer is arranged on the side face of the channel layer, and the dielectric layer is not overlapped with the ohmic contact layer; the source electrode and the drain electrode are arranged on partial areas of the ohmic contact layer and the dielectric layer, and partial areas of the dielectric layer are not covered by the source electrode and the drain electrode; the grid electrode is positioned above or under the channel layer; and the grid insulation layer is arranged between the grid electrode and the channel layer.
Description
Technical field
The present invention relates to a kind of semiconductor element and manufacture method thereof, and particularly relate to a kind of thin-film transistor and manufacture method thereof.
Background technology
In recent years, increasingly mature along with photoelectric technology and semiconductor fabrication, flat-panel screens is just flourish, wherein LCD is based on advantage such as its low voltage operating, radiationless line scattering, in light weight and volume be little, replaces traditional cathode-ray tube display more gradually and becomes the main flow of display product in recent years.Generally speaking, LCD can be divided into two kinds of amorphous silicon film transistor (amorphoussilicon thin film transistor) LCD and low-temperature polysilicon film transistor (lowtemperature poly-silicon thin film transistor) LCD etc.
Figure 1A is a kind of generalized section of existing thin-film transistor.Please refer to Figure 1A, thin-film transistor 100 is disposed on the substrate 101, thin-film transistor 100 comprises grid 110, patterning amorphous silicon layer (being channel layer) 120, source electrode 130 and drains 132 that wherein source electrode 130 and 132 meetings that the drain ohmic contact layer 140 that passes through out of the ordinary be connected with channel layer 120.When thin-film transistor 100 was unlocked, grid 100 can be applied in high voltage, so that channel layer 120 presents the state of conducting, and then made source electrode 130 and drain electrode 132 mutual conduction.Yet; when thin-film transistor 100 is not unlocked; though grid 110 is not applied to high voltage, channel layer 120 regular meetings are subjected to the irradiation of extraneous light and produce leakage current (leakagecurrent), and therefore influence the element reliability (reliability) of thin-film transistor 100.In order to suppress leakage current, existing prior art proposes to increase the improvement method of one plasma treatment (Plasma treatment) in the manufacture craft of thin-film transistor 100.Figure 1B is existing plasma treatment schematic diagram.Please refer to Figure 1B, generally speaking, plasma treatment can be after ohmic contact layer 140 and photoresist layer 150 patterning and form source electrode 130 and 132 second layer metal deposition of draining before carry out, and the employed plasma 160 of plasma treatment can be oxygen plasma (O
2-plasma) or argon plasma (Ar-plasma).After plasma treatment, it is the film of silica (Si-Ox) that the side 121 of channel layer 120 and 123 can form one deck material, to suppress leakage current.
Fig. 1 C is a kind of generalized section of existing thin-film transistor.Please refer to Figure 1A and Fig. 1 C, its difference is that source electrode 170, drain electrode 172 and ohmic contact layer 180 utilization of thin-film transistor 102 make with reticle fabrication process, so source electrode 170 172 is understood and be had identical pattern with ohmic contact layer 180 with draining.Yet at the thin-film transistor of Fig. 1 C, the problem of leakage current still can't obtain effective solution.
Summary of the invention
The object of the present invention is to provide a kind of thin-film transistor and manufacture method thereof, can reduce leakage current.
The present invention proposes a kind of method of manufacturing thin film transistor, and it comprises the following steps.On substrate, form grid.On substrate, form gate insulation layer, with cover gate.Form channel material layer, ohmic contact material layer and patterning photoresist layer on gate insulation layer in regular turn, wherein patterning photoresist layer is positioned at the grid top.With patterning photoresist layer is mask, and patterning channel material layer and ohmic contact material layer are to form channel layer and the ohmic contact layer between channel layer and patterning photoresist layer.On the side of the side of patterning photoresist layer, channel layer, ohmic contact layer and gate insulation layer, form dielectric layer.The part dielectric layer that removes patterning photoresist layer and contact with patterning photoresist layer is so that ohmic contact layer is exposed.On part dielectric layer and part ohmic contact layer, form source electrode and drain electrode, and will do not removed by the ohmic contact layer of source electrode and drain electrode covering.
In one embodiment of this invention, method of manufacturing thin film transistor more comprises the formation protective layer, to cover source electrode, drain electrode, part dielectric layer and part channel layer.
The present invention proposes a kind of method of manufacturing thin film transistor in addition, and it comprises the following steps.On substrate, form channel material layer, ohmic contact material layer and patterning photoresist layer in regular turn.With patterning photoresist layer is mask, and patterning channel material layer and ohmic contact material layer are to form channel layer and the ohmic contact layer between channel layer and patterning photoresist layer.On the side of the side of patterning photoresist layer, channel layer and ohmic contact layer, form dielectric layer.The part dielectric layer that removes patterning photoresist layer and contact with patterning photoresist layer is so that ohmic contact layer is exposed.On part dielectric layer and part ohmic contact layer, form source electrode and drain electrode, and will do not removed by the ohmic contact layer of source electrode and drain electrode covering.On substrate, form gate insulation layer, to cover source electrode, drain electrode, part dielectric layer and part channel layer.Form grid on gate insulation layer, wherein grid is positioned at the channel layer top.
In one embodiment of this invention, the method for the above-mentioned part dielectric layer that removes patterning photoresist layer and contact with patterning photoresist layer comprises and lifts off manufacture craft (lift-off process).
In one embodiment of this invention, above-mentioned after patterning photoresist layer is removed, dielectric layer is connected with the side of ohmic contact layer, and dielectric layer and ohmic contact layer are not overlapping.
In one embodiment of this invention, method of manufacturing thin film transistor more comprises the formation protective layer, with cover gate and gate insulation layer.
In one embodiment of this invention, above-mentioned dielectric layer more comprises on the subregion that is covered in substrate.
In one embodiment of this invention, before forming the channel material layer, method of manufacturing thin film transistor more is included in and forms resilient coating on the substrate, and above-mentioned dielectric layer more comprises on the subregion that is covered in resilient coating.
The present invention also proposes a kind of thin-film transistor, is suitable for being disposed on the substrate.Thin-film transistor comprises channel layer, ohmic contact layer, dielectric layer, source electrode, drain electrode, grid and gate insulation layer.Channel layer has upper surface and side.Ohmic contact layer is disposed on the subregion of upper surface of channel layer.Dielectric layer is disposed on the side of channel layer, and dielectric layer and ohmic contact layer are not overlapping.Source electrode and drain configuration are on the subregion of ohmic contact layer and dielectric layer, and the subregion of dielectric layer is not covered by source electrode and drain electrode.Grid is positioned at above or below the channel layer.Gate insulation layer is disposed between grid and the channel layer.
In one embodiment of this invention, when grid is positioned at channel layer below, gate insulation layer is disposed on the substrate with cover gate, and dielectric layer extends on the substrate from the side of channel layer.
In one embodiment of this invention, thin-film transistor more comprises protective layer, to cover source electrode, drain electrode, part dielectric layer and part channel layer.
In one embodiment of this invention, above grid was positioned at channel layer, gate insulation layer covered source electrode, drain electrode, part dielectric layer and part channel layer.
In one embodiment of this invention, thin-film transistor more comprises protective layer, with cover gate and gate insulation layer.
In one embodiment of this invention, thin-film transistor more comprises resilient coating, and it is between dielectric layer and the substrate and between channel layer and the substrate.
Based on above-mentioned, thin-film transistor of the present invention and manufacture method thereof can suppress leakage current effectively, and then promote reliability.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate appended accompanying drawing to be described in detail below.
Description of drawings
Figure 1A is a kind of generalized section of existing thin-film transistor;
Figure 1B is existing plasma treatment schematic diagram;
Fig. 1 C is a kind of generalized section of existing thin-film transistor;
Fig. 2 A to Fig. 2 H is the manufacturing process generalized section of the thin-film transistor of the first embodiment of the present invention;
Fig. 3 A to Fig. 3 I is the manufacturing process generalized section of the thin-film transistor of the second embodiment of the present invention.
The main element symbol description
101,210,310: substrate
100,102,220,320: thin-film transistor
110,222,338: grid
120,226a, 324a: channel layer
121,123: the side
130,170,234,332: source electrode
132,172,236,334: drain electrode
140,180,228a, 326a: ohmic contact layer
150,230,328: the photoresist layer
160: plasma
224,336: gate insulation layer
226,324: the channel material layer
228,326: the ohmic contact material layer
232,330: dielectric layer
238,340: protective layer
322: resilient coating
Embodiment
First embodiment
Fig. 2 A to Fig. 2 H is the manufacturing process generalized section of the thin-film transistor of the first embodiment of the present invention.Please refer to Fig. 2 A, the manufacture method of the thin-film transistor 220 of present embodiment comprises the following steps.At first, on substrate 210, form grid 222, and can pass through the first road photoetching process (1 at grid 222
StPhotolithography and Etch Process, 1
StPEP) form.Wherein, the material of substrate 210 can be inorganic transparent material (for example glass, quartz, other suitable material and combination thereof), organic transparent material (for example polyalkenes, poly-Hai class, polyalcohols, polyesters, rubber, thermoplastic polymer, thermosetting polymer, poly aromatic hydro carbons, poly-methyl-prop vinegar acid methyl esters class, polycarbonate-based, other suitable material, above-mentioned derivative and combination thereof), inorganic transparent materials (for example silicon chip, pottery, other suitable material or above-mentioned combination) or above-mentioned combination.
Please refer to Fig. 2 B, then, on substrate 210, form gate insulation layer 224, with cover gate 222 and substrate 210.For example, the material of gate insulation layer 224 for example is silica (SiOx) or silicon nitride inorganics such as (SiNx).Please refer to Fig. 2 C, then, on gate insulation layer 224, form channel material layer 226 in regular turn, ohmic contact material layer (ohmic contact material layer) 228 and patterning photoresist layer 230, wherein patterning photoresist layer 230 is positioned at grid 222 tops, and the material of patterning photoresist layer 230 can be photoresist (Photo resist, PR), metal or removable material, the material of ohmic contact material layer 228 can be the semi-conducting material of N type doping, as N type doped amorphous silicon (n+a-Si), and the material of channel material layer 226 can be amorphous silicon (a-Si).
Please refer to Fig. 2 D, then, with patterning photoresist layer 230 is mask, be not patterned ohmic contact material layer 228 and the part channel material layer 226 that photoresist layer 230 covers to remove, and then form the channel layer 226a of patterning and the ohmic contact layer 228a between channel layer 226a and photoresist layer 230.
Please refer to Fig. 2 E, on the side of the side of patterning photoresist layer 230, channel layer 226a, ohmic contact layer 228a and gate insulation layer 224, form dielectric layer 232, and the depositional mode of dielectric layer 232 can be physical vapour deposition (PVD) (physical vapor deposition, PVD), chemical vapour deposition (CVD) (chemical vapor deposition, CVD) or solution rotating coating (Spin-Coating).Wherein the material of dielectric layer 232 can be silica (SiOx), silicon nitride (SiNx) or silicon oxynitride (SiON), and physical vapour deposition (PVD) for example is a sputtering method (sputtering), chemical vapour deposition (CVD) for example be plasma chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD).
Please refer to Fig. 2 F, the part dielectric layer 232 that then removes patterning photoresist layer 230 and contact with patterning photoresist layer 230 is so that ohmic contact layer 228a is exposed.Wherein, remove patterning photoresist layer 230 and the method for the part dielectric layer 232 that contacts with patterning photoresist layer 230 can be for lifting off manufacture craft (lift-off process).And after patterning photoresist layer 230 was removed, dielectric layer 232 was connected with the side of ohmic contact layer 228a, and dielectric layer 232 is not overlapping with ohmic contact layer 228a.
Please refer to Fig. 2 G, then, on part dielectric layer 232 and part ohmic contact 228a layer, form source electrode 234 and drain 236, and will do not removed by the source electrode 234 and the 236 ohmic contact layer 228a that cover that drain.Shown in Fig. 2 G, source electrode 234 and to drain 234 be by the 3rd road photoetching process (3
RdPEP) form, and this photoetching process is half mode photoetching process (HTMprocess), gray scale photoetching process (GM process) or slit photoetching process (SM process), therefore present embodiment can further reduce the quantity of employed photoetching process, and then reduces manufacturing cost and man-hour.Please refer to Fig. 2 H, last, form the protective layer 238 that covers source electrode 234, drain electrode 236, part dielectric layer 232 and part channel layer 226a, with protective film transistor 220.
Shown in Fig. 2 H, thin-film transistor 220 is bottom-gate (bottom-gate) thin-film transistor, and has grid 222, gate insulation layer 224, channel layer 226a, ohmic contact layer 228a, dielectric layer 232, source electrode 234, drain electrode 236 and protective layer 238.Grid 222 is positioned at the below of channel layer 226a.Gate insulation layer 224 is disposed between grid 222 and the channel layer 226a.Ohmic contact layer 228a is disposed on the subregion of upper surface of channel layer 226a.Dielectric layer 232 is disposed on the side of channel layer 226a, and 232 layers of dielectrics are in contact with one another with ohmic contact layer 228a but not overlapping.Source electrode 234 and draining 236 is disposed on the subregion of ohmic contact layer 228a and dielectric layer 232, and the subregion of dielectric layer 232 not by source electrode 234 and drain 236 cover.Protective layer 238 covers source electrode 234, drain electrode 236, part dielectric layer 232 and part channel layer 226a.
Second embodiment
Fig. 3 A to Fig. 3 I is the manufacturing process generalized section of the thin-film transistor of the second embodiment of the present invention.Please refer to Fig. 3 A, the manufacture method of the thin-film transistor 320 of present embodiment comprises the following steps.At first, form 322 on substrate 310, wherein the material of resilient coating 322 can be dielectric materials such as silica, silicon nitride.
Please refer to Fig. 3 B to Fig. 3 D, then, form channel material layer 324, ohmic contact material layer 326 and patterning photoresist layer 328 in regular turn on resilient coating 322, wherein the material of channel material layer 324 can be amorphous silicon or polysilicon (poly-Si).Similarly, be mask with patterning photoresist layer 328,326 layers of patterning channel material layer 324 and ohmic contact materials are to form channel layer 324a and the ohmic contact layer 326a between channel layer 324a and patterning photoresist layer 328.Then, forming dielectric layer 330 on the side of the side of patterning photoresist layer 328, channel layer 324a, ohmic contact layer 326a and on the subregion of resilient coating 322.
Please refer to Fig. 3 E to Fig. 3 F, then, the part dielectric layer 330 that removes patterning photoresist layer 328 and contact with patterning photoresist layer 328, so that ohmic contact layer 326a is exposed, wherein after patterning photoresist layer 328 is removed, dielectric layer 330 is connected with the side of ohmic contact layer 326a, and dielectric layer 330 is not overlapping with ohmic contact layer 326a.Then, on dielectric layer 330 partly and part ohmic contact layer 326a, form source electrode 332 and drain 334, and will do not removed by the source electrode 332 and the 334 ohmic contact layer 326a that cover that drain.
Please refer to Fig. 3 G to Fig. 3 I, next, on substrate 310, form gate insulation layer 336, to cover source electrode 332, drain electrode 324, part dielectric layer 330 and part channel layer 326a.Afterwards, form grid 338 on gate insulation layer 336, wherein grid 338 is positioned at channel layer 324a top.At last, form protective layer 340 with cover gate 338 and gate insulation layer 336.
Shown in Fig. 3 I, thin-film transistor 320 is top grid (top-gate) thin-film transistor, and has resilient coating 322, channel layer 324a, ohmic contact layer 326a, dielectric layer 330, source electrode 332, drain electrode 334, grid 338 and protective layer 340.Resilient coating 322 is between dielectric layer 330 and substrate 310, and between channel layer 324a and substrate 310.Ohmic contact layer 326a is disposed on the subregion of upper surface of channel layer 324a.Dielectric layer 330 is disposed on the side of channel layer 324a, and 330 layers of dielectrics are in contact with one another with ohmic contact layer 326a but not overlapping.Source electrode 332 and draining 334 is disposed on the subregion of ohmic contact layer 326a and dielectric layer 330, and the subregion of dielectric layer 330 not by source electrode 332 and drain 334 cover.Grid 338 is positioned at the top of channel layer 324a.Gate insulation layer 336 is disposed between grid 338 and the channel layer 324a, and covers source electrode 332, drain electrode 334, part dielectric layer 330 and part channel layer 324a.Protective layer 340 cover gate 338 and gate insulation layer 336.
What deserves to be mentioned is, when the material of channel layer 324a is amorphous silicon, then can omit resilient coating 332 in the structure of thin-film transistor 320, also can ignore the step that forms resilient coating 332 and on substrate 310, directly form channel layer 324a, and part dielectric layer 330 can be covered on the substrate 310.
In sum, the thin-film transistor of the embodiment of the invention and manufacture method thereof can suppress leakage current effectively.In addition, because the patterning of dielectric layer can be finished via lifting off manufacture craft, therefore can reduce manufacturing cost and man-hour.
Though disclosed the present invention in conjunction with above embodiment; yet it is not in order to limit the present invention; be familiar with this operator in the technical field under any; without departing from the spirit and scope of the present invention; can do a little change and retouching, thus protection scope of the present invention should with enclose claim was defined is as the criterion.
Claims (17)
1. method of manufacturing thin film transistor comprises:
On a substrate, form a grid;
On this substrate, form a gate insulation layer, to cover this grid;
Form a channel material layer, an ohmic contact material layer and a patterning photoresist layer on this gate insulation layer in regular turn, wherein this patterning photoresist layer is positioned at this grid top;
With this patterning photoresist layer is mask, and this channel material layer of patterning and this ohmic contact material layer are to form the ohmic contact layer of a channel layer and between this channel layer and this patterning photoresist layer;
On the side of the side of this patterning photoresist layer, this channel layer, this ohmic contact layer and this gate insulation layer, form a dielectric layer;
This dielectric layer of part that removes this patterning photoresist layer and contact with this patterning photoresist layer is so that this ohmic contact layer is exposed; And
Partly forming an one source pole and a drain electrode on this dielectric layer and this ohmic contact layer of part, and will do not removed by this ohmic contact layer of this source electrode and this drain electrode covering.
2. method of manufacturing thin film transistor as claimed in claim 1, the method that wherein removes this patterning photoresist layer and this dielectric layer of part of contacting with this patterning photoresist layer comprises lifts off manufacture craft (lift-offprocess).
3. method of manufacturing thin film transistor as claimed in claim 1, wherein after this patterning photoresist layer was removed, this dielectric layer was connected with the side of this ohmic contact layer, and this dielectric layer and this ohmic contact layer are not overlapping.
4. method of manufacturing thin film transistor as claimed in claim 1 also comprises forming a protective layer, to cover this source electrode, this drain electrode, this dielectric layer of part and this channel layer of part.
5. method of manufacturing thin film transistor comprises:
On a substrate, form a channel material layer, an ohmic contact material layer and a patterning photoresist layer in regular turn;
With this patterning photoresist layer is mask, and this channel material layer of patterning and this ohmic contact material layer are to form the ohmic contact layer of a channel layer and between this channel layer and this patterning photoresist layer;
On the side of the side of this patterning photoresist layer, this channel layer and this ohmic contact layer, form a dielectric layer;
This dielectric layer of part that removes this patterning photoresist layer and contact with this patterning photoresist layer is so that this ohmic contact layer is exposed;
Partly forming an one source pole and a drain electrode on this dielectric layer and this ohmic contact layer of part, and will do not removed by this ohmic contact layer of this source electrode and this drain electrode covering;
On this substrate, form a gate insulation layer, to cover this source electrode, this drain electrode, this dielectric layer of part and this channel layer of part; And
Form a grid on this gate insulation layer, wherein this grid is positioned at this channel layer top.
6. method of manufacturing thin film transistor as claimed in claim 5, the method that wherein removes this patterning photoresist layer and this dielectric layer of part of contacting with this patterning photoresist layer comprises lifts off manufacture craft (lift-off process).
7. method of manufacturing thin film transistor as claimed in claim 5, wherein after this patterning photoresist layer was removed, this dielectric layer was connected with the side of this ohmic contact layer, and this dielectric layer and this ohmic contact layer are not overlapping.
8. method of manufacturing thin film transistor as claimed in claim 5 also comprises forming a protective layer, to cover this grid and this gate insulation layer.
9. method of manufacturing thin film transistor as claimed in claim 5, wherein this dielectric layer also comprises on the subregion that is covered in this substrate.
10. method of manufacturing thin film transistor as claimed in claim 5 before forming this channel material layer, also is included in and forms a resilient coating on this substrate.
11. method of manufacturing thin film transistor as claimed in claim 10, wherein this dielectric layer also comprises on the subregion that is covered in this resilient coating.
12. a thin-film transistor is suitable for being disposed on the substrate, this thin-film transistor comprises:
Channel layer has a upper surface and a side;
Ohmic contact layer is disposed on the subregion of this upper surface of this channel layer;
Dielectric layer is disposed on this side of this channel layer, and this dielectric layer and this ohmic contact layer are not overlapping;
A source electrode and a drain electrode be disposed on the subregion of this ohmic contact layer and this dielectric layer, and the subregion of this dielectric layer are not covered by this source electrode and this drain electrode;
Grid is positioned at above or below this channel layer; And
Gate insulation layer is disposed between this grid and this channel layer.
13. thin-film transistor as claimed in claim 12 wherein is positioned at this channel layer below when this grid, this gate insulation layer is disposed on this substrate covering this grid, and this dielectric layer extends on this substrate from this side of this channel layer.
14. thin-film transistor as claimed in claim 13 also comprises a protective layer, to cover this source electrode, this drain electrode, this dielectric layer of part and this channel layer of part.
15. thin-film transistor as claimed in claim 12, wherein above this grid was positioned at this channel layer, this gate insulation layer covered this source electrode, this drain electrode, this dielectric layer of part and this channel layer of part.
16. thin-film transistor as claimed in claim 15 also comprises a protective layer, to cover this grid and this gate insulation layer.
17. thin-film transistor as claimed in claim 15 also comprises a resilient coating, between this dielectric layer and this substrate and between this channel layer and this substrate.
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| CN 201010143282 CN101794713A (en) | 2010-03-18 | 2010-03-18 | Thin film transistor and manufacturing method thereof |
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| CN 201010143282 CN101794713A (en) | 2010-03-18 | 2010-03-18 | Thin film transistor and manufacturing method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102709329A (en) * | 2012-06-14 | 2012-10-03 | 深超光电（深圳）有限公司 | Thin film transistor and manufacturing method thereof |
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Application publication date: 20100804 |