CN101145562A - TFT matrix structure and making method thereof - Google Patents
TFT matrix structure and making method thereof Download PDFInfo
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- CN101145562A CN101145562A CNA200610152023XA CN200610152023A CN101145562A CN 101145562 A CN101145562 A CN 101145562A CN A200610152023X A CNA200610152023X A CN A200610152023XA CN 200610152023 A CN200610152023 A CN 200610152023A CN 101145562 A CN101145562 A CN 101145562A
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Abstract
The invention discloses a TFT array structure which comprises a substrate; a gate line and a gate electrode integrated therewith; a first insulating layer, a semi-conductive layer and an ohmic contact layer which are covered in order above the gate and the gate electrode; a thin-film transistor groove; a second gate insulating layer formed on the ohmic contact layer to expose the thin-film transistor groove and a part of the ohmic contact layer; data wires and a source electrode integrated therewith which both are directly lapped on the ohmic contact layer; a drain electrode directly lapped on the ohmic contact layer; a passivation layer formed above the data wires, the source electrode and the drain electrode; a pixel electrode formed on the second insulating layer and lapped partially with the drain electrode; a groove formed on the gate line between the data wires and cutting off the ohmic contact layer above the gate line. The invention also discloses a fabrication method of the TFT array structure. The inventive array structure and the fabrication method thereof can shorten the production cycle of the TFT array and reduce the production cost.
Description
Technical field
The present invention relates to a kind of thin-film transistor (TFT) matrix structure and manufacture method thereof, particularly a kind of TFT matrix structure and manufacture method thereof by four photoetching preparation.
Background technology
The liquid crystal display mode is the main flow of present flat panel display, and active driving TFT LCD (Thin Film Transistor-LCD) then is the leading display mode in the field of liquid crystal display.The manufacturing process of TFT LCD is compatible mutually with traditional IC circuit, the display quality excellence, low in energy consumption, in light weight, radiationless, be a kind of very friendly man-machine communication interface, its main application fields has notebook computer, desktop computer monitor, work station, industry monitoring device, GPS (Global Position System) (GPS), personal data processing, game machine, video telephone, portable V CD, DVD and some other portable units.
For price and its rate of finished products of raising of reducing TFT LCD effectively, the manufacturing process of active drive thin film transistors (TFT) matrix progressively obtains simplifying, from seven times or six photoetching generally five photoetching of employing till now of beginning.Recently, four photoetching processes based on gray mask version photoetching " Gray Tone Mask " technology begin to set foot in the manufacturing field of TFT LCD and progressively be applied, and its core process is used active layer photoetching (Active Mask) and the source-drain electrode photoetching (S/D Mask) in five photoetching processes of source-drain electrode (S/D) Gray Tone Mask replacement tradition exactly.Its specific embodiment is as follows: at first, form gate electrode by the photoetching first time, then metal level is leaked in successive sedimentation one deck gate insulation layer, active layer, ohmic contact layer and source on gate electrode.Then after the photoetching second time, form data wire, active area, source-drain electrode and TFT raceway groove figure by S/D wet etching, multistep etching (active layer etching → ashing (Ashing) → Mo dry etching → n+ etching).Deposit one deck passivation layer then, on passivation layer, form connecting hole by photoetching for the third time.Deposit the pixel electrode layer of layer of transparent at last and form pixel electrode by the 4th photoetching.
Although these four photoetching processes have obtained some progress with respect to five photoetching processes of tradition, but still there are several main shortcomings: the one, multistep etching technics complexity, development difficulty is big, and can produce some defectives inevitably, and is residual as metal M o, channel surface is coarse etc.The 2nd, the side direction etching that produces in the Mo dry etching will influence the breadth length ratio of raceway groove, cause the change of TFT electrology characteristic, and will be on the low side etc. as ON state current.
Summary of the invention
The present invention is directed to the defective of prior art, proposed a kind ofly to be equipped with active driving TFT matrix construction and manufacture method thereof, thereby shortened the production cycle of TFT matrix, reduced its production cost by four optical gravings.
To achieve these goals, the invention provides a kind of TFT matrix structure, comprising:
One substrate;
One grid line and with the gate electrode of its one, be formed on the described substrate, the top of grid line and gate electrode is coated with ground floor insulating barrier, semiconductor layer, ohmic contact layer successively;
One thin film transistor channel is formed on the ohmic contact layer on the described gate electrode;
One second layer gate insulation layer is formed on the described ohmic contact layer, and exposes thin film transistor channel and part ohmic contact layer at described thin film transistor channel and two side positions;
One data wire reaches the source electrode with its one, be formed on the top of described second layer insulating barrier, and the source electrode snaps into directly on the ohmic contact layer of described thin film transistor channel one side;
One drain electrode be formed on the top of described second layer insulating barrier, and drain electrode snaps into directly on the ohmic contact layer of described thin film transistor channel opposite side;
One passivation layer is formed on the top of described data wire, source electrode and drain electrode;
One pixel electrode is formed on described second insulating barrier, and partly overlaps with described drain electrode;
One groove is formed on the grid line between the described data wire, and described groove blocks the ohmic contact layer of grid line top and exposes the ground floor insulating barrier, and the top that described groove exposes first insulating barrier covers one deck pixel electrode material layer.
In the such scheme, described grid line, gate electrode, source electrode, data wire or the very monofilm of Cr, W, Ti, Ta, Mo, Al or Cu that leaks electricity perhaps are one of Cr, W, Ti, Ta, Mo, Al or Cu or composite membrane that combination in any constituted.Described ground floor insulating barrier, second layer gate insulation layer or passivation layer are oxide, nitride or oxynitrides.
To achieve these goals, the present invention provides a kind of manufacture method of TFT matrix structure simultaneously, comprising:
Step 1 on substrate, deposits grid metal level, ground floor insulating barrier, semiconductor layer and ohmic contact layer successively, adopts first mask, carries out mask, exposure and etching, forms grid line, gate electrode and thin film transistor channel part;
Step 2, deposition second layer gate insulation layer on the substrate of completing steps 1, adopt second mask, after carrying out mask, exposure and etching, part second layer gate insulation layer on the ohmic contact layer of thin film transistor channel top and both sides thereof is etched away, expose the ohmic contact layer of thin film transistor channel part level both sides; Simultaneously the part second layer insulating barrier on the grid line between neighbor is etched away, form a recess;
Step 4, deposit passivation layer on the substrate of completing steps 3, adopt the 4th mask, carry out forming the passivation layer figure after mask, exposure and the etching, wherein etching will etch away the passivation layer above the recess in the step 2 in this step, and continue the ohmic contact layer and the semiconductor layer of etching recess below, form a groove; Keep the photoresist on the passivation layer after etching is finished, then pixel deposition electrode material layer on passivation layer peels off photoresist and the pixel electrode material layer above the photoresist by chemical solution at last, forms pixel electrode.
In the such scheme, depositing grid metal level, ground floor insulating barrier, semiconductor layer and ohmic contact layer in the described step 1 successively is successive sedimentation.The mask that adopts in the described step 1 is the gray mask version, after the described gray mask version exposure, obtain photoresist unexposed area, photoresist partial exposure area and photoresist complete exposure area, wherein corresponding grid line and the gate electrode position of forming of photoresist unexposed area; The corresponding TFT raceway groove position that forms of photoresist partial exposure area; The corresponding other parts of photoresist complete exposure area.The etching of described step 1 is that grid metal level, ground floor insulating barrier, semiconductor layer and ohmic contact layer once form in the multistep etching.To carry out quarter when forming thin film transistor channel in the described step 1, the ohmic contact layer of channel region was etched away fully.
Compare with prior art, in the TFT matrix structure and manufacture method thereof that the present invention proposes, the formation of raceway groove only can be finished by ashing (Ashing) → ohmic contact layer etching, simplified the preparation process of TFT raceway groove greatly, simultaneously can obviously reduce various defectives such as raceway groove is residual, raceway groove short circuit, channel surface roughening, source-drain electrode short circuit (ESD) etc., improve the rate of finished products of TFT matrix.
Moreover what the present invention proposed forms the process of passivation layer and pixel electrode by a photoetching and stripping technology, simple and practical, has saved a large amount of chemical liquids simultaneously.
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
Description of drawings
Fig. 1 is the vertical view of TFT matrix unit structure of the present invention;
Fig. 2 is Figure 1A-A partial cross section figure;
Fig. 3 is Figure 1B-B partial cross section figure;
Fig. 4 is the sectional view of the present invention after carrying out successive sedimentation grid metal level, ground floor insulating barrier, semiconductor layer, ohmic contact layer on the substrate;
Fig. 5 is that the present invention adopts expose fully sectional view behind the grid metal level, ground floor insulating barrier, semiconductor layer, ohmic contact layer etching of corresponding region of photoresist in the gray mask version photoetching process;
Fig. 6 is that the present invention adopts partly expose sectional view after the ohmic contact layer etching of corresponding region of photoresist in the gray mask version photoetching process;
Fig. 7 is the present invention's sectional view of the present invention behind deposition second layer gate insulation layer on substrate, semiconductor layer, the ohmic contact layer;
Fig. 8 be the present invention by the second time chemical wet etching fall sectional view behind the second layer gate insulation layer on the part ohmic contact layer;
Fig. 9 is the sectional view after the present invention's photoetching for the third time forms source-drain electrode.
Mark among the figure: 21, substrate; 22, grid metal level; 22a, grid line; 22b, gate electrode; 23, ground floor insulating barrier; 24, semiconductor layer; 25, ohmic contact layer; 26, second layer insulating barrier; 27, metal level is leaked in the source; 27a, source electrode; 27b, drain electrode; 27c, data wire; 28, passivation layer; 29 pixel electrode material layers; 30, groove; 31, pixel electrode.
Embodiment
Fig. 1, Fig. 2 and Figure 3 shows that the structure of TFT matrix of the present invention.
As Fig. 1, Fig. 2 and shown in Figure 3, TFT matrix structure of the present invention comprises: substrate 21; Grid line 22a and with the gate electrode 22b of its one, be formed on the substrate 21; The top of grid line 22a and gate electrode 22b is coated with ground floor insulating barrier 23, semiconductor layer 24 and ohmic contact layer 25 successively; Thin film transistor channel is formed on the ohmic contact layer 25 on the gate electrode 22b; Second layer gate insulation layer 26 is formed on the ohmic contact layer 25, and exposes thin film transistor channel and part ohmic contact layer at thin film transistor channel and two side positions; Data wire 27c reaches the source electrode 27a with its one, form the top of second layer insulating barrier 26, and source electrode 27a snaps into directly on the ohmic contact layer 25 of thin film transistor channel one side; Drain electrode 27b be formed on the top of second layer insulating barrier 26, and drain electrode 27b snaps into directly on the ohmic contact layer 25 of thin film transistor channel opposite side; Passivation layer 28 is formed on the top of data wire 27c, source electrode 27a and drain electrode 27b etc.; Pixel electrode 31 is formed on second insulating barrier 26, and partly overlaps with drain electrode 27b; Groove 30 is formed on grid line 2 2a between the data wire 27c, and groove 30 blocks the ohmic contact layer 25 of grid line 22a top, and the top that groove 30 exposes ground floor insulating barrier 23 covers one deck pixel electrode material layer 29.
Fig. 4 to Figure 10 has provided the manufacture method that adopts four photolithographic fabrication TFT matrix structures of the present invention.
On substrate 21 (clear glass or quartz), the method for employing sputter or thermal evaporation deposition goes up thickness and is about 3600 grid metal level 22.The grid metal can be selected metal or their alloys such as Cr, W, Ti, Ta, Mo, Al, Cu for use, also can be satisfied the demand by the grid metal level of multiple layer metal or alloy composition.Then ground floor insulating barrier 23, the thickness that is about 4000 by PECVD method successive sedimentation thickness on grid metal level 22 is about the semiconductor layer 24 of 1800 and the ohmic contact layer 25 that thickness is about 500 , as shown in Figure 4.Ground floor insulating barrier 23 can be selected oxide, nitride or oxynitrides for use, and corresponding reacting gas can be SiH4, NH3 or N2, also or SiH2C12, NH3 or N2.The reacting gas of semiconductor layer 24 and ohmic contact layer 25 correspondences can be SiH4 and H2 or SiH2C12 and H2.
Adopt first mask, promptly gray mask version (Gray Tone mask) is carried out mask, exposure and etching.Wherein after the exposure, obtain photoresist unexposed area, photoresist partial exposure area (GrayTone) and photoresist complete exposure area, wherein photoresist unexposed area photoresist keeps fully, for keeping the photoresist zone fully, corresponding grid line and the gate electrode position of forming; Photoresist partial exposure area photoresist partly keeps, for part keeps the photoresist zone, and the corresponding TFT raceway groove position that forms; Photoresist complete exposure area part photoresist is removed fully, is no photoresist zone.
Adopt multistep to do the method for carving and etch away corresponding grid metal level 22, ground floor insulating barrier 23, semiconductor layer 24 and the ohmic contact layer 25 in no photoresist zone, form grid line 22a and gate electrode 22b, as shown in Figure 5.The etching gas of grid metal level 22 can be selected SF6/02 or C12/02 for use, and the etching gas of ground floor insulating barrier 23 can be selected SF6/02, C12/02 or HCl/02 for use, and the etching gas of semiconductive layer 24 and ohmic contact layer 25 can be selected gases such as SF6/C12 or SF6/HCl for use.
After multistep do to carve finishes, carry out photoresist ashing technology, mainly be in order to remove the photoresist of photoresist part reserve area, podzolic gas is chosen as SF6,02 or SF6/02 mist etc.At this moment, the photoresist of the complete reserve area of photoresist is also removed (thickness attenuation) by part.After ashing was finished, the ohmic contact layer 25 of photoresist part reserve area correspondence just was exposed, and then the ohmic contact layer that will expose by a step dry carving technology etches away, and forms the raceway groove of TFT, as shown in Figure 6.Etching gas is chosen as gases such as SF6/C12 or SF6/HCl.In order to guarantee that the ohmic contact layer of channel region is etched away fully, generally take the method for over etching.
After the raceway groove of TFT forms, be about the second layer gate insulation layer 26 of 2500 by Plasma Enhanced Chemical Vapor Deposition (PECVD) (PECVD) deposit thickness on substrate 21, ohmic contact layer 25 and the semiconductor layer that exposes, as shown in Figure 7.Second layer gate insulation layer 26 can be selected oxide, nitride or oxynitrides for use, and corresponding reacting gas can be SiH4, NH3 or N2, also or SiH2C12, NH3 or N2.
Adopt second normal masks version, carry out after mask, exposure and the etching with the part second layer gate insulation layer 26 on ohmic contact layer 25 and the thin film transistor channel, as shown in Figure 8.Lithographic method is a dry etching, and etching gas can be selected SF6/02, C12/02 or HCl/02 for use.Ohmic contact layer 25 and thin film transistor channel will come out like this.In this step etching, simultaneously the part second layer insulating barrier 26 on the grid line 22a between neighbor is etched away, on grid line, form a recess.
After second layer gate insulation layer 26 etchings are finished, be about the source leakage metal level 27 of 2200 by the last thickness of method deposition of sputter or thermal evaporation.Metal level is leaked in the source can select metal or their alloys such as Cr, W, Ti, Ta, Mo, Al, Cu for use, can be single or multiple lift on the structure.
Then adopt the 3rd mask, carry out forming source electrode 27a and drain electrode 27b after mask, exposure and the etching, as shown in Figure 9, the lithographic method of taking can be dry etching or wet etching, and wherein source electrode 27a and drain electrode 27b directly snap into respectively on the ohmic contact layer 25 on the gate electrode 22b.
After source electrode 27a and drain electrode 27b form, be about the passivation layer 28 of 2000 by PECVD method deposit thickness.Passivation layer 28 can be selected oxide, nitride or oxynitrides for use, and corresponding reacting gas can be SiH4, NH3 or N2, also or SiH2C12, NH3 or N2.Adopt the 4th mask then, carry out forming the passivation layer figure after mask, exposure and the etching, this moment, channel region was only covered by passivation layer 28.Wherein the passivation layer etching forms the passivation layer 28 of recess top after will etching away photoetching for the second time, and continues the ohmic contact layer 25 and the semiconductor layer 24 of this recess below of etching, forms groove 30.
After passivation layer 28 figures form, keep the photoresist on the passivation layer, method deposition by sputter or thermal evaporation goes up the transparent pixels electrode material layer 29 that thickness is about 400 , be generally ITO, at last peel off photoresist and the transparent conductive material layer above the photoresist by chemical solution, form pixel electrode 31, finish the making of film transistor matrix, as shown in Figure 2.Its further groove 30 tops keep transparent pixels electrode material layer 29, as shown in Figure 3.
Comprehensively above-mentioned, specific embodiment of the present invention is roughly as follows: gray mask version photoetching for the first time forms grid metal level, ground floor insulating barrier, active area (semiconductor layer and ohmic contact layer) and the channel part of TFT matrix.Wherein gate electrode, ground floor insulating barrier, active area figure form by a step etching technics, and the formation of raceway groove is finished by photoresist ashing (Ashing) → ohmic contact layer etching technics; Second layer gate insulation layer figure is finished in photoetching for the second time; Photoetching for the third time forms source-drain electrode; The 4th photoetching forms passivation layer and pixel electrode.
Therefore, in film transistor matrix structure of the present invention and the manufacture method, the formation of raceway groove only can be finished by photoresist ashing (Ashing) → ohmic contact layer etching, simplified the preparation process of TFT raceway groove greatly, simultaneously can obviously reduce various defectives such as raceway groove is residual, raceway groove short circuit, channel surface roughening, ESD etc., improve the rate of finished products of TFT matrix.
Simultaneously, what the present invention proposed forms the process of passivation layer and pixel electrode by a photoetching and stripping technology, simple and practical, has saved a large amount of chemical liquids simultaneously.
It should be noted that at last, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art should can use different materials and equipment to realize it as required, promptly can make amendment or be equal to replacement, and not break away from the spirit and scope of technical solution of the present invention technical scheme of the present invention.
Claims (8)
1. a TFT matrix structure is characterized in that, comprising:
One substrate;
One grid line and with the gate electrode of its one, be formed on the described substrate, the top of grid line and gate electrode is coated with ground floor insulating barrier, semiconductor layer, ohmic contact layer successively;
One thin film transistor channel is formed on the ohmic contact layer on the described gate electrode;
One second layer gate insulation layer is formed on the described ohmic contact layer, and exposes thin film transistor channel and part ohmic contact layer at described thin film transistor channel and two side positions;
One data wire reaches the source electrode with its one, be formed on the top of described second layer insulating barrier, and the source electrode snaps into directly on the ohmic contact layer of described thin film transistor channel one side;
One drain electrode be formed on the top of described second layer insulating barrier, and drain electrode snaps into directly on the ohmic contact layer of described thin film transistor channel opposite side;
One passivation layer is formed on the top of described data wire, source electrode and drain electrode;
One pixel electrode is formed on described second insulating barrier, and partly overlaps with described drain electrode;
One groove is formed on the grid line between the described data wire, and described groove blocks the ohmic contact layer of grid line top and exposes the ground floor insulating barrier, and the top that described groove exposes first insulating barrier covers one deck pixel electrode material layer.
2. matrix structure according to claim 1, it is characterized in that: described grid line, gate electrode, source electrode, data wire or the very monofilm of Cr, W, Ti, Ta, Mo, Al or Cu that leaks electricity perhaps are one of Cr, W, Ti, Ta, Mo, Al or Cu or composite membrane that combination in any constituted.
3. matrix structure according to claim 1 is characterized in that: described ground floor insulating barrier, second layer gate insulation layer or passivation layer are oxide, nitride or oxynitrides.
4. the manufacture method of a TFT matrix structure is characterized in that, comprising:
Step 1 on substrate, deposits grid metal level, ground floor insulating barrier, semiconductor layer and ohmic contact layer successively, adopts first mask, carries out mask, exposure and etching, forms grid line, gate electrode and thin film transistor channel part;
Step 2, deposition second layer gate insulation layer on the substrate of completing steps 1, adopt second mask, after carrying out mask, exposure and etching, part second layer gate insulation layer on the ohmic contact layer of thin film transistor channel top and both sides thereof is etched away, expose the ohmic contact layer of thin film transistor channel part level both sides; Simultaneously the part second layer insulating barrier on the grid line between neighbor is etched away, form a recess;
Step 3, sedimentary origin leaks metal level on the substrate of completing steps 2, adopt the 3rd mask, carry out forming source electrode and drain electrode after mask, exposure and the etching, wherein source electrode and drain electrode directly snap on the ohmic contact layer of thin film transistor channel both sides;
Step 4, deposit passivation layer on the substrate of completing steps 3, adopt the 4th mask, carry out forming the passivation layer figure after mask, exposure and the etching, wherein etching will etch away the passivation layer above the recess in the step 2 in this step, and continue the ohmic contact layer and the semiconductor layer of etching recess below, form a groove; Keep the photoresist on the passivation layer after etching is finished, then pixel deposition electrode material layer on passivation layer peels off photoresist and the pixel electrode material layer above the photoresist by chemical solution at last, forms pixel electrode.
5. manufacture method according to claim 4 is characterized in that: depositing grid metal level, ground floor insulating barrier, semiconductor layer and ohmic contact layer in the described step 1 successively is successive sedimentation.
6. manufacture method according to claim 4, it is characterized in that: the mask that adopts in the described step 1 is the gray mask version, after the described gray mask version exposure, obtain photoresist unexposed area, photoresist partial exposure area and photoresist complete exposure area, wherein corresponding grid line and the gate electrode position of forming of photoresist unexposed area; The corresponding TFT raceway groove position that forms of photoresist partial exposure area; The corresponding other parts of photoresist complete exposure area.
7. manufacture method according to claim 4 is characterized in that: the etching of described step 1 is that grid metal level, ground floor insulating barrier, semiconductor layer and ohmic contact layer once form in the multistep etching.
8. manufacture method according to claim 4 is characterized in that: will carry out quarter when forming thin film transistor channel in the described step 1, the ohmic contact layer of channel region is etched away fully.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
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| CNB200610152023XA CN100454559C (en) | 2006-09-11 | 2006-09-11 | TFT matrix structure and making method thereof |
| JP2007235757A JP4823989B2 (en) | 2006-09-11 | 2007-09-11 | TFT-LCD array substrate and manufacturing method thereof |
| KR1020070091891A KR100867866B1 (en) | 2006-09-11 | 2007-09-11 | Tft matrix structure and manufacturing method thereof |
| US11/853,297 US7636135B2 (en) | 2006-09-11 | 2007-09-11 | TFT-LCD array substrate and method for manufacturing the same |
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| CNB200610152023XA CN100454559C (en) | 2006-09-11 | 2006-09-11 | TFT matrix structure and making method thereof |
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| CN100454559C CN100454559C (en) | 2009-01-21 |
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| CN101794713A (en) * | 2010-03-18 | 2010-08-04 | 友达光电股份有限公司 | Thin film transistor and manufacturing method thereof |
| CN102945829A (en) * | 2012-11-23 | 2013-02-27 | 京东方科技集团股份有限公司 | Array substrate, manufacture method thereof and display device including array substrate |
| CN101527320B (en) * | 2007-12-03 | 2013-03-27 | 株式会社半导体能源研究所 | Semiconductor |
| CN104167418A (en) * | 2014-06-30 | 2014-11-26 | 厦门天马微电子有限公司 | Array substrate, manufacture method and liquid crystal display panel |
| CN106711231A (en) * | 2017-01-13 | 2017-05-24 | 京东方科技集团股份有限公司 | Thin film transistor, preparation method of thin film transistor, display substrate and preparation method of display substrate |
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| CN1230919C (en) * | 1994-06-02 | 2005-12-07 | 株式会社半导体能源研究所 | Active matrix display device and electrooptical element |
| GB2350467B (en) * | 1996-05-23 | 2001-04-11 | Lg Electronics Inc | Active matrix liquid crystal display and method of making same |
| JP3208658B2 (en) * | 1997-03-27 | 2001-09-17 | 株式会社アドバンスト・ディスプレイ | Manufacturing method of electro-optical element |
| JP3391343B2 (en) * | 1999-10-26 | 2003-03-31 | 日本電気株式会社 | Active matrix substrate and manufacturing method thereof |
| JP3617800B2 (en) * | 1999-12-28 | 2005-02-09 | 松下電器産業株式会社 | TFT array substrate and its manufacturing method Liquid crystal display device using the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101527320B (en) * | 2007-12-03 | 2013-03-27 | 株式会社半导体能源研究所 | Semiconductor |
| US8558236B2 (en) | 2007-12-03 | 2013-10-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| CN101794713A (en) * | 2010-03-18 | 2010-08-04 | 友达光电股份有限公司 | Thin film transistor and manufacturing method thereof |
| CN102945829A (en) * | 2012-11-23 | 2013-02-27 | 京东方科技集团股份有限公司 | Array substrate, manufacture method thereof and display device including array substrate |
| CN102945829B (en) * | 2012-11-23 | 2014-12-03 | 京东方科技集团股份有限公司 | Array substrate, manufacture method thereof and display device including array substrate |
| CN104167418A (en) * | 2014-06-30 | 2014-11-26 | 厦门天马微电子有限公司 | Array substrate, manufacture method and liquid crystal display panel |
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