CN101794159A - Band-gap reference voltage source of high power supply voltage rejection ratio - Google Patents

Abstract

The invention relates to a band-gap reference voltage source of high power supply voltage rejection ratio, comprising a start-up circuit (1), a positive and negative temperature coefficient current generation circuit (2), an operational amplifier (3) and a reference voltage generation circuit (4). The direct-current input ends of the start-up circuit (1), the positive and negative temperature coefficient current generation circuit (2), the operational amplifier (3) and the reference voltage generation circuit (4) are respectively connected with a direct-current power supply Vcc; the output end of the start-up circuit (1) is connected with a first input end of the positive and negative temperature coefficient current generation circuit (2); a first output end of the positive and negative temperature coefficient current generation circuit (2) is connected with a first input end of the operational amplifier (3); a second output end of the positive and negative temperature coefficient current generation circuit (2) is connected with a second input end of the operational amplifier (3); a third output end of the positive and negative temperature coefficient current generation circuit (2) is connected with a first input end of the reference voltage generation circuit (4); and the first output end of the operational amplifier (3) is connected with a second input end of the positive and negative temperature coefficient current generation circuit (2).

Description

A kind of bandgap voltage reference of high power supply voltage rejection ratio

Technical field

The present invention relates to be used for radio frequency, Digital Analog Hybrid Circuits and need the low-temperature coefficient that produces and the reference voltage source of high Power Supply Rejection Ratio.Along with the widespread use of SOC (SOC (system on a chip)), digital switch, the noise of radio-frequency module etc. can be coupled on the reference voltage source, makes traditional bandgap voltage reference more and more urgent to the requirement of high Power Supply Rejection Ratio.

Background technology

For mimic channels such as digital to analog converter, analog to digital converter, electric pressure converter, voltage detecting circuit, reference voltage source is considerable module, and the stability of reference voltage source is directly connected to the duty of circuit and the performance of circuit.In order to satisfy the operate as normal requirement of circuit under different external environments, reference voltage source should have advantages such as output is stable, antijamming capability is strong, temperature coefficient is little.Relatively more commonly used is bandgap voltage reference at present, adopts bipolar device to realize, output voltage values is substantially constant at (current-mode is 0.6V, and is bipolar) about 125V; Its principle of work is that the positive temperature coefficient (PTC) of Δ Vbe (voltage differences of two the base-launch sites of bipolar transistor under different current density biasings) and the drift that negative temperature coefficient produced of Vbe (bipolar transistor base-launch site voltage) are cancelled out each other.But, because along with further dwindling of size, the further reduction of supply voltage is after cascode structures such as (cascades) can't be used, make traditional bandgap voltage reference be difficult to that higher Power Supply Rejection Ratio is arranged again, and be vital for high-precision analog circuit power voltage rejection ratio.

Summary of the invention

Technical matters: the invention provides a kind of internal regulation of passing through, regulate making output voltage reach extremely a kind of bandgap voltage reference of high power supply voltage rejection ratio.Circuit has improved traditional amplifier on the basis of traditional bandgap voltage reference, the supply-voltage rejection ratio of the amplifier after the improvement can pass through internal regulation, it in the 0dB left and right adjusting, and had the disturbance rejection scope of broad for the steady state (SS) that obtains after the required supply-voltage rejection ratio.

Technical scheme: the bandgap voltage reference of a kind of high power supply voltage rejection ratio of the present invention comprises start-up circuit, Positive and Negative Coefficient Temperature current generating circuit, amplifier and reference voltage generating circuit; Start-up circuit, the Positive and Negative Coefficient Temperature current generating circuit, the direct current input end of amplifier and reference voltage generating circuit connects direct supply Vcc respectively, the first input end of the output termination Positive and Negative Coefficient Temperature current generating circuit of start-up circuit, first output terminal of Positive and Negative Coefficient Temperature current generating circuit links to each other with the first input end of amplifier, second output terminal of Positive and Negative Coefficient Temperature current generating circuit links to each other with second input end of amplifier, the 3rd output terminal of Positive and Negative Coefficient Temperature current generating circuit is connected with the first input end of reference voltage generating circuit, second input end of the first output termination Positive and Negative Coefficient Temperature current generating circuit of amplifier.

Described start-up circuit by a PMOS manage, the 2nd PMOS pipe forms with second resistance, the source electrode of the one PMOS pipe is as the direct current input end of start-up circuit, drain electrode links to each other with grid, the drain electrode of the 2nd PMOS pipe and second resistance, one end of the 2nd PMOS pipe respectively, the grid of the source electrode of the 2nd PMOS pipe and a PMOS pipe links to each other as the output terminal of start-up circuit, another termination common of second resistance.

In the described amplifier, the source electrode of 3aPMOS pipe, 3bPMOS pipe links to each other with the source electrode of 5a PMOS pipe, 5b PMOS pipe and as the direct current input end of amplifier, Vcc links to each other with direct supply; The grid of the drain electrode of the grid of 3bPMOS pipe and 2a NMOS pipe, the drain electrode of 4a PMOS pipe and 5a PMOS pipe continuous cropping altogether is the output terminal of amplifier; The drain electrode of the grid of 3a PMOS pipe and the drain electrode of 2b NMOS pipe, 4b PMOS pipe and the grid of 5b PMOS pipe and drain electrode connect altogether; The drain electrode of 5a PMOS pipe connects the source electrode of 4a PMOS pipe, the drain electrode of 3b PMOS pipe connects the source electrode of 4b PMOS pipe; The grid of 4a PMOS pipe and 4b PMOS pipe continuous cropping altogether is the 3rd input end of amplifier, and the grid of 2a NMOS pipe and 2b NMOS pipe continuous cropping altogether is the four-input terminal of amplifier; The drain electrode of 1aNMOS pipe connects the source electrode of 2a NMOS pipe, and the drain electrode of 1b NMOS pipe connects the source electrode of 2b NMOS pipe; The grid of 1b NMOS pipe is as the first input end of amplifier, and the grid of 1a NMOS pipe is as second input end of amplifier; The source electrode of 1a NMOS pipe, the source electrode of 1b NMOS pipe and the anode of the 5th resistance connect altogether; The other end of the 5th resistance connects and common.

Described reference voltage generating circuit is formed by connecting by 1 metal-oxide-semiconductor and two resistance; The grid of the 11 PMOS pipe is as the first input end of reference voltage generating circuit, source electrode is as the direct current input end of reference voltage generating circuit, drain electrode connects the anode of the 4th resistance, the other end of the 4th resistance links to each other as the reference voltage output end of reference voltage generating circuit with the anode of the 3rd resistance, and the other end of the 3rd resistance is connected with common.

This reference voltage source also comprises an adjustment module, and the input end of adjustment module is connected the 3rd output terminal of Positive and Negative Coefficient Temperature current generating circuit, and the voltage output end of adjustment module is connected the four-input terminal of amplifier.

Described adjustment module is made up of adjustable unit and the 6th PMOS pipe, one end of adjustable unit is connected with the drain electrode of the 6th PMOS pipe, and as the output terminal of adjustment module, the grid of the 6th PMOS pipe is as the input end of adjustment module, the source electrode of the 6th PMOS pipe is as the direct current input end of adjustment module, and the other end of adjustable unit is connected to common.Described adjustable unit adopts adjustable resistance to realize.

This reference voltage source also comprises a biasing circuit, and the input end of biasing circuit is connected the 3rd output terminal of Positive and Negative Coefficient Temperature current generating circuit, and the voltage output end of biasing circuit is connected the 3rd input end of amplifier.

Described biasing circuit is made up of the 7th PMOS pipe and the 12 NMOS pipe, the 13 NMOS pipe, the source electrode of the 7th PMOS pipe is as the direct current input end of biasing circuit, grid is as the input end of biasing circuit, drain electrode links to each other as the voltage output end of biasing circuit with the drain and gate of the 12 NMOS pipe, the drain and gate of the 13 NMOS pipe links to each other with the source electrode of the 12 NMOS pipe, and the source electrode of the 13 NMOS pipe is connected to common.

Beneficial effect:

1. circuit structure is simple, comprise start-up circuit, Positive and Negative Coefficient Temperature current generating circuit, amplifier and reference voltage generating circuit, the current mirror of Positive and Negative Coefficient Temperature current generating circuit all adopts the single tube coupling, and saved the cascade current-mirror structure of introducing in order to reach high supply-voltage rejection ratio, under low supply voltage (below the 1.2V), advantage is more obvious.

2. reference voltage source circuit of the present invention can be adjusted to optimum condition to the supply-voltage rejection ratio of benchmark output voltage as the case may be.According to the characteristics of this structure, can simply adjust the supply-voltage rejection ratio of amplifier itself by the outer regulator of sheet, just can make the supply-voltage rejection ratio of benchmark output voltage reach the high like this value of direct current 150dB.

3. the biasing circuit of reference voltage source circuit of the present invention is simple, if two PMOS pipes and a resistance, and when the circuit operate as normal, do not introduce extra electric current substantially, do not increase extra power consumption.

Description of drawings

Fig. 1 is a structured flowchart of the present invention.

Fig. 2 is a circuit diagram of the present invention.

Fig. 3 be the present invention under the different process angle, amplifier four-input terminal voltage changes the benchmark output voltage supply-voltage rejection ratio change curve that obtains from 550mV to 800mV.

Fig. 4 is the supply-voltage rejection ratio curve of the benchmark output voltage that obtains when getting desired value of amplifier four-input terminal voltage of the present invention.

Fig. 5 is the theory relation curve of amplifier supply-voltage rejection ratio of the present invention and regulatory factor.

Embodiment

The bandgap voltage reference of a kind of high power supply voltage rejection ratio of the present invention comprises start-up circuit, Positive and Negative Coefficient Temperature current generating circuit, amplifier and reference voltage generating circuit; Start-up circuit, the Positive and Negative Coefficient Temperature current generating circuit, the direct current input end of amplifier and reference voltage generating circuit connects direct supply Vcc respectively, the first input end of the output termination Positive and Negative Coefficient Temperature current generating circuit of start-up circuit, first output terminal of Positive and Negative Coefficient Temperature current generating circuit links to each other with the first input end of amplifier, its second output terminal links to each other with second input end of amplifier, the 3rd output terminal of Positive and Negative Coefficient Temperature current generating circuit is connected with the first input end of reference voltage generating circuit, and first output terminal of amplifier is connected with second input end of Positive and Negative Coefficient Temperature current generating circuit.Reference voltage generating circuit has reference voltage output end, output reference voltage.

In order to use of the requirement of various systems to reference voltage value, this circuit also comprises an adjustment module, the input end of adjustment module is connected the 3rd output terminal of Positive and Negative Coefficient Temperature current generating circuit, and the voltage output end of adjustment module is connected the four-input terminal of amplifier.This circuit also comprises a biasing circuit, and the input end of biasing circuit is connected the 3rd output terminal of Positive and Negative Coefficient Temperature current generating circuit, and the voltage output end of biasing circuit is connected the 3rd input end of amplifier.

Principle of the present invention:

Fig. 1 has provided the structural principle block diagram of the reference voltage source circuit of being invented, and Fig. 2 has provided the circuit diagram of the reference voltage source circuit of being invented.How this circuit structure of narration improves the principle of work of supply-voltage rejection ratio below.

At first, as follows to some parameter-definitions of using on the formula in the analytic process: PSRRamp is the supply-voltage rejection ratio vout/vdd of amplifier 3, and wherein vout is the output terminal of amplifier 3; Av is the dc open-loop gain of amplifier 3; VP is the PMOS pipe M9 in the Positive and Negative Coefficient Temperature current generating circuit 2, the grid voltage of M8; V1 is the drain voltage of the PMOS pipe M8 in the Positive and Negative Coefficient Temperature current generating circuit 2; V2 is the drain voltage of the PMOS pipe M9 in the Positive and Negative Coefficient Temperature current generating circuit 2; Ro is the PMOS pipe M9 in the Positive and Negative Coefficient Temperature current generating circuit 2, the output impedance of the PMOS pipe M11 in M8 and the reference voltage generating circuit 4, and process can be similar to these three pipes according to side circuit and have identical output impedance to simplify the analysis.Gm is the PMOS pipe M9 in the Positive and Negative Coefficient Temperature current generating circuit 2, the mutual conductance of the PMOS pipe M11 in M8 and the reference voltage generating circuit 4, and process can be similar to these three pipes according to side circuit and have identical mutual conductance to simplify the analysis.R1 is the impedance of the drain electrode of the PMOS pipe M8 in the Positive and Negative Coefficient Temperature current generating circuit 2 to ground; R2 is the impedance of the drain electrode of the PMOS pipe M9 in the Positive and Negative Coefficient Temperature current generating circuit 2 to ground; R3 is the impedance of the drain electrode of the PMOS pipe M11 in the reference voltage generating circuit 4 to ground; Below (be analysis based on small-signal model.

Three supply voltages mentioning in the course of work of circuit of the present invention are to the approach that influences of benchmark output voltage values, first, PMOS pipe M8 by Positive and Negative Coefficient Temperature current generating circuit 2, amplification in the same way by amplifier 3 after the source electrode of M9 enters and amplifies is managed on the grid of M11 at the PMOS of reference voltage generating circuit 4, reverse amplification by the PMOS pipe is on voltage output end VREF, and what produce by this approach is the ripple reverse with mains voltage ripple.The ripple of supposing supply voltage is vdd, acts on the V1, and the change in voltage of V1 is v1, can be formulated as:

$v1=-\mathrm{vp}\&CenterDot;\mathrm{gm}\&CenterDot;\mathrm{<figure-callout\; id="1"\; label="r"\; filenames="HSA00000050149300011.png,HSA00000050149300031.png"\; state="\{\{state\}\}">r</figure-callout>}1+\frac{\mathrm{vdd}\&CenterDot;(\mathrm{gm}\&CenterDot;\mathrm{ro}+1)\&CenterDot;r1}{(\mathrm{ro}+r1)}---\left(1\right)$

Act on simultaneously on the V2, the change in voltage of V2 is v2, can be formulated as:

$\mathrm{<figure-callout\; id="2"\; label="v"\; filenames="HSA00000050149300011.png,HSA00000050149300031.png"\; state="\{\{state\}\}">v</figure-callout>}2=-\mathrm{vp}\&CenterDot;\mathrm{gm}\&CenterDot;\mathrm{<figure-callout\; id="2"\; label="r"\; filenames="HSA00000050149300011.png,HSA00000050149300031.png"\; state="\{\{state\}\}">r</figure-callout>}2+\frac{\mathrm{vdd}\&CenterDot;(\mathrm{gm}\&CenterDot;\mathrm{ro}+1)\&CenterDot;r2}{(\mathrm{ro}+r2)}---\left(2\right)$

Voltage signal v1 then, v2 affacts again on the VP by amplifier 3, and the voltage signal that changes on VP that has this approach to cause is vp1, can be formulated as:

vp1＝A _v·(v1-v2) (3)

The second, be that vdd passes through amplifier (3) separately from PMOS pipe M3, the voltage signal that M5 enters on the VP is vp2, can be formulated as:

vp2＝PSRRamp·vdd (4)

So total voltage signal that changes on VP is vp, is formulated as:

vp＝PSRRamp·vdd+A _v·(v1-v2) (5)

The 3rd, after entering and be exaggerated, source end by PMOS pipe M11 acts on the voltage output end VREF, act on voltage change signal on the voltage output end VREF being superimposed with grid from the PMOS pipe M11 of top two approach by reference voltage generating circuit 4, obtain total voltage change signal vref, can be formulated as:

$\mathrm{vref}=-\mathrm{vp}\&CenterDot;\mathrm{gm}\&CenterDot;v3+\frac{\mathrm{vdd}\&CenterDot;(\mathrm{gm}\&CenterDot;\mathrm{ro}+1)\&CenterDot;r3}{(\mathrm{ro}+r3)}---\left(6\right)$

Simultaneous formula (1), (2), (5), (6), and be realistic hypothesis ro much larger than r1, r2, and r3 can obtain following result:

$\frac{\mathrm{vref}}{\mathrm{vdd}}=\frac{\mathrm{gm}\&CenterDot;\mathrm{ro}\&CenterDot;r3+r3-\mathrm{gm}\&CenterDot;\mathrm{ro}\&CenterDot;r3\&CenterDot;\mathrm{PSRRamp}}{\mathrm{ro}\&CenterDot;(1+A_v\&CenterDot;\mathrm{gm}\&CenterDot;(r1-r2))}---\left(7\right)$

From formula (7) as can be seen, suppress ability, must make in order to reach high supply voltage

Near 0, the supply-voltage rejection ratio of amplifier 3 should be approaching as far as possible for this reason as far as possible

According to above analysis, the supply-voltage rejection ratio of the amplifier 3 shown in the figure (2) just has characteristics like this, before analyzing the amplifier supply-voltage rejection ratio, as follows to some parameter-definitions of using on the formula in the analytic process: ro1 is that the grid of supposition M3a exchanges ground and in the drain electrode of M4a, the grid of M5a and the drain electrode of M3a, when the drain electrode of M2a disconnects, the output impedance of seeing into from the drain electrode of M3a; In like manner, ro2 is the output impedance of seeing into from the drain electrode of M4b; The mutual conductance that the present invention chooses the PMOS pipe is 2 * gm5a=2 * gm3b=gm3a=gm5b.The analytical approach of similar benchmark output voltage supply-voltage rejection ratio, the PSRRamp that can draw amplifier 3 is:

$\mathrm{PSRRamp}=\frac{\frac{k\&CenterDot;\mathrm{gm}5a\&CenterDot;\mathrm{ro}1}{k\&CenterDot;\mathrm{gm}5a\&CenterDot;\mathrm{<figure-callout\; id="1"\; label="ro"\; filenames="HSA00000050149300011.png,HSA00000050149300031.png"\; state="\{\{state\}\}">ro</figure-callout>}1+1}+\frac{\mathrm{gm}3a\&CenterDot;\mathrm{<figure-callout\; id="1"\; label="ro"\; filenames="HSA00000050149300011.png,HSA00000050149300031.png"\; state="\{\{state\}\}">ro</figure-callout>}1}{\mathrm{gm}3a\&CenterDot;\mathrm{<figure-callout\; id="1"\; label="ro"\; filenames="HSA00000050149300011.png,HSA00000050149300031.png"\; state="\{\{state\}\}">ro</figure-callout>}1+1}\frac{\mathrm{gm}3a\&CenterDot;\mathrm{rol}}{\mathrm{gm}5a\&CenterDot;\mathrm{<figure-callout\; id="1"\; label="ro"\; filenames="HSA00000050149300011.png,HSA00000050149300031.png"\; state="\{\{state\}\}">ro</figure-callout>}1+1}\&CenterDot;\frac{\mathrm{gm}3b\&CenterDot;\mathrm{<figure-callout\; id="2"\; label="ro"\; filenames="HSA00000050149300011.png,HSA00000050149300031.png"\; state="\{\{state\}\}">ro</figure-callout>}2}{\mathrm{gm}5b\&CenterDot;\mathrm{<figure-callout\; id="2"\; label="ro"\; filenames="HSA00000050149300011.png,HSA00000050149300031.png"\; state="\{\{state\}\}">ro</figure-callout>}2+1}\frac{\mathrm{gm}3a\&CenterDot;\mathrm{rol}}{\mathrm{gm}5a\&CenterDot;\mathrm{<figure-callout\; id="1"\; label="ro"\; filenames="HSA00000050149300011.png,HSA00000050149300031.png"\; state="\{\{state\}\}">ro</figure-callout>}1+1}\&CenterDot;\frac{\mathrm{gm}5b\&CenterDot;\mathrm{<figure-callout\; id="2"\; label="ro"\; filenames="HSA00000050149300011.png,HSA00000050149300031.png"\; state="\{\{state\}\}">ro</figure-callout>}2}{\mathrm{gm}5b\&CenterDot;\mathrm{<figure-callout\; id="2"\; label="ro"\; filenames="HSA00000050149300011.png,HSA00000050149300031.png"\; state="\{\{state\}\}">ro</figure-callout>}2+1}}{1-\frac{\mathrm{gm}3a\&CenterDot;\mathrm{rol}}{\mathrm{gm}5a\&CenterDot;\mathrm{<figure-callout\; id="1"\; label="ro"\; filenames="HSA00000050149300011.png,HSA00000050149300031.png"\; state="\{\{state\}\}">ro</figure-callout>}1+1}\&CenterDot;\frac{\mathrm{gm}3b\&CenterDot;\mathrm{<figure-callout\; id="2"\; label="ro"\; filenames="HSA00000050149300011.png,HSA00000050149300031.png"\; state="\{\{state\}\}">ro</figure-callout>}2}{\mathrm{gm}5b\&CenterDot;\mathrm{<figure-callout\; id="2"\; label="ro"\; filenames="HSA00000050149300011.png,HSA00000050149300031.png"\; state="\{\{state\}\}">ro</figure-callout>}2+1}}---\left(8\right)$

Wherein k is the regulatory factor of the grid introducing of M4a and M4b.The relation curve that calculates PSRRamp and regulatory factor k by matlab as shown in Figure 5, more identical with side circuit, and satisfied the condition of the supply-voltage rejection ratio of above amplifier 3, so far, analysis draws side circuit by internal regulation, can obtain theoretical optimal power supply voltage fully and suppress ability.

When the present invention works, can simultaneously, can obtain the output voltage values of less temperature coefficient by regulating the output voltage values that obtains high supply-voltage rejection ratio.Below by specific embodiments of the invention also in conjunction with the accompanying drawings, purpose of the present invention, circuit structure and advantage are further described.

A kind of bandgap voltage reference of high power supply voltage rejection ratio, as shown in Figure 1, reference voltage source circuit comprises and is used for making reference circuit to break away from zero stable state, changes the start-up circuit 1 of normal operating conditions over to, Positive and Negative Coefficient Temperature current generating circuit 2, amplifier 3 and reference voltage generating circuit 4; Start-up circuit 1, Positive and Negative Coefficient Temperature current generating circuit 2, the direct current input end of amplifier 3 and reference voltage generating circuit 4 connects direct supply Vdd respectively, the first input end of the output termination Positive and Negative Coefficient Temperature current generating circuit 2 of start-up circuit 1, first output terminal of Positive and Negative Coefficient Temperature current generating circuit 2 links to each other with the first input end of amplifier 3, its second output terminal links to each other with second input end of amplifier 3, the 3rd output terminal of Positive and Negative Coefficient Temperature current generating circuit 2 is connected with the first input end of reference voltage generating circuit 4, and first output terminal of amplifier 3 is connected with second input end of Positive and Negative Coefficient Temperature current generating circuit 2.Reference voltage generating circuit 4 has reference voltage output end, output reference voltage.

Wherein, as shown in Figure 2, described start-up circuit 1 is made up of PMOS pipe P1, the 2nd PMOS pipe P2 and second resistance R 2, the source electrode of the one PMOS pipe P1 is as the direct current input end of start-up circuit 1, drain electrode links to each other with grid, the P2 drain electrode of the 2nd PMOS pipe and second resistance R, 2 one ends of the 2nd PMOS pipe P2 respectively, the source electrode of the 2nd PMOS pipe P2 links to each other as the output terminal of start-up circuit 1 another termination common of second resistance R 2 with the grid of PMOS pipe P1.

Described Positive and Negative Coefficient Temperature current generating circuit 2 is made up of the 8th metal-oxide-semiconductor M8, the 9th metal-oxide-semiconductor M9, the 0th resistance R 0,1a resistance R 1a, 1b resistance R 1b, the first bipolar transistor B0 and the second bipolar transistor B1; The source electrode of the 8th metal-oxide-semiconductor M8, the 9th metal-oxide-semiconductor M9 links to each other and as the direct current input end of Positive and Negative Coefficient Temperature current generating circuit 2, Vcc links to each other with direct supply, and the drain electrode of the 8th metal-oxide-semiconductor M8 links to each other with the anode of the 0th resistance R 0,1b resistance R 1b and as first output terminal of Positive and Negative Coefficient Temperature current generating circuit 2; The drain electrode of the 9th metal-oxide-semiconductor M9 links to each other with the collector of 1a resistance R 1a, the first bipolar transistor B0 and as second output terminal of Positive and Negative Coefficient Temperature current generating circuit 2; The other end of the 0th resistance R 0 links to each other with the collector of the second bipolar transistor B1.The grid of the 8th metal-oxide-semiconductor M8, the 9th metal-oxide-semiconductor M9 links to each other and as the 3rd output terminal of Positive and Negative Coefficient Temperature current generating circuit 2, simultaneously also as first input end; The base stage of the first bipolar transistor B0 and the second bipolar transistor B1 links to each other also and the emitter-base bandgap grading of the first bipolar transistor B0 and the second bipolar transistor B1 connects common altogether.

In the described amplifier 3, the source electrode of 3a PMOS pipe M3a, 3b PMOS pipe M3b links to each other with the source electrode of 5aPMOS pipe M5a, 5b PMOS pipe M5b and as the direct current input end of amplifier 3, Vcc links to each other with direct supply; The grid of the drain electrode of the drain electrode of the grid of 3b PMOS pipe M3b and 2aNMOS pipe M2a, 4a PMOS pipe M4a and 5a PMOS pipe M5a continuous cropping altogether is first output terminal of amplifier 3; Grid and the drain electrode of the drain electrode of the drain electrode of the grid of 3a PMOS pipe M3a and 2b NMOS pipe M2b, 4b PMOS pipe M4b and 5b PMOS pipe M5b connect altogether; The drain electrode of 5a PMOS pipe MSa connects the source electrode of 4a PMOS pipe M4a, the drain electrode of 3b PMOS pipe M3b connects the source electrode of 4b PMOS pipe M4b; The grid of 4aPMOS pipe M4a and 4b PMOS pipe M4b continuous cropping altogether is the 3rd input end of amplifier 3, and the grid of 2a NMOS pipe M2a and 2b NMOS pipe M2b continuous cropping altogether is the four-input terminal of amplifier 3; The drain electrode of 1a NMOS pipe M1a connects the source electrode of 2a NMOS pipe M2a, and the drain electrode of 1b NMOS pipe M1b connects the source electrode of 2bNMOS pipe M2b; The grid of 1bNMOS pipe M1b is as the first input end of amplifier 3, and the grid of 1a NMOS pipe M1a is as second input end of amplifier 3; The source electrode of the source electrode of 1aNMOS pipe M1a, 1b NMOS pipe M1b and the anode of the 5th resistance R 5 connect altogether; The other end of the 5th resistance R 5 connects and common.

Described reference voltage generating circuit 4 is formed by connecting by 1 metal-oxide-semiconductor and two resistance; The grid of the 11 PMOS pipe M11 is as the first input end of reference voltage generating circuit 4, source electrode is as the direct current input end of reference voltage generating circuit 4, drain electrode connects the anode of the 4th resistance R 4, the other end of the 4th resistance R 4 links to each other as the reference voltage output end of reference voltage generating circuit 4 with the anode of the 3rd resistance R 3, and the other end of the 3rd resistance R 3 is connected with common.

In order to make actual chips can obtain optimal power supply voltage rejection ratio, this reference voltage source also comprises an adjustment module 5, the input end of adjustment module 5 is connected the 3rd output terminal of Positive and Negative Coefficient Temperature current generating circuit 2, and the voltage output end of adjustment module 5 is connected the four-input terminal of amplifier 3.

Described adjustment module 5 is made up of adjustable unit R M and the 6th PMOS pipe M6, the end of adjustable unit R M is connected with the drain electrode of the 6th PMOS pipe M6, and as the output terminal of adjustment module 5, the grid of the 6th PMOS pipe M6 is as the input end of adjustment module 5, the source electrode of the 6th PMOS pipe M6 is as the direct current input end of adjustment module 5, and the other end of adjustable unit R M is connected to common.Described adjustable unit R M adopts adjustable resistance to realize.

In order to make amplifier 3 energy operate as normal, and bigger gain is arranged, this reference voltage source also comprises a biasing circuit 6, and the input end of biasing circuit 6 is connected the 3rd output terminal of Positive and Negative Coefficient Temperature current generating circuit 2, and the voltage output end of biasing circuit 6 is connected the 3rd input end of amplifier 3.

Described biasing circuit 6 is made up of the 7th PMOS pipe M7 and the 12 NMOS pipe M12, the 13 NMOS pipe M13, the source electrode of the 7th PMOS pipe M7 is as the direct current input end of biasing circuit 6, grid is as the input end of biasing circuit 6, drain electrode links to each other as the voltage output end of biasing circuit 6 with the drain and gate of the 12 NMOS pipe M12, the drain and gate of the 13 NMOS pipe M13 links to each other with the source electrode of the 12 NMOS pipe M12, and the source electrode of the 13 NMOS pipe M13 is connected to common.

Referring to Fig. 3, shown in the figure for the present invention under the different process angle, amplifier four-input terminal voltage changes the benchmark output voltage supply-voltage rejection ratio change curve that obtains from 550mV to 800mV.By curve map as can be seen, under various process corner, the optimal power supply voltage rejection ratio of regulating the generation of adjustable unit has skew; We are also as can be seen under the different process angle, though optimal power supply voltage rejection ratio scope can be offset, do not surpass the range of adjustment of adjustable unit, that is to say, but actual conditions how, and I can obtain the optimal power supply voltage rejection ratio of this moment by the adjusting of adjustable unit; And its characteristic of chip of general same batch has similarity, so, as long as regulated wherein chip piece.

Referring to Fig. 4,, the supply-voltage rejection ratio curve of the benchmark output voltage that obtains when getting desired value for amplifier four-input terminal voltage of the present invention shown in the figure.By curve map as can be seen, the supply-voltage rejection ratio of the benchmark output voltage values that obtains after regulating by regulon, its direct supply voltage rejection ratio has reached 158dB.

The course of work of circuit of the present invention:

Behind energized voltage Vdd, start-up circuit 1 work that takes the lead in, because the grid of PMOS pipe P1 is to be in noble potential, so PMOS pipe P2 conducting, at this moment the grid current potential of PMOS pipe P1 is dragged down, thereby make the PMOS pipe M9 in the Positive and Negative Coefficient Temperature current generating circuit 2, M8 opens and produces electric current, PMOS manages M8, electric current on the M9 drives amplifier 3 again and is able to operate as normal, the effect of amplifier 3 be PMOS is managed M8 and M9 by feedback the drain voltage clamper at the voltage that equates because the area of B0 and B1 is different, the base stage of BJT is also different to the voltage VBE of emitter-base bandgap grading, on resistance R 0, just produce the voltage of a Δ VBE, this voltage has the basic positive temperature coefficient that is, the result produces the electric current that a brace has positive temperature coefficient (PTC) on resistance R 0.Simultaneously, because VBE itself has negative temperature coefficient, on resistance R 1a and R1b, produce the electric current that a brace has negative temperature coefficient.Manage M11 by the 3rd output terminal mirror image of Positive and Negative Coefficient Temperature current generating circuit 2 to PMOS after these two electric current stacks, these two electric currents that have Positive and Negative Coefficient Temperature respectively form a benchmark output voltage with single order temperature compensation on R3.

In above groundwork process, the present invention makes the benchmark output voltage values reach high supply-voltage rejection ratio by following process: when supply voltage has low-frequency ripple, this ripple has three approach to influence reference voltage output, at first, act on the voltage output end VREF after source end by PMOS pipe M11 enters and is exaggerated, and be and mains voltage ripple ripple in the same way by what this approach produced; Secondly, PMOS pipe M8 by Positive and Negative Coefficient Temperature current generating circuit 2, amplification in the same way by amplifier 3 after the source electrode of M9 enters and amplifies is managed on the grid of M11 at the PMOS of reference voltage generating circuit 4, reverse amplification by the PMOS pipe is on voltage output end VREF, and what produce by this approach is the ripple reverse with mains voltage ripple; Traditional has often only just finished the inhibiting effect of benchmark to mains voltage ripple with the stack of these two kinds of effects.The present invention on this basis, the characteristics that its supply-voltage rejection ratio of amplifier after utilize improving can be finely tuned up and down at 0dB, make PMOS pipe M3 by amplifier 3, the ripple that M5 introduces also is added on the voltage output end VREF of benchmark, thereby reaches the high inhibition ability of reference source to supply voltage.Wherein the PMOS in the amplifier 3 manages M4a, and M4b has played the function of the supply-voltage rejection ratio of fine setting amplifier 3.

Claims (9)

1. the bandgap voltage reference of a high power supply voltage rejection ratio is characterized in that this power supply comprises start-up circuit (1), Positive and Negative Coefficient Temperature current generating circuit (2), amplifier (3) and reference voltage generating circuit (4); Start-up circuit (1), Positive and Negative Coefficient Temperature current generating circuit (2), the direct current input end of amplifier (3) and reference voltage generating circuit (4) connects direct supply Vcc respectively, the first input end of the output termination Positive and Negative Coefficient Temperature current generating circuit (2) of start-up circuit (1), first output terminal of Positive and Negative Coefficient Temperature current generating circuit (2) links to each other with the first input end of amplifier (3), second output terminal of Positive and Negative Coefficient Temperature current generating circuit (2) links to each other with second input end of amplifier (3), the 3rd output terminal of Positive and Negative Coefficient Temperature current generating circuit (2) is connected with the first input end of reference voltage generating circuit (4), second input end of the first output termination Positive and Negative Coefficient Temperature current generating circuit (2) of amplifier (3).

2. the bandgap voltage reference of a kind of high power supply voltage rejection ratio according to claim 1, it is characterized in that: described start-up circuit (1) is by PMOS pipe (P1), the 2nd PMOS pipe (P2) is formed with second resistance (R2), the source electrode of the one PMOS pipe (P1) is as the direct current input end of start-up circuit (1), the grid of (P2) is managed in drain electrode respectively with the 2nd PMOS, the 2nd PMOS pipe (P2) drain electrode and second resistance (R2) end link to each other, the source electrode of the 2nd PMOS pipe (P2) links to each other as the output terminal of start-up circuit (1) another termination common of second resistance (R2) with the grid that a PMOS manages (P1).

3. the bandgap voltage reference of a kind of high power supply voltage rejection ratio according to claim 1, it is characterized in that in the described amplifier (3), the source electrode that the source electrode of 3a PMOS pipe (M3a), 3b PMOS pipe (M3b) and 5a PMOS pipe (M5a), 5b PMOS manage (M5b) links to each other and as the direct current input end of amplifier (3), Vcc links to each other with direct supply; The grid of the drain electrode of the drain electrode of the grid of 3b PMOS pipe (M3b) and 2a NMOS pipe (M2a), 4a PMOS pipe (M4a) and 5a PMOS pipe (M5a) continuous cropping altogether is first output terminal of amplifier (3); The grid of the drain electrode of the drain electrode of the grid of 3a PMOS pipe (M3a) and 2b NMOS pipe (M2b), 4b PMOS pipe (M4b) and 5bPMOS pipe (M5b) and drain electrode connect altogether; The drain electrode of 5a PMOS pipe (M5a) connects the source electrode of 4a PMOS pipe (M4a), the drain electrode of 3b PMOS pipe (M3b) connects the source electrode of 4b PMOS pipe (M4b); The grid of 4a PMOS pipe (M4a) and 4b PMOS pipe (M4b) continuous cropping altogether is the 3rd input end of amplifier (3), and the grid of 2a NMOS pipe (M2a) and 2b NMOS pipe (M2b) continuous cropping altogether is the four-input terminal of amplifier (3); The drain electrode of 1aNMOS pipe (M1a) connects the source electrode of 2aNMOS pipe (M2a), and the drain electrode of 1bNMOS pipe (M1b) connects the source electrode of 2b NMOS pipe (M2b); The grid of 1b NMOS pipe (M1b) is as the first input end of amplifier (3), and the grid of 1a NMOS pipe (M1a) is as second input end of amplifier (3); The source electrode of the source electrode of 1a NMOS pipe (M1a), 1b NMOS pipe (M1b) and the anode of the 5th resistance (R5) connect altogether; The other end of the 5th resistance (R5) connects and common.

4. the bandgap voltage reference of a kind of high power supply voltage rejection ratio according to claim 1 is characterized in that: described reference voltage generating circuit (4) is formed by connecting by 1 metal-oxide-semiconductor and two resistance; The grid of the 11 PMOS pipe (M11) is as the first input end of reference voltage generating circuit (4), source electrode is as the direct current input end of reference voltage generating circuit (4), drain electrode connects the anode of the 4th resistance (R4), the other end of the 4th resistance (R4) links to each other as the reference voltage output end of reference voltage generating circuit (4) with the anode of the 3rd resistance (R3), and the other end of the 3rd resistance (R3) is connected with common.

5. the bandgap voltage reference of a kind of high power supply voltage rejection ratio according to claim 1, it is characterized in that this reference voltage source also comprises an adjustment module (5), the input end of adjustment module (5) is connected the 3rd output terminal of Positive and Negative Coefficient Temperature current generating circuit (2), and the voltage output end of adjustment module (5) is connected the four-input terminal of amplifier (3).

6. the bandgap voltage reference of a kind of high power supply voltage rejection ratio according to claim 5, it is characterized in that: described adjustment module (5) is made up of adjustable unit (RM) and the 6th PMOS pipe (M6), one end of adjustable unit (RM) is connected with the drain electrode that the 6th PMOS manages (M6), and as the output terminal of adjustment module (5), the grid of the 6th PMOS pipe (M6) is as the input end of adjustment module (5), the source electrode of the 6th PMOS pipe (M6) is as the direct current input end of adjustment module (5), and the other end of adjustable unit (RM) is connected to common.

7. the bandgap voltage reference of a kind of high power supply voltage rejection ratio according to claim 6 is characterized in that: described adjustable unit (RM) adopts adjustable resistance to realize.

8. a kind of according to claim 1 or 5 bandgap voltage reference of high power supply voltage rejection ratio, it is characterized in that this reference voltage source also comprises a biasing circuit (6), the input end of biasing circuit (6) is connected the 3rd output terminal of Positive and Negative Coefficient Temperature current generating circuit (2), and the voltage output end of biasing circuit (6) is connected the 3rd input end of amplifier (3).

9. the bandgap voltage reference of a kind of high power supply voltage rejection ratio according to claim 8, it is characterized in that described biasing circuit (6) is by the 7th PMOS pipe (M7) and the 12 NMOS pipe (M12), the 13 NMOS pipe (M13) is formed, the source electrode of the 7th PMOS pipe (M7) is as the direct current input end of biasing circuit (6), grid is as the input end of biasing circuit (6), drain electrode links to each other as the voltage output end of biasing circuit (6) with the drain and gate of the 12 NMOS pipe (M12), the drain and gate of the 13 NMOS pipe (M13) links to each other with the source electrode of the 12 NMOS pipe (M12), and the source electrode of the 13 NMOS pipe (M13) is connected to common.

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