CN101789044A - Method of implementing cooperative work of software and hardware of genetic algorithm - Google Patents
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Abstract
The invention provides a method of implementing cooperative work of software and hardware of a genetic algorithm. The genetic algorithm is a typical evolution algorithm, however, due to the characteristic of binary coding, the genetic algorithm implemented by using the software has low efficiency in solving practical problems; and although the hardware FPGA can improve the solving speed, the hardware structure is not easily changed and lacks of flexibility once the pure hardware is implemented. The invention proposes a cooperative design method of the software and the hardware of the genetic algorithm aiming at the shortcomings of the implementation of the software and the hardware, the operating speed can be improved, the generality of the IP core of the genetic algorithm can be improved as well, and the similar problems can be solved only by rewriting the fitness function on a software layer. Compared with the implementation of the pure software and the pure hardware, the working platform with the cooperative software and the hardware has higher efficiency and wider generality in solving the problems by using the method of cooperative software and the hardware.
Description
Technical field
The present invention relates to intelligence computation and software-hardware synergism technology, particularly a kind of technology of using software-hardware synergism to handle genetic algorithm.
Background technology
Genetic algorithm (Genetic Algorithm, GA) be a kind of probabilistic search algorithm that Holland proposed in " Adaptation in Natural andArtificial System " first in 1975, yet genetic algorithm is by in an organized way being that message exchange randomly comes the good string of those adaptability of recombination, in each generation, utilize good position of adaptability in the previous generation string and section to generate the colony of a new string, as extra interpolation, also in string structure, attempt once in a while substituting original part with new position and section.Be similar to nature and evolve, genetic algorithm is sought good chromosome and is found the solution problem by acting on the gene on the chromosome.Because it is not subjected to the constraint of the restricted assumed condition in search volume, needn't require such as hypothesis such as continuity, differentiability and unimodality, with and intrinsic concurrency, therefore be widely used in every field as a kind of sane, efficient optimization algorithm.
And present genetic algorithm all is to be realized by pure hardware or pure software, realizes that by software the operation efficiency of algorithm is low.And realize by pure hardware, can only find the solution at certain problem, do not accomplish versatility.These two kinds of implementation methods all have its defective separately, are badly in need of the defective that a kind of feasible integrated technology method can be improved above-mentioned technology at present.
The thought of software-hardware synergism design (Hardware/Software Co-designing) is to utilize it to act synergistically to greatest extent to the greatest extent in the hardware and software design process to satisfy the requirement of system.After software-hardware synergism thought proposes, enjoy domestic and international researcher's concern always, also very active about the research of software-hardware synergism design field.Up to the present, Chinese scholars had been done a lot of researchs in this regard, such as real time effect at remote sensing image, the audio coding algorithm, the Lattice decoding algorithm, digital circuit simulation, software and hardware cooperating design method was all used in some aspects such as the simulation of system, emulation and debugging, and obtained than using traditional better effect of method for designing.Therefore utilize software and hardware cooperating design method not only can improve the efficient of the problem of finding the solution, can widen its application simultaneously, further promote the development of software-hardware synergism design etc.
Summary of the invention
The objective of the invention is to, utilize the mode of cooperative work of software and hardware that a kind of implementation method of genetic algorithm is provided, the calculated performance of algorithm is promoted significantly, and increase the versatility of calculating.
The cooperative work of software and hardware implementation method of genetic algorithm provided by the present invention, based on the following each several part of FPGA Platform Implementation,
(1) at hardware view, set up hardware genetic algorithm IP kernel,
(2) set up the software collaboration system at software view, be used to calculate adaptive value and random number and provide to hardware genetic algorithm IP kernel,
(3) set up the agreement of information interaction between hardware genetic algorithm IP kernel and the software collaboration system, make the information interaction between hardware view and the software view reach synchronous regime;
Described software collaboration system comprises with lower module,
The adaptive value computing module, this module provides corresponding adaptive value function according to practical problems, realizes the calculating of individual fitness by the adaptive value function;
The random number module, this module produces a random number according to hsrdware requirements;
Described hardware genetic algorithm IP kernel comprises with lower module,
Top control module, this module provides the control signal of calling between each module, thereby controls the flow process of whole genetic algorithm and the flow direction of data, coordinates each module and works under the control signal of top control module;
Initialization module, this module produce the required initial population that develops randomly, for genetic algorithm provides initial population;
Intersect and select module, this module realizes combining of elite's selection and interlace operation, promptly the random number that is provided by the random number module selects two individualities as the parent individuality, determine the position, point of crossing, carry out the single-point interlace operation and produce two new individualities, the adaptive value that provides according to the adaptive value computing module selects two individualities that adaptive value is the highest to replace parent from new individuality and parent individuality then;
Module is selected in variation, this module realizes combining of elite's selection and mutation operation, promptly the random number that is provided by the random number module selects one by one body as the parent individuality, definitive variation point position, carry out the single-point mutation operation and produce a new individuality, the adaptive value that provides according to the adaptive value computing module selects an individuality that adaptive value is the highest to replace parent from new individuality and parent individuality then;
Evaluation module, this module is sought out the individuality that has the optimal-adaptive value in the population of new generation, and the individuality that will have an optimal-adaptive value is updated on the sheet of storage population on the internal memory; And judge whether to reach end condition, then stop genetic algorithm if satisfy end condition;
Memory modules on the sheet, internal memory on two sheets of this module tissue is respectively applied for storage population and adaptive value;
Individual control module, this module be one four and select a module, is used for judging initialization module, intersects that to select module, variation to select module and evaluation module be which module will be carried out individuality the internal memory and read and store from the sheet of storage population;
Adaptive value control module, this module be one four and select a module, is used for judging initialization module, intersects that to select module, variation to select module and evaluation module be which module will be carried out adaptive value the internal memory and read and store from the sheet of storage adaptive value.
And when evaluation module judged whether to reach end condition, described end condition was that the optimal-adaptive value did not change in 100 generations.
And described population of new generation is to select module to carry out elite's selection and interlace operation through intersecting, and selects module to carry out the elite through variation then and selects and mutation operation gained result.
The present invention uses hardware programming to realize as hybridization, variation etc. the module that is suitable for hardware handles in the genetic algorithm, adaptive value in the genetic algorithm is estimated this versatility module handle with software.It not only can promote arithmetic speed, and improves the versatility of genetic algorithm IP kernel, only needs to rewrite the adaptive value function at software layer, just can realize finding the solution of similar problem.The workbench of software-hardware synergism and pure software or pure hardware are realized comparing, and utilization software-hardware synergism method is found the solution has higher efficient and versatility widely.
Description of drawings
Fig. 1 is a schematic diagram of the present invention;
Fig. 2 is the finite state machine figure of the embodiment of the invention;
Fig. 3 is the software and hardware interaction protocol synoptic diagram of the embodiment of the invention.
Embodiment
Describe the present invention below in conjunction with accompanying drawing and embodiment:
Present embodiment is to realize on the XC2VP30 FPGA development board that Xilinx company provides, use PowerPC (a kind of central processing unit of reduced instruction set computer framework) as processor, use logic gates to constitute Hardware I P nuclear, use Xilinx BlockMemory Generator as storer.The FPGA platform has two buses, PLB (Processor Local Bus, processor local bus) and OPB (On-Chip Peripheral Bus, peripheral bus on the sheet).The OPB bus connects some low speed and low-performance equipment, and it is not directly connected to processor cores, but gets in touch by the equipment on bus bridge and the PLB bus (as internal memory on PowerPC and the sheet).During concrete enforcement, the random number module of software view and adaptive value computing module are adopted to be installed among the PowerPC behind the software modularity conceptual design by those skilled in the art and get final product; Each module of hardware view can adopt the Verilog language description according to principle of work, is compiled into to go into the OPB bus as Hardware I P stone grafting after the logic gates and get final product.Build on XC2VP30 FPGA development board in the Hardware I P nuclear, the FPGA platform provides register so that software and hardware directly carries out using when mutual in workflow.Because internal memory can only hardware access on the sheet, embodiment has set 24 registers, is designated as register 0,2,3...23.
As shown in Figure 1, duty of the present invention is to realize regulation and control between each module by top control module.As the random number module and the adaptive value computing module of software view, the initialization module of hardware view, intersection select module, variation to select module, evaluation module all carrying out the mutual of information with top control module.Therefore top control module is the core of whole design, and like the CPU of computer-internal, it is controlling the flow process of whole design and the flow direction of data, and each module also all is to work in an orderly manner under the control signal of top control module.For the design of this IP kernel, the whole system operation state all is embodied on the top control module.Each submodule is carrying out the mutual of information by the control signal of top control module.Initialization module, intersection selection module, variation selection module, evaluation module all are to come internal memory on the sheet is conducted interviews by adaptive value control module and individual control module in addition.For the purpose of implementing, describe among the embodiment each module below in detail for your guidance:
Top control module: top control module is made of a state machine, and state is respectively IDLE, INIT, CROSS, MUT, VALUE and STOP.Top control module is controlled other modules by the mode of state machine.For example enter the INIT state and then activate initialization module and carry out work, enter the CROSS state and then activate to intersect and select module to carry out work.
Random number module: be input as the request signal that initialization module in the hardware view, intersection selection module or variation select module to send, be output as the random number of some.Embodiment adopts the C language to realize, is specially the built-in function rand that calls the C language, and the random number that is obtained is carried out scope handle output again.
Adaptive value computing module: be input as individuality, be output as the adaptive value that calculates.Adopt the C language to realize that specific implementation is for to calculate at the individuality of asking problem to the binary coding form.During concrete enforcement, can according to practical problems corresponding adaptive value function be set in this module in advance, for example embodiment is the 0-1 knapsack problem.
Initialization module: module is finished the initial work of the phase one of genetic algorithm, and specific implementation is the individuality of a generation population size binary coding form, and calculates corresponding adaptive value.The size of setting population in the embodiment of the invention is 32, promptly comprises 32 individualities, these individual formation first generation populations.The adaptive value that initialization module is individual and corresponding with these is kept on the sheet in the internal memory (all individualities deposit internal memory on the sheet of storing population in, and corresponding adaptive value deposits internal memory on the sheet of storing adaptive value in), notifies the top control module task to finish at last.
Intersect and select module: intersect and select module after obtaining the top control module enabling signal, to start.At first send random number request signal (in the present embodiment for be 1) after starting and begin to wait for, detect this signal (CROSS_RAN=1) in the random number module of software view and use the rand function to produce 3 random numbers afterwards immediately CROSS_RAN position in the register 1, wherein two are used for selecting individuality as the parent individuality, and another is used for obtaining the hybridization point.And random number is write in the register (among the embodiment for register 20) of appointment, when the random number module is finished after, return and finish signal (among the embodiment be with register 1 in CROSS_RAN_DONE position be 1) to top control module.Intersect and select module to work on afterwards at this high level signal of acquisition (CROSS_RAN_DONE=1).Intersect and select module to read random number from assigned address (register 20) again, internal memory carries out individual reading on the individual sheet from storing to notify individual control module then, and notice adaptive value control module internal memory from the sheet of storage adaptive value reads corresponding adaptive value.Intersect to select module o'clock two individualities to be hybridized according to the hybridization that obtains again.It is single-point hybridization that embodiment adopts the hybridization mode, is respectively 0xffff and 0x0000 as two individualities, and the hybridization point is 8.Then hybridization acquisition result is 0x00ff and 0xff00.After hybridization finishes, two newly-generated individualities are kept at the appointment adaptive value successively calculate memory address (embodiment is a register 7,8,9,10,11).And then will ask the adaptive value signal calculated to be changed to 1 (being the req_fit position in the register 1 among the embodiment).The adaptive value computing module is detecting this high level signal (req_fit=1) afterwards from specifying adaptive value calculating memory address (register 7,8,9,10,11) to read individuality and carry out corresponding calculated, then the result is kept at specified memory address (being register 12 among the embodiment) and transmits completion signal (the fit_done position for register 0 among the embodiment is high).Intersect and select module to obtain to finish signal (fit_done=1) afterwards after the specified memory address (register 12) that keeps adaptive value reads adaptive value, select wherein two individualities that adaptive value is the highest to deposit internal memory on the sheet of storage population in from parent individuality (two) and offspring individual (two), corresponding adaptive value also deposits internal memory on the sheet of storage adaptive value in.Intersect at last and select module to transmit completion signal.
Module is selected in variation: variation selects module to start after obtaining the top control module enabling signal.At first send random number request signal (in the present embodiment for be 1) after starting and begin to wait for MUT_RAN position in the register 1, obtaining this signal (MUT_RAN=1) in the random number module of software view uses the rand function to produce 2 random numbers afterwards immediately, one of them is used for selecting individual as the parent individuality, another is used to obtain change point, and random number is write in the register (being register 20 among the embodiment) of appointment.After the random number module is finished, return and finish signal (in the present embodiment be 1 for MUT_RAN_DONE position in register 1) to top control module.Variation selects module to work on afterwards at this high level signal of acquisition (MUT_RAN_DONE=1).Variation selects module to read random number from assigned address (register 20) again, internal memory carries out individual reading on the individual sheet from storing to notify individual control module then, and notice adaptive value control module internal memory from the sheet of storage adaptive value reads corresponding adaptive value.Intersect and select module according to the change point that obtains this individuality of selecting to be carried out the single-point variation again.As original parent individuality is 0xff00, and change point is 1, and then variation obtains the new individual 0xff01 that is.After treating that variation finishes, newly-generated individuality is kept at the appointment adaptive value calculates memory address (embodiment is a register 7,8,9,10,11), and then will ask the adaptive value signal calculated to be changed to 1 (being the req_fit position in the register 1 among the embodiment).The adaptive value computing module calculates memory address (register 7,8,9,10,11) from adaptive value afterwards and reads individuality and carry out corresponding calculated detecting this high level signal (req_fit=1), then the result is kept at adaptive value memory address (being the 12nd register among the embodiment) and transmits completion signal (the fit_done position that among the embodiment is the 0th register is for high).Variation selects module to obtain to finish signal (fit_done=1) afterwards after adaptive value memory address (register 12) reads adaptive value, select the best individuality of adaptive value to deposit internal memory on the sheet of storing population in from parent individuality () and offspring individual (), corresponding adaptive value also deposits internal memory on the sheet of storing adaptive value in.Variation at last selects module to transmit completion signal.
Evaluation module: concrete operations are to have the adaptive value size of the individuality that has the optimal-adaptive value in the individuality of optimal-adaptive value and the previous generation population in the population more of new generation relatively.Bigger as the former adaptive value, then the former is replaced the latter and counter is put 0.Otherwise just continue to have, and counter is added 1.Among the embodiment, remove storage 32 each and every one is external for internal memory on the sheet of storage population, and the individuality that also provides a private space storage to have the optimal-adaptive value separately upgrades this space and gets final product during replacement.Internal memory also provides a private space to store corresponding optimal-adaptive value separately on the sheet of storage adaptive value, also carries out corresponding renewal when replacing individuality.When counter during greater than preset value (embodiment is 100), illustrate that the optimal-adaptive value does not change in 100 generations, then notify top control module to shut down.During concrete enforcement, can whenever once intersect selections, once variation selection, with the result as a new generation; Can also set the alternately used intersection selects and makes a variation to select to obtain the next generation, for example once intersect and select the back result as a new generation, once make a variation and select the back result as next a new generation, once intersect again and select the back result as a new generation ... even design a function, select still variation to select to obtain the next generation by the function decision by intersecting.Embodiment sets, and once intersects selection, the selection that once makes a variation then, again with the result as a new generation, like this can comprehensive two kinds of mode of evolution advantages.During concrete enforcement, also can be opposite, the selection that once makes a variation once intersects selection then, again with the result as a new generation.
Individual control module: owing to there are 4 modules need read on the sheet in the memory modules internal memory on the sheet of storage population among the embodiment, this module is four to select a module.Embodiment is other by the different priorities that uses 4 modules of memory modules on the sheet, determines that memory modules obtains individuality to which module on the sheet by using, and concrete priority is that initialization module＞intersection selects module＞variation to select module＞evaluation module;
The adaptive value control module: owing to there are 4 modules need read on the sheet internal memory on the sheet of storage adaptive value in the memory modules among the embodiment, this module is four to select a module.Embodiment is other by the different priorities that uses 4 modules of memory modules on the sheet, and memory modules obtains adaptive value on the sheet by using to determine which module use, and concrete priority is that initialization module＞intersection is selected module＞collector＞evaluation module;
Memory modules on the sheet: for read fast individual information produce the storage population sheet on internal memory, (embodiment is internal memory on the twoport sheet of 33*50 to the individual string length of (population size+1) * that specific implementation generates for the Block Memory Generator that uses Xilinx company.Xilinx Block Memory Generator provides AB two ports, and embodiment is used to the A port to read, and the B port is used to write.The storage of adaptive value is corresponding to individuality, the implementation unanimity: in order to read internal memory on the sheet that adaptive value information produces the storage adaptive value fast, specific implementation is internal memory on the twoport sheet of (population size+1) * adaptive value size (embodiment is 33*32) of the Block Memory Generator generation of using Xilinx company.Xilinx Block MemoryGenerator provides AB two ports, and embodiment is used to the A port to read, and the B port is used to write.Except the individuality and corresponding adaptive value of storage population, especially 1 individuality and the corresponding adaptive value memory locations of being provided with of embodiment more, exactly in order to deposit the individuality that has the optimal-adaptive value in the population, and adaptive value that should individuality.
As shown in Figure 2, whole design is divided into six states.Following system is meant whole software and hardware combining scheme of the present invention.
IDLE: idle condition enters this state after the system reset.Idle condition is carried out control and treatment by the top control module of hardware view.System checks when rising edge clock whether outside run signal (as the switch switch) is arranged.After obtaining high level signal, system brings into operation, otherwise circular wait always.Promptly change init state (INIT) after bringing into operation over to.
INIT: init state, finish the initial work of native system, initial work has specifically comprised the generation population, estimates the adaptive value of population individuality.At first send a signal to software view by top control module, the init mark position that is about to register 0 is 1.Software view then brings into use random number module (calling the rand function) to begin to produce the random number of population size when detecting the init marker bit and be 1, and the adaptive value computing module that the result delivers to software view is carried out evaluation calculation.After the end to be evaluated, the adaptive value computing module is placed on assigned address with individuality and adaptive value thereof and (among the embodiment individuality is left in the register 2,3,4,5,6, adaptive value leaves in the register 12), be 1 with the init_done mark position in the register 0 then.Promptly transmit completion signal the notice top control module.Top control module receive finish signal after, sending the signalisation initialization module again goes to specify register (register 2,3,4,5,6,12) to read individual and adaptive value and individuality and adaptive value is stored on the sheet in the internal memory, all individualities deposit internal memory on the sheet of storing population in, and corresponding adaptive value deposits internal memory on the sheet of storing adaptive value in.After initialization module was finished a population size individual initial work, initialization module sent the initialization end signal and enters the CROSS state to top control module.
CROSS: crossing condition, finish the intersection selection operation in the native system.Being specially top control module sends signal and calls to intersect and select module to start working.And wait at this state.Wait to receive to intersect and select the finishing after the signal of module, enter the MUT state.
MUT: the variation state, finish the variation selection operation in the native system.Being specially top control module sends signal and calls variation and select module to start working.And wait at this state.Wait to receive that variation selects finishing after the signal of module, enter the VALUE state.
VALUE: evaluation status, finish the assessment in the native system and shut down judgment task.Whether evaluation module is used for judging from hybridization and variation kind of the new individuality that obtains has adaptive value better individual.If when adaptive value (native system is 100 iteration among the embodiment) optimum individual in a period of time does not change, just illustrate and found optimum individual, send the signalisation top control module and shut down.
STOP: halted state, finish the associative operation in the native system stopped process.Main operation is exactly that system is with optimum individual and adaptive value output thereof, soon individual and adaptive value places assigned address, and (embodiment leaves individuality in register 19,20,21,22,23, adaptive value leaves in the register 12), read printing by software view then.Entire equipment is returned to the IDLE state at last, internal memory is reset on the sheet again.
The whole system operation flow process is: system reset or power on after enter the IDLE state, system then keep to wait at the IDLE state when the START signal is 0.After system obtains START=1, change the INIT init state over to; The work of INIT state imperfect tense, INIT_DONE equals 0 always, and works on remaining on the INIT state.Send the INIT_DONE=1 signal after initial chemical industry is finished, system changes the CROSS state over to; Before crossover operation was not finished, CROSS_DONE remained 0 always, and worked on remaining on the CROSS state.Send the CROSS_DONE=1 signal after interlace operation is finished, system changes the MUT state over to; Before mutation operation was not finished, MUT_DONE remained 0 always, and worked on remaining on the MUT state.Send the MUT_DONE=1 signal after mutation operation is finished, system changes the EVALUE state over to; Estimate and carry out the halted state judgement after operation is finished, if satisfy stop condition, then send the STOP=1 signal, system changes the STOP state over to, otherwise sends the STOP=0 signal and change the CROSS state over to, proceeds cycling; System unconditionally changes the IDLE state over to after finishing the work that the STOP state will do.
About software and hardware communication protocol as shown in Figure 3: hardware sends Request and finishes for the signal and the obstruction wait software processes of high (1), software obtains hardware, and to send the Request signal be just to begin the software processes work of being correlated with behind the height, will handle done after software processes is finished and be changed to height (1) and begin to block and wait for; Hardware obtains carrying out relevant hardware and handling after the done signal of signal for high (1) that software sends, the Request signal is changed to low (0) after hardware handles is finished again and blocks and wait for.Software obtains after hardware sends the Request signal that signal is low (0) the done signal being put low (0); It is that low (0) illustrates this software and hardware sign off that hardware obtains the done signal, and hardware just can carry out follow-up work then.This operation avoided since hardware speed very fast, cause after software signal is finished in the process of degrade signal, the misdata that hardware solicit operation is once more brought; Perhaps software repeatedly responds maloperations such as hardware requests signal.The stability and the robustness of system have been guaranteed.
Inventive embodiments has been chosen this typical combinatorial optimization problem of 0-1 knapsack problem and has been the contrast experiment from three aspects respectively, and in experimentation, three kinds of modes have all adopted same evolutionary strategy, experimental result such as following table
Data can know that this invention travelling speed obviously is better than the speed of pure software operation and can obtains the optimal value the same with software even better from table.The present invention can also be applied to the scale-of-two problem in addition, and function optimization problem etc. have demonstrated fully pure hardware and realized not available versatility.
The above only for an embodiment among the present invention, is not limited to the present invention.All within spirit of the present invention and principle, any modification of being made improves etc., all should be included within protection scope of the present invention.
Claims (3)
1. the cooperative work of software and hardware implementation method of a genetic algorithm is characterized in that: based on the following each several part of FPGA Platform Implementation,
(1) at hardware view, set up hardware genetic algorithm IP kernel,
(2) set up the software collaboration system at software view, be used to calculate adaptive value and random number and provide to hardware genetic algorithm IP kernel,
(3) set up the agreement of information interaction between hardware genetic algorithm IP kernel and the software collaboration system, make the information interaction between hardware view and the software view reach synchronous regime;
Described software collaboration system comprises with lower module,
The adaptive value computing module, this module provides corresponding adaptive value function according to practical problems, realizes the calculating of individual fitness by the adaptive value function;
The random number module, this module produces a random number according to hsrdware requirements;
Described hardware genetic algorithm IP kernel comprises with lower module,
Top control module, this module provides the control signal of calling between each module, thereby controls the flow process of whole genetic algorithm and the flow direction of data, coordinates each module and works under the control signal of top control module;
Initialization module, this module produce the required initial population that develops randomly, for genetic algorithm provides initial population;
Intersect and select module, this module realizes combining of elite's selection and interlace operation, promptly the random number that is provided by the random number module selects two individualities as the parent individuality, determine the position, point of crossing, carry out the single-point interlace operation and produce two new individualities, the adaptive value that provides according to the adaptive value computing module selects two individualities that adaptive value is the highest to replace parent from new individuality and parent individuality then;
Module is selected in variation, this module realizes combining of elite's selection and mutation operation, promptly the random number that is provided by the random number module selects one by one body as the parent individuality, definitive variation point position, carry out the single-point mutation operation and produce a new individuality, the adaptive value that provides according to the adaptive value computing module selects an individuality that adaptive value is the highest to replace parent from new individuality and parent individuality then;
Evaluation module, this module is sought out the individuality that has the optimal-adaptive value in the population of new generation, and the individuality that will have an optimal-adaptive value is updated on the sheet of storage population on the internal memory; And judge whether to reach end condition, then stop genetic algorithm if satisfy end condition;
Memory modules on the sheet, internal memory on two sheets of this module tissue is respectively applied for storage population and adaptive value; Individual control module, this module be one four and select a module, is used for judging initialization module, intersects that to select module, variation to select module and evaluation module be which module will be carried out individuality the internal memory and read and store from the sheet of storage population;
Adaptive value control module, this module be one four and select a module, is used for judging initialization module, intersects that to select module, variation to select module and evaluation module be which module will be carried out adaptive value the internal memory and read and store from the sheet of storage adaptive value.
2. according to the cooperative work of software and hardware implementation method of the described genetic algorithm of claim 1, it is characterized in that: when evaluation module judged whether to reach end condition, described end condition was that the optimal-adaptive value did not change in 100 generations.
3. according to the cooperative work of software and hardware implementation method of the described genetic algorithm of claim 2, it is characterized in that: described population of new generation is to select module to carry out elite's selection and interlace operation through intersecting, and selects module to carry out the elite through variation then and selects and mutation operation gained result.
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| CN1276378C (en) * | 2003-09-29 | 2006-09-20 | 北京中电华大电子设计有限责任公司 | Method for realizing improved classification efficiency of software and hardware based on optimized genetic algorithm |
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2010
- 2010-01-27 CN CN2010101035739A patent/CN101789044B/en not_active Expired - Fee Related
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| CN102254225A (en) * | 2011-06-03 | 2011-11-23 | 中国科学院西安光学精密机械研究所 | Evolution hardware implementation method based on trend type compact genetic algorithm |
| CN102254225B (en) * | 2011-06-03 | 2013-09-25 | 中国科学院西安光学精密机械研究所 | Evolution hardware implementation method based on trend type compact genetic algorithm |
| CN102495823A (en) * | 2011-12-07 | 2012-06-13 | 重庆邮电大学 | System for classifying deoxyribonucleic acid (DNA) micro-array data based on evolvable hardware and method for constructing system |
| CN102567585A (en) * | 2011-12-31 | 2012-07-11 | 重庆邮电大学 | Intrinsic evolvable hardware system and method based on multi-core virtual reconfigurable structure |
| CN103279332A (en) * | 2013-06-09 | 2013-09-04 | 浪潮电子信息产业股份有限公司 | Data flow parallel processing method based on GPU-CUDA platform and genetic algorithm |
| CN105701539A (en) * | 2016-01-04 | 2016-06-22 | 西安电子科技大学 | Tend type compact genetic algorithm (GA) based on non-durable elitism strategy |
| CN107301459A (en) * | 2017-07-14 | 2017-10-27 | 郑州云海信息技术有限公司 | A kind of method and system that genetic algorithm is run based on FPGA isomeries |
| CN111800223A (en) * | 2019-08-15 | 2020-10-20 | 北京京东尚科信息技术有限公司 | Method, device and system for generating sending message and processing receiving message |
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