CN101789044B - Method of implementing cooperative work of software and hardware of genetic algorithm - Google Patents
Method of implementing cooperative work of software and hardware of genetic algorithm Download PDFInfo
- Publication number
- CN101789044B CN101789044B CN2010101035739A CN201010103573A CN101789044B CN 101789044 B CN101789044 B CN 101789044B CN 2010101035739 A CN2010101035739 A CN 2010101035739A CN 201010103573 A CN201010103573 A CN 201010103573A CN 101789044 B CN101789044 B CN 101789044B
- Authority
- CN
- China
- Prior art keywords
- module
- adaptive value
- hardware
- software
- state
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Management, Administration, Business Operations System, And Electronic Commerce (AREA)
- Feedback Control In General (AREA)
Abstract
The invention provides a method of implementing cooperative work of software and hardware of a genetic algorithm. The genetic algorithm is a typical evolution algorithm, however, due to the characteristic of binary coding, the genetic algorithm implemented by using the software has low efficiency in solving practical problems; and although the hardware FPGA can improve the solving speed, the hardware structure is not easily changed and lacks of flexibility once the pure hardware is implemented. The invention proposes a cooperative design method of the software and the hardware of the genetic algorithm aiming at the shortcomings of the implementation of the software and the hardware, the operating speed can be improved, the generality of the IP core of the genetic algorithm can be improved as well, and the similar problems can be solved only by rewriting the fitness function on a software layer. Compared with the implementation of the pure software and the pure hardware, the working platform with the cooperative software and the hardware has higher efficiency and wider generality in solving the problems by using the method of cooperative software and the hardware.
Description
Technical field
The present invention relates to intelligence computation and software-hardware synergism technology, particularly a kind of technology of using software-hardware synergism to handle genetic algorithm.
Background technology
Genetic algorithm (Genetic Algorithm; GA) be a kind of probabilistic search algorithm that Holland proposed in " Adaptation in Natural andArtificial System " in 1975 first; Yet genetic algorithm is through in an organized way being that message exchange randomly comes the good string of those adaptability of recombination; In each generation; Utilize good position of adaptability in the previous generation string and section to generate the colony of a new string,, also will in string structure, attempt with new position once in a while and section substitute original part as extra interpolation.Be similar to nature and evolve, genetic algorithm is sought good chromosome and is found the solution problem through acting on the gene on the chromosome.Because it does not receive the constraint of the restricted assumed condition in search volume, needn't require such as hypothesis such as continuity, differentiability and unimodality, with and intrinsic concurrency, therefore be widely used in every field as a kind of sane, efficient optimization algorithm.
And present genetic algorithm all is to be realized by pure hardware or pure software, realizes that by software the operation efficiency of algorithm is low.And realize by pure hardware, can only find the solution to certain problem, do not accomplish versatility.These two kinds of implementation methods all have its defective separately, are badly in need of the defective that a kind of feasible integrated technology method can be improved above-mentioned technology at present.
The thought of software-hardware synergism design (Hardware/Software Co-designing) is in the hardware and software design process, to utilize it to act synergistically to greatest extent to the greatest extent to satisfy the requirement of system.After software-hardware synergism thought proposes, enjoy domestic and international researcher's concern always, also very active about the research of software-hardware synergism design field.Up to the present; Chinese scholars had been done a lot of researchs in this regard, such as real time effect at remote sensing image, and the audio coding algorithm; The Lattice decoding algorithm; Digital circuit simulation, software and hardware cooperating design method was all used in some aspects such as the simulation of system, emulation and debugging, and obtained than using the better effect of traditional design method.Therefore utilize software and hardware cooperating design method not only can improve the efficient of the problem of finding the solution, can widen its application simultaneously, further promote software-hardware synergism Design and Development etc.
Summary of the invention
The objective of the invention is to, utilize the mode of cooperative work of software and hardware that a kind of implementation method of genetic algorithm is provided, the calculated performance of algorithm is promoted significantly, and increase the versatility of calculating.
The cooperative work of software and hardware implementation method of genetic algorithm provided by the present invention, based on the following each several part of FPGA Platform Implementation,
(1) at hardware view, set up hardware genetic algorithm IP kernel,
(2) set up the software collaboration system at software view, be used to calculate adaptive value and random number and provide to hardware genetic algorithm IP kernel,
(3) set up the agreement of information interaction between hardware genetic algorithm IP kernel and the software collaboration system, make the information interaction between hardware view and the software view reach synchronous regime;
Said software collaboration system comprises with lower module,
The adaptive value computing module, this module provides corresponding adaptive value function according to practical problems, realizes the calculating of individual fitness through the adaptive value function;
The random number module, this module produces a random number according to hsrdware requirements;
Said hardware genetic algorithm IP kernel comprises with lower module,
Top control module, this module provides the control signal of calling between each module, thereby controls the flow process of whole genetic algorithm and the flow direction of data, coordinates each module and under the control signal of top control module, works;
Initialization module, this module produce the required initial population that develops randomly, for genetic algorithm provides initial population;
Intersect and select module; This module realizes combining of elite's selection and interlace operation; The random number that is promptly provided by the random number module selects two individuals individual as parent, confirms the position, point of crossing, carries out the single-point interlace operation and produces two new individualities; The adaptive value that provides according to the adaptive value computing module is then selected two individuality that adaptive value is the highest replacement parents from new individuality and parent individuality;
Module is selected in variation; This module realizes that the elite selects and the combining of mutation operation, and promptly the random number that is provided by the random number module selects one by one body as parent individuality, definitive variation point position; Carry out the single-point mutation operation and produce a new individuality; The adaptive value that provides based on the adaptive value computing module is selected the individuality that adaptive value is a highest replacement parent from new individuality and parent individuality then;
Evaluation module, this module is sought out the individuality that has the optimal-adaptive value in the population of new generation, and the individuality that will have an optimal-adaptive value is updated on the sheet of storage population on the internal memory; And judge whether to reach end condition, then stop genetic algorithm if satisfy end condition;
Memory modules on the sheet, internal memory on two sheets of this module tissue is respectively applied for storage population and adaptive value;
Individual control module, this module be one four and select a module, is used for judging initialization module, intersects that to select module, variation to select module and evaluation module be that which module will be carried out individuality the internal memory and read and store from the sheet of storage population;
Adaptive value control module, this module be one four and select a module, is used for judging initialization module, intersects that to select module, variation to select module and evaluation module be that which module will be carried out adaptive value the internal memory and read and store from the sheet of storage adaptive value.
And when evaluation module judged whether to reach end condition, said end condition was that the optimal-adaptive value did not change in 100 generations.
And said population of new generation is to select module to carry out elite's selection and interlace operation through intersecting, and selects module to carry out the elite through variation then and selects and mutation operation gained result.
The present invention uses hardware programming to realize like hybridization, variation etc. the module that is suitable for hardware handles in the genetic algorithm, and this versatility module of adaptive value evaluation in the genetic algorithm is handled with software.It not only can promote arithmetic speed, and improves the versatility of genetic algorithm IP kernel, only needs to rewrite the adaptive value function at software layer, just can realize finding the solution of similar problem.The workbench of software-hardware synergism and pure software or pure hardware are realized comparing, and utilization software-hardware synergism method is found the solution has higher efficient and versatility widely.
Description of drawings
Fig. 1 is a schematic diagram of the present invention;
Fig. 2 is the finite state machine figure of the embodiment of the invention;
Fig. 3 is the software and hardware interaction protocol synoptic diagram of the embodiment of the invention.
Embodiment
Describe the present invention below in conjunction with accompanying drawing and embodiment:
Present embodiment is on the XC2VP30 FPGA development board that Xilinx company provides, to realize; Use PowerPC (a kind of central processing unit of reduced instruction set computer framework) as processor; Use logic gates to constitute Hardware I P nuclear, use Xilinx BlockMemory Generator as storer.The FPGA platform has two buses, PLB (Processor Local Bus, processor local bus) and OPB (On-Chip Peripheral Bus, peripheral bus on the sheet).The OPB bus connects some low speed and low-performance equipment, and it is not directly connected to processor cores, but through the contact of the equipment (like internal memory on PowerPC and the sheet) on bus bridge and the PLB bus.During practical implementation, the random number module of software view and adaptive value computing module are adopted to be installed among the PowerPC behind the software modularity conceptual design by those skilled in the art and get final product; Each module of hardware view can adopt the Verilog language description according to principle of work, is compiled into to go into the OPB bus as Hardware I P stone grafting after the logic gates and get final product.On XC2VP30 FPGA development board, build in the Hardware I P nuclear, the FPGA platform provides register so that software and hardware directly carries out using when mutual in workflow.Because internal memory can only hardware access on the sheet, embodiment has set 24 registers, is designated as register 0,2,3...23.
As shown in Figure 1, duty of the present invention is to realize the regulation and control between each module by top control module.Like the random number module and the adaptive value computing module of software view, the initialization module of hardware view, intersection select module, variation to select module, evaluation module all carrying out the mutual of information with top control module.Therefore top control module is the core of whole design, and like the CPU of computer-internal, it is controlling the flow process of whole design and the flow direction of data, and each module also all is under the control signal of top control module, to work in an orderly manner.As far as the design of this IP kernel, the whole system operation state all is embodied on the top control module.Each sub-module is being carried out the mutual of information through the control signal of top control module.Initialization module, intersection selection module, variation selection module, evaluation module all are to come internal memory on the sheet is conducted interviews through adaptive value control module and individual control module in addition.For the purpose of implementing, specify among the embodiment each module below for your guidance:
Top control module: top control module is made up of a state machine, and state is respectively IDLE, INIT, CROSS, MUT, VALUE and STOP.Top control module is controlled other modules through the mode of state machine.For example get into the INIT state and then activate initialization module and carry out work, get into the CROSS state and then activate to intersect and select module to carry out work.
Random number module: be input as initialization module in the hardware view, intersect and select module or variation to select module sent request signal, be output as the random number of some.Embodiment adopts the C language to realize, is specially the built-in function rand that calls the C language, and the random number that is obtained is carried out scope handle output again.
Adaptive value computing module: be input as individuality, be output as the adaptive value that calculates.Adopt the C language to realize, specifically be embodied as to the problem of asking the individuality of binary coding form is calculated.During practical implementation, can based on practical problem corresponding adaptive value function be set in this module in advance, for example embodiment is the 0-1 knapsack problem.
Initialization module: module is accomplished the initial work of the phase one of genetic algorithm, specifically is embodied as the individuality that produces a population size binary coding form, and calculates corresponding adaptive value.The size of setting population in the embodiment of the invention is 32, promptly comprises 32 individuals, these individual formation first generation populations.Initialization module is kept at these individual and corresponding adaptive values on the sheet in the internal memory (all individualities deposit internal memory on the sheet of storage population in, and corresponding adaptive value deposits internal memory on the sheet of storing adaptive value in), notifies the completion of top control module task at last.
Intersect and select module: intersect and select module after obtaining the top control module enabling signal, to start.At first send random number request signal (in the present embodiment for be 1) after starting and begin to wait for, detect this signal (CROSS_RAN=1) in the random number module of software view and use the rand function to produce 3 random numbers afterwards immediately CROSS_RAN position in the register 1; Wherein two are used for selecting individuality individual as parent, and another is used for obtaining the hybridization point.And random number is write in the register (among the embodiment for register 20) of appointment, after the random number module is accomplished, return and accomplish signal (among the embodiment be with register 1 in CROSS_RAN_DONE position be 1) to top control module.Intersect and select module to work on afterwards at this high level signal of acquisition (CROSS_RAN_DONE=1).Intersect and select module to read random number from assigned address (register 20) again; Internal memory carries out individual reading on the individual sheet from storing to notify individual control module then, and notice adaptive value control module internal memory from the sheet of storage adaptive value reads corresponding adaptive value.Intersect to select module o'clock two individuals to be hybridized according to the hybridization that obtains again.It is single-point hybridization that embodiment adopts the hybridization mode, is respectively 0xffff and 0x0000 like two individuals, and the hybridization point is 8.Then hybridization acquisition result is 0x00ff and 0xff00.After hybridization finishes, two newly-generated individuals are kept at the appointment adaptive value successively calculate memory address (embodiment is a register 7,8,9,10,11).And then will ask the adaptive value signal calculated to be changed to 1 (being the req_fit position in the register 1 among the embodiment).The adaptive value computing module is detecting this high level signal (req_fit=1) afterwards from specifying adaptive value calculating memory address (register 7,8,9,10,11) to read individuality and carry out corresponding calculated, then the result is kept at specified memory address (being register 12 among the embodiment) and sends completion signal (the fit_done position for register 0 among the embodiment is high).Intersect and select module to obtain to accomplish signal (fit_done=1) afterwards after the specified memory address (register 12) that keeps adaptive value reads adaptive value; From parent individual (two) and offspring individual (two), select wherein that two individualities that adaptive value is the highest deposit internal memory on the sheet of storing population in, corresponding adaptive value also deposits internal memory on the sheet of storing adaptive value in.Intersect at last and select module to send the completion signal.
Module is selected in variation: variation selects module after obtaining the top control module enabling signal, to start.At first send random number request signal (in the present embodiment for be 1) after starting and begin to wait for MUT_RAN position in the register 1; Random number module this signal of acquisition (MUT_RAN=1) at software view uses the rand function to produce 2 random numbers afterwards immediately; One of them is used for selecting individual individual as parent; Another is used to obtain change point, and random number is write in the register (being register 20 among the embodiment) of appointment.After the random number module is accomplished, return and accomplish signal (in the present embodiment be with register 1 in MUT_RAN_DONE position be 1) to top control module.Variation selects module to work on afterwards at this high level signal of acquisition (MUT_RAN_DONE=1).Variation selects module to read random number from assigned address (register 20) again; Internal memory carries out individual reading on the individual sheet from storing to notify individual control module then, and notice adaptive value control module internal memory from the sheet of storage adaptive value reads corresponding adaptive value.Intersect and select module according to the change point that obtains this individuals of selecting to be carried out the single-point variation again.Parent individuality as original is 0xff00, and change point is 1, and then variation obtains the new individual 0xff01 that is.After treating that variation finishes, newly-generated individuality is kept at the appointment adaptive value calculates memory address (embodiment is a register 7,8,9,10,11), and then will ask the adaptive value signal calculated to be changed to 1 (being the req_fit position in the register 1 among the embodiment).The adaptive value computing module calculates memory address (register 7,8,9,10,11) from adaptive value afterwards and reads individuality and carry out corresponding calculated detecting this high level signal (req_fit=1), then the result is kept at adaptive value memory address (being the 12nd register among the embodiment) and sends and accomplish signal (the fit_done position that among the embodiment is the 0th register is for high).Variation selects module to obtain to accomplish signal (fit_done=1) afterwards after adaptive value memory address (register 12) reads adaptive value; From parent individual () and offspring individual (), select the best individuality of adaptive value to deposit internal memory on the sheet of storing population in, corresponding adaptive value also deposits internal memory on the sheet of storing adaptive value in.Variation is at last selected module to send and is accomplished signal.
Evaluation module: concrete operations are to have the adaptive value size of the individuality that has the optimal-adaptive value in the individuality of optimal-adaptive value and the previous generation population in the population more of new generation relatively.Bigger like the former adaptive value, then the former is replaced the latter and counter is put 0.Otherwise just continue to have, and counter is added 1.Among the embodiment, internal memory is except that storage 32 individuals on the sheet of storage population, and the individuality that also provides a private space storage to have the optimal-adaptive value separately upgrades this space and gets final product during replacement.Internal memory also provides a private space to store corresponding optimal-adaptive value separately on the sheet of storage adaptive value, also carries out corresponding renewal when replacement is individual.When counter during greater than preset value (embodiment is 100), explain that the optimal-adaptive value does not change in 100 generations, then notify top control module to shut down.During practical implementation, can whenever once intersect selection, once variation is selected, with the result as a new generation; Can also set the alternately used intersection selects and makes a variation to select to obtain the next generation; For example once intersect and select the back result as a new generation; Once make a variation and select the back result as next a new generation; Once intersect again and select the back result as a new generation ... even design a function, select still variation to select to obtain the next generation by the function decision through intersecting.Embodiment sets, and once intersects selection, the selection that once makes a variation then, again with the result as a new generation, like this can comprehensive two kinds of mode of evolution advantages.During practical implementation, also can be opposite, the selection that once makes a variation once intersects selection then, again with the result as a new generation.
Individual control module: owing to there are 4 modules need read on the sheet in the memory modules internal memory on the sheet of storage population among the embodiment, this module is four to select a module.Embodiment is other through the different priorities that uses 4 modules of memory modules on the sheet, confirms that memory modules obtains individuality to which module on the sheet through using, and concrete priority is that initialization module＞intersection selects module＞variation to select module＞evaluation module;
The adaptive value control module: owing to there are 4 modules need read on the sheet internal memory on the sheet of storage adaptive value in the memory modules among the embodiment, this module is four to select a module.Embodiment is other through the different priorities that uses 4 modules of memory modules on the sheet, and memory modules obtains adaptive value on the sheet through using to confirm which module use, and concrete priority is that initialization module＞intersection is selected module＞collector＞evaluation module;
Memory modules on the sheet: for read fast individual information produce the storage population sheet on internal memory, (embodiment is internal memory on the twoport sheet of 33*50 specifically to be embodied as the individual string length of (population size+1) * that the Block Memory Generator that uses Xilinx company generates.Xilinx Block Memory Generator provides AB two ports, and embodiment is used to the A port to read, and the B port is used to write.The storage of adaptive value is corresponding to individuality; Implementation is consistent: for internal memory on the twoport sheet of (population big or small+1) * adaptive value big or small (embodiment is 33*32) of reading internal memory on the sheet that adaptive value information produces the storage adaptive value fast, specifically being embodied as the Block Memory Generator generation of using Xilinx company.Xilinx Block MemoryGenerator provides AB two ports, and embodiment is used to the A port to read, and the B port is used to write.Except the individuality and corresponding adaptive value of storage population, especially 1 individuals and the corresponding adaptive value memory locations of being provided with of embodiment more, exactly in order to deposit the individuality that has the optimal-adaptive value in the population, and adaptive value that should individuality.
As shown in Figure 2, whole design is divided into six states.Following system is meant whole software and hardware combining scheme of the present invention.
IDLE: idle condition gets into this state after the system reset.Idle condition is carried out control and treatment by the top control module of hardware view.System checks when rising edge clock whether outside run signal (like the switch switch) is arranged., system brings into operation after obtaining high level signal, otherwise circular wait always.Promptly change init state (INIT) after bringing into operation over to.
INIT: init state, the initial work of completion native system, initial work has specifically comprised the generation population, estimates the individual adaptive value of population.At first send a signal to software view by top control module, the init mark position that is about to register 0 is 1.Software view then brings into use random number module (calling the rand function) to begin to produce the random number of population size when detecting the init marker bit and be 1, and the adaptive value computing module that the result delivers to software view is carried out evaluation calculation.After the end to be evaluated; The adaptive value computing module is placed on assigned address with individuality and adaptive value thereof and (among the embodiment individuality is left in the register 2,3,4,5,6; Adaptive value leaves in the register 12), be 1 with the init_done mark position in the register 0 then.Promptly send and accomplish the signalisation top control module.Top control module is after receiving the completion signal; The signalisation initialization module of redispatching goes to specify register (register 2,3,4,5,6,12) to read individual and adaptive value and individuality and adaptive value is stored on the sheet in the internal memory; All individualities deposit internal memory on the sheet of storing population in, and corresponding adaptive value deposits internal memory on the sheet of storing adaptive value in.After initialization module was accomplished the initial work of population size individuals, initialization module sent the initialization end signal and gets into the CROSS state to top control module.
CROSS: crossing condition, accomplish the intersection selection operation in the native system.Being specially top control module sends signal and calls to intersect and select module to start working.And wait at this state.Wait to receive to intersect and select to get into the MUT state after the completion signal of module.
MUT: the variation state, accomplish the variation selection operation in the native system.Being specially top control module sends signal and calls variation and select module to start working.And wait at this state.Wait to receive after the completion signal of variation selection module, get into the VALUE state.
VALUE: evaluation status, accomplish the assessment in the native system and shut down judgment task.Whether evaluation module is used for judging from hybridization and variation kind of the new individuality that obtains has adaptive value better individual.If when adaptive value (native system is 100 iteration among the embodiment) optimum individual in a period of time does not change, just explain and found optimum individual, send the signalisation top control module and shut down.
STOP: halted state, accomplish the associative operation in the native system stopped process.Main operation is exactly that system is with optimum individual and adaptive value output thereof; Soon individual and adaptive value places assigned address, and (embodiment leaves individuality in register 19,20,21,22,23; Adaptive value leaves in the register 12), read printing by software view then.Again entire equipment is returned to the IDLE state at last, internal memory is reset on the sheet.
The whole system operation flow process is: the system reset or the back that powers on get into the IDLE state, and system then keeps waiting at the IDLE state when the START signal is 0.After system obtains START=1, change the INIT init state over to; The work of INIT state imperfect tense, INIT_DONE equals 0 always, and works on remaining on the INIT state.After initial chemical industry is done to accomplish, send the INIT_DONE=1 signal, system changes the CROSS state over to; Before crossover operation was not accomplished, CROSS_DONE remained 0 always, and worked on remaining on the CROSS state.After interlace operation is accomplished, send the CROSS_DONE=1 signal, system changes the MUT state over to; Before mutation operation was not accomplished, MUT_DONE remained 0 always, and worked on remaining on the MUT state.After mutation operation is accomplished, send the MUT_DONE=1 signal, system changes the EVALUE state over to; Estimate and carry out the halted state judgement after operation is accomplished, if satisfy stop condition, then send the STOP=1 signal, system changes the STOP state over to, otherwise sends the STOP=0 signal and change the CROSS state over to, proceeds cycling; Unconditionally change the IDLE state over to after the work that system's completion STOP state will be done.
Can be known by Fig. 3 about software and hardware communication protocol: hardware sends Request and accomplishes for the signal and the obstruction wait software processes of high (1); Software obtains hardware, and to send the Request signal be just to begin the software processes work of being correlated with behind the height, will handle done after software processes is accomplished and be changed to height (1) and begin to block wait; Hardware obtains carrying out relevant hardware and handling after the done signal of signal for high (1) that software sends, again the Request signal is changed to low (0) after hardware handles is accomplished and blocks and wait for.Software obtains after hardware sends the Request signal that signal is low (0) the done signal being put low (0); It is that this software and hardware sign off is explained in low (0) that hardware obtains the done signal, and hardware just can carry out follow-up work then.This operation has been avoided because hardware speed is very fast, cause after software signal is accomplished in the process at degrade signal, the misdata that hardware solicit operation is once more brought; Perhaps software repeatedly responds maloperations such as hardware requests signal.The stability and the robustness of system have been guaranteed.
Inventive embodiments has been chosen this typical combinatorial optimization problem of 0-1 knapsack problem and has been the contrast experiment from three aspects respectively, and in experimentation, three kinds of modes have all adopted same evolutionary strategy, experimental result such as following table
Data can know that this invention travelling speed obviously is superior to the speed of pure software operation and can obtains the optimal value the same with software even better from table.The present invention can also be applied to the scale-of-two problem in addition, and function optimization problem etc. have demonstrated fully pure hardware and realized not available versatility.
The embodiment that the above is merely among the present invention is not limited to the present invention.All within spirit of the present invention and principle, any modification of being made improves etc., all should be included within protection scope of the present invention.
Claims (3)
1. a software-hardware synergism genetic algorithm realizes system, it is characterized in that: based on the following each several part of FPGA Platform Implementation,
(1) at hardware view, set up hardware genetic algorithm IP kernel,
(2) set up the software collaboration system at software view, be used to calculate adaptive value and random number and provide to hardware genetic algorithm IP kernel,
(3) set up the agreement of information interaction between hardware genetic algorithm IP kernel and the software collaboration system, make the information interaction between hardware view and the software view reach synchronous regime; Deposit internal memory on the sheet of storing population in, corresponding adaptive value also deposits internal memory on the sheet of storing adaptive value in;
Said software collaboration system comprises with lower module,
The adaptive value computing module, this module provides corresponding adaptive value function according to practical problems, realizes the calculating of individual fitness through the adaptive value function, this module be input as individuality, be output as the adaptive value that calculates;
The random number module, this module produces a random number according to hsrdware requirements, and module sent request signal is selected in be input as initialization module in the hardware view, intersection selection module or the variation of this module, is output as the random number of some;
Said hardware genetic algorithm IP kernel comprises with lower module,
Top control module, this module provides the control signal of calling between each module, thereby controls the flow process of whole genetic algorithm and the flow direction of data, coordinates each module and under the control signal of top control module, works;
Initialization module; This module produces the required initial population that develops randomly; For genetic algorithm provides initial population, comprise the individuality that produces a population size binary coding form, and calculate corresponding adaptive value; All individualities deposit internal memory on the sheet of storing population in, and corresponding adaptive value deposits internal memory on the sheet of storing adaptive value in;
Intersect and select module; This module realizes combining of elite's selection and interlace operation, and promptly the random number that is provided by the random number module selects two individuals individual as parent, confirms the position, crosspoint; Carry out the single-point interlace operation and produce two new individualities; The adaptive value that provides based on the adaptive value computing module is selected two individuality that adaptive value is the highest replacement parents and is deposited internal memory on the sheet of storing population in from new individuality and parent individuality then, and corresponding adaptive value also deposits internal memory on the sheet of storing adaptive value in;
Module is selected in variation; This module realizes combining of elite's selection and mutation operation; Promptly the random number that is provided by the random number module selects one by one body individual as parent, and definitive variation point position is carried out the single-point mutation operation and produced a new individuality; The adaptive value that provides based on the adaptive value computing module is selected the individuality that adaptive value is a highest replacement parent from new individuality and parent individuality then;
Evaluation module, this module is sought out the individuality that has the optimal-adaptive value in the population of new generation, and the individuality that will have an optimal-adaptive value is updated on the sheet of storage population on the internal memory; And judge whether to reach end condition, then stop genetic algorithm if satisfy end condition;
Memory modules on the sheet, internal memory on two sheets of this module tissue is respectively applied for storage population and adaptive value;
Individual control module, this module be one four and select a module, is used for judging initialization module, intersects that to select module, variation to select module and evaluation module be that which module will be carried out individuality the internal memory and read and store from the sheet of storage population;
Adaptive value control module, this module be one four and select a module, is used for judging initialization module, intersects that to select module, variation to select module and evaluation module be that which module will be carried out adaptive value the internal memory and read and store from the sheet of storage adaptive value;
It all is to come internal memory on the sheet is conducted interviews through adaptive value control module and individual control module that said initialization module, intersection select module, variation to select module, evaluation module;
Said top control module is made up of a state machine, and state is respectively IDLE, INIT, CROSS, MUT, VALUE and STOP,
IDLE representes idle condition, gets into this state after the system reset; Idle condition is carried out control and treatment by the top control module of hardware view; System checks when rising edge clock whether outside run signal is arranged; After system obtains high level signal, bring into operation, otherwise circular wait always promptly changes the INIT state over to after bringing into operation;
INIT representes init state, accomplishes the initial work of native system, and initial work has specifically comprised the generation population, estimates the individual adaptive value of population; At first send a signal to software view by top control module, the INIT mark position that is about to register 0 is 1; Software view then brings into use the random number module to begin to produce the random number of population size when detecting the INIT marker bit and be 1, and the adaptive value computing module that the result delivers to software view is carried out evaluation calculation; After the end to be evaluated, the adaptive value computing module is placed on assigned address with individuality and adaptive value thereof, is 1 with the INIT_DONE mark position in the register 0 then, promptly sends and accomplishes the signalisation top control module; Top control module is after receiving the completion signal; The signalisation initialization module of redispatching goes to specify register to read individual and adaptive value and individuality and adaptive value is stored on the sheet in the internal memory; All individualities deposit internal memory on the sheet of storing population in, and corresponding adaptive value deposits internal memory on the sheet of storing adaptive value in; After initialization module was accomplished the initial work of population size individuals, initialization module sent the initialization end signal and gets into the CROSS state to top control module;
CROSS representes crossing condition, accomplishes the intersection selection operation in the native system, is specially top control module and sends signal and call to intersect and select module to start working.And wait at this state.Wait to receive to intersect and select to get into the MUT state after the completion signal of module;
MUT representes the variation state, accomplishes the variation selection operation in the native system, is specially top control module and sends signal and call variation and select module to start working, and wait at this state, waits to receive that variation selects to get into the VALUE state after the completion signal of module;
VALUE representes evaluation status; Accomplish the assessment in the native system and shut down judgment task; Whether evaluation module is judged from hybridization and variation kind of the new individuality that obtains has adaptive value better individual; If when adaptive value optimum individual in a period of time does not change, just explain and found optimum individual, send the signalisation top control module and shut down;
STOP representes halted state, accomplishes the associative operation in the native system stopped process, and system is with optimum individual and adaptive value output thereof; Be about to individuality and place assigned address with adaptive value; Read printing by software view then, again entire equipment is returned to the IDLE state at last, internal memory is reset on the sheet;
The whole system operation flow process is: the system reset or the back that powers on get into the IDLE state, and system then keeps waiting at the IDLE state when the START signal is 0, after system obtains START=1, changes the INIT init state over to; The work of INIT state imperfect tense, INIT_DONE equals 0 always, and works on remaining on the INIT state; After initial chemical industry is done to accomplish, send the INIT_DONE=1 signal, system changes the CROSS state over to; Before crossover operation was not accomplished, CROSS_DONE remained 0 always, and worked on remaining on the CROSS state; After interlace operation is accomplished, send the CROSS_DONE=1 signal, system changes the MUT state over to; Before mutation operation was not accomplished, MUT_DONE remained 0 always, and worked on remaining on the MUT state; After mutation operation is accomplished, send the MUT_DONE=1 signal, system changes the EVALUE state over to; Estimate and carry out the halted state judgement after operation is accomplished, if satisfy stop condition, then send the STOP=1 signal, system changes the STOP state over to, otherwise sends the STOP=0 signal and change the CROSS state over to, proceeds cycling; Unconditionally change the IDLE state over to after the work that system's completion STOP state will be done.
2. software-hardware synergism genetic algorithm according to claim 1 realizes system, and it is characterized in that: when evaluation module judged whether to reach end condition, said end condition was that the optimal-adaptive value did not change in 100 generations.
3. software-hardware synergism genetic algorithm according to claim 2 realizes system; It is characterized in that: said population of new generation is to select module to carry out elite's selection and interlace operation through intersecting, and selects module to carry out the elite through variation then and selects and mutation operation gained result.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101035739A CN101789044B (en) | 2010-01-27 | 2010-01-27 | Method of implementing cooperative work of software and hardware of genetic algorithm |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101035739A CN101789044B (en) | 2010-01-27 | 2010-01-27 | Method of implementing cooperative work of software and hardware of genetic algorithm |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101789044A CN101789044A (en) | 2010-07-28 |
| CN101789044B true CN101789044B (en) | 2012-03-28 |
Family
ID=42532254
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010101035739A Expired - Fee Related CN101789044B (en) | 2010-01-27 | 2010-01-27 | Method of implementing cooperative work of software and hardware of genetic algorithm |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101789044B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102254225B (en) * | 2011-06-03 | 2013-09-25 | 中国科学院西安光学精密机械研究所 | Evolvable hardware implementation method based on trend-type compact genetic algorithm |
| CN102495823A (en) * | 2011-12-07 | 2012-06-13 | 重庆邮电大学 | System for classifying deoxyribonucleic acid (DNA) micro-array data based on evolvable hardware and method for constructing system |
| CN102567585B (en) * | 2011-12-31 | 2014-03-19 | 重庆邮电大学 | Intrinsic evolvable hardware system and method based on multi-core virtual reconfigurable structure |
| CN103279332A (en) * | 2013-06-09 | 2013-09-04 | 浪潮电子信息产业股份有限公司 | Data flow parallel processing method based on GPU-CUDA platform and genetic algorithm |
| CN105701539A (en) * | 2016-01-04 | 2016-06-22 | 西安电子科技大学 | Tend type compact genetic algorithm (GA) based on non-durable elitism strategy |
| CN107301459A (en) * | 2017-07-14 | 2017-10-27 | 郑州云海信息技术有限公司 | A kind of method and system that genetic algorithm is run based on FPGA isomeries |
| CN111800223B (en) * | 2019-08-15 | 2023-06-23 | 北京京东尚科信息技术有限公司 | Method, device and system for generating sending message and processing receiving message |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1604304A (en) * | 2003-09-29 | 2005-04-06 | 北京中电华大电子设计有限责任公司 | Method for realizing improved classification efficiency of software and hardware based on optimized genetic algorithm |
-
2010
- 2010-01-27 CN CN2010101035739A patent/CN101789044B/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1604304A (en) * | 2003-09-29 | 2005-04-06 | 北京中电华大电子设计有限责任公司 | Method for realizing improved classification efficiency of software and hardware based on optimized genetic algorithm |
Non-Patent Citations (3)
| Title |
|---|
| 刘功杰，张鲁峰，李思昆.遗传算法在软硬件划分中的应用.《国防科技大学学报》.2002,第24卷(第2期),第64-68页. * |
| 郭兆阳.基于遗传算法的软硬件协同设计探索.《真空电子技术》.2005,(第2期),第13-15页. * |
| 郭荣华，李斌，庄镇泉.基于混合量子遗传算法的嵌入式系统软硬件协同综合算法.《量子电子学报》.2008,第25卷(第4期),第443-450页. * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101789044A (en) | 2010-07-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101789044B (en) | Method of implementing cooperative work of software and hardware of genetic algorithm | |
| Li et al. | Efficient multi-objective optimization algorithm for hybrid flow shop scheduling problems with setup energy consumptions | |
| CN109858620A (en) | One type brain computing system | |
| CN102306141B (en) | Method for describing configuration information of dynamic reconfigurable array | |
| Xie et al. | An effective multi-objective artificial bee colony algorithm for energy efficient distributed job shop scheduling | |
| CN1645352A (en) | Method for managing data in an array processor and array processor carrying out this method | |
| Zhong et al. | An optimized mapping algorithm based on simulated annealing for regular NoC architecture | |
| CN102402415B (en) | Device and method for buffering data in dynamic reconfigurable array | |
| US20110225110A1 (en) | Software control of hardware accelerated DNA codeword searching | |
| Bhatele et al. | Application-specific topology-aware mapping for three dimensional topologies | |
| WO2018208338A1 (en) | Configuration of application software on multi-core image processor | |
| CN108829230B (en) | Queuing theory-based data center energy-saving model design method | |
| Zhang et al. | Task scheduling of cloud computing based on Improved CHC algorithm | |
| Navimipour et al. | The LGR method for task scheduling in computational grid | |
| CN102289424B (en) | Configuration stream working method for dynamic reconfigurable array processor | |
| CN104579651B (en) | The method and apparatus of elliptic curve cipher point multiplication operation | |
| Ding et al. | A Novel Evolutionary Algorithm for Energy Efficient Scheduling in Flexible Job Shops | |
| Ozen et al. | Genetic algorithm based NoC design with voltage/frequency islands | |
| EP4268086A1 (en) | A novel data processing architecture and related procedures and hardware improvements | |
| Lee et al. | Memory-aware mapping and scheduling of tasks and communications on many-core SoC | |
| Le et al. | Pareto optimal mapping for tile-based network-on-chip under reliability constraints | |
| Han et al. | A hybrid discrete harmony search algorithm for blocking flow shop scheduling | |
| CN102968388A (en) | Method and device for structuring data | |
| Mulchandani et al. | EBMICQL: Improving Efficiency of Blockchain Miner Pools via Incremental and Continuous Q-Learning Framework | |
| CN105975048A (en) | DSP chip and construction method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C53 | Correction of patent for invention or patent application | ||
| CB03 | Change of inventor or designer information |
Inventor after: Wang Feng Inventor after: Li Yuanxiang Inventor after: Liu Haifeng Inventor after: Wang Long Inventor after: Lei Xin Inventor after: Liu Lin Inventor before: Liu Haifeng Inventor before: Li Yuanxiang Inventor before: Wang Feng Inventor before: Wang Long Inventor before: Lei Xin Inventor before: Liu Lin |
|
| COR | Change of bibliographic data |
Free format text: CORRECT: INVENTOR; FROM: LIU HAIFENG LI YUANXIANG WANG FENG WANG LONG LEI XIN LIU LIN TO: WANG FENG LI YUANXIANG LIU HAIFENG WANG LONG LEI XIN LIU LIN |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120328 Termination date: 20170127 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |