CN101778535A - Low-cost high-efficiency method for controlling multi-layer circuit board platen manufacturing layer deviation - Google Patents
Low-cost high-efficiency method for controlling multi-layer circuit board platen manufacturing layer deviation Download PDFInfo
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- CN101778535A CN101778535A CN200910104877A CN200910104877A CN101778535A CN 101778535 A CN101778535 A CN 101778535A CN 200910104877 A CN200910104877 A CN 200910104877A CN 200910104877 A CN200910104877 A CN 200910104877A CN 101778535 A CN101778535 A CN 101778535A
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Abstract
The invention discloses a low-cost high-efficiency method for controlling multi-layer circuit board platen manufacturing layer deviation, belonging to the technical field of multi-layer circuit board manufacturing, in particular to a low-cost method for controlling multi-layer circuit board platen manufacturing layer deviation. The method can solve the phenomena of dropping and the like before hot melting position stitching because a well-known punching machine can not simultaneously position, chooses improper hot melting positioning or has personal operation problems due to low precision and hot melting and riveting for walkthrough during punching one by one. The invention adopts an OPE machine to punch by an internal layer of core veneers, and walkthrough simultaneously adopts hot melting and riveting to stake for complementing so as to obtain ideal positioning effect. The method not only can improve production efficiency and low production cost but also can solve the problem of interlayer dislocation.
Description
Technical field
The invention belongs to the multilayer circuit board manufacture technology field, especially a kind of method of low-cost high-efficiency control multi-layer circuit board platen manufacturing layer deviation.
Background technology
It is more to clip the PP number in the multilayer circuit board production between two central layers, fluidity was bigger than normal relatively after the PP resin was heated to a certain degree in the pressing process, thereby easily tearing central layer during resin flows makes it the central layer slippage and causes interlayer dislocation, central layer thickness is that 5mil (not cupric) is following particularly evident, produce the inclined to one side scrappage of this type of structure flaggy and reach 5%-10%, cost is higher.
At present, known multi-layer circuit board platen manufacturing method is that the riveted layer adopts tabula rasa to add the PP structure, and punching is one by one adjusted the design of CAM data simultaneously and divided 2 pressings, during pressing location employing riveter nail or hot melt list kind mode position, adopt the isolation type film mode during pressing tabula rasa.In the production process of reality, the method can reduce resin flow to a certain extent, prevent that pressing process middle level is inclined to one side, but cause internal layer exposure aligning difficulty to increase, flow process is loaded down with trivial details, does the back processing procedure and is prone to the plate bursting lamination, there is quality hidden danger, seriously increased cost, reduced production efficiency, the client can't guarantee delivery date.
Summary of the invention
In order to overcome the interlayer dislocation in the multi-layer circuit board platen manufacturing process, cost height, the problem that production efficiency is low.Through my company's repetition test, invented a kind of method of low-cost high-efficiency control multi-layer circuit board platen manufacturing layer deviation.This method can be enhanced productivity, be reduced production costs, and can improve the difficult problem of interlayer dislocation again.
The technical solution adopted in the present invention is: core material adopts OPE, and (full name: machine punching OPTILINE PE), walkthrough are adopted hot melt to add the riveter nail and are positioned simultaneously.The OPE perforating press can disposablely be gone out 12 location holes, if core material exists harmomegathus difference also can nourish and repays punching, have the high advantage of punching precision.Corresponding PP equally also needs go out location hole with OPE PP perforating press, and punching hole diameter is that 4.5mm can solve because of punching one by one causes precision not high, and the punching aperture generally can be amplified to 6-8mm.Rivet diameter is generally 3.175mm, yielding or holes during the excessive riveter in PP aperture nail, cause pressing after layer partially.Walkthrough of the present invention adopts hot melt to add the riveter nail and positions simultaneously, can solve because of its location area of riveter nail location is little merely, rivet is bloomed or simple hot melt location, can not reach the desired position effect with regard to occurring coming off before the improper or personnel operation problem of hot melt parameters selection makes the pressing of hot melt position.Carry out both complementations of mode riveted simultaneously but adopt hot melt to add the riveter nail, thereby reach desirable locating effect.
Adopt the method for the invention management and control to produce multilayer circuit board in batches, a layer scrappage is partially reduced in 1% by former 5%-10%, is a kind ofly can enhance productivity, reduce production costs, and can improve the method that misplaces between many PP structure sheafs again.
Embodiment
Material selection: riveted layer PP requires to use short G/T PP, and gel time is 110 ± 10 seconds.
Internal layer: central layer uses the punching of OPE machine.
Walkthrough:
A:PP uses OPE PP perforating press to go out positioning hole corresponding, and punching hole diameter is 4.5mm.
B: play 6 closing-ups again with 4 slotted eye location hot melts earlier.
The pressing plate formula: (pressure unit: PSI, temperature unit: ℃)
Temperature/time: 14,0/5 140,/15 160,/10 160,/11 180,/14 210,/11 210,/34 140/20
Pressure/time: 10,0/5 100,/15 250,/10 280,/11 280,/14 280,/11 280,/34 200/20.
Claims (2)
1. the method for a low-cost high-efficiency control multi-layer circuit board platen manufacturing layer deviation is characterized in that: PP and OPE PP perforating press are gone out location hole, adopt hot melt and riveter nail to position simultaneously.
2. the method for a kind of low-cost high-efficiency control multi-layer circuit board platen manufacturing layer deviation according to claim 1 is characterized by: significant data is that A:PP uses OPE PP perforating press to go out positioning hole corresponding during walkthrough, and diameter is 4.5mm.B: play 6 closing-ups again with 4 slotted eye location hot melts earlier.The pressing plate formula: (pressure unit: PSI, temperature unit: ℃) temperature/time: 14,0/5 140,/15 160,/10 160,/11 180,/14,210,/11 210,/34 140/20 pressure/time: 10,0/5 100,/15 250,/10 280,/11 280,/14 280,/11 280/34200/20.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910104877A CN101778535A (en) | 2009-01-09 | 2009-01-09 | Low-cost high-efficiency method for controlling multi-layer circuit board platen manufacturing layer deviation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910104877A CN101778535A (en) | 2009-01-09 | 2009-01-09 | Low-cost high-efficiency method for controlling multi-layer circuit board platen manufacturing layer deviation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101778535A true CN101778535A (en) | 2010-07-14 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910104877A Pending CN101778535A (en) | 2009-01-09 | 2009-01-09 | Low-cost high-efficiency method for controlling multi-layer circuit board platen manufacturing layer deviation |
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| CN (1) | CN101778535A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103249266A (en) * | 2013-04-03 | 2013-08-14 | 胜宏科技（惠州）股份有限公司 | Multilayer circuit board production method capable of preventing layer deviation |
| CN106358387A (en) * | 2016-11-17 | 2017-01-25 | 百硕电脑(苏州)有限公司 | Combining method of PCB inner-layer boards |
| CN106376188A (en) * | 2016-11-01 | 2017-02-01 | 苏州艾美德国际贸易有限公司 | PCB production line and PCB produced by PCB production line |
| CN109511211A (en) * | 2017-09-14 | 2019-03-22 | 深圳市博敏电子有限公司 | Prevent the blast resistance construction and its manufacture craft of edges of boards plate bursting |
| CN109587977A (en) * | 2018-12-14 | 2019-04-05 | 深圳崇达多层线路板有限公司 | A kind of improvement fusion undesirable method of position making sheet |
-
2009
- 2009-01-09 CN CN200910104877A patent/CN101778535A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103249266A (en) * | 2013-04-03 | 2013-08-14 | 胜宏科技（惠州）股份有限公司 | Multilayer circuit board production method capable of preventing layer deviation |
| CN106376188A (en) * | 2016-11-01 | 2017-02-01 | 苏州艾美德国际贸易有限公司 | PCB production line and PCB produced by PCB production line |
| CN106358387A (en) * | 2016-11-17 | 2017-01-25 | 百硕电脑(苏州)有限公司 | Combining method of PCB inner-layer boards |
| CN109511211A (en) * | 2017-09-14 | 2019-03-22 | 深圳市博敏电子有限公司 | Prevent the blast resistance construction and its manufacture craft of edges of boards plate bursting |
| CN109587977A (en) * | 2018-12-14 | 2019-04-05 | 深圳崇达多层线路板有限公司 | A kind of improvement fusion undesirable method of position making sheet |
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Open date: 20100714 |