CN101777502A - Packaging method of inverted chip - Google Patents
Packaging method of inverted chip Download PDFInfo
- Publication number
- CN101777502A CN101777502A CN 200910003642 CN200910003642A CN101777502A CN 101777502 A CN101777502 A CN 101777502A CN 200910003642 CN200910003642 CN 200910003642 CN 200910003642 A CN200910003642 A CN 200910003642A CN 101777502 A CN101777502 A CN 101777502A
- Authority
- CN
- China
- Prior art keywords
- several
- colloid
- template
- mounting method
- flip chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention discloses a packaging method of an inverted chip, at least comprising the following steps of: firstly providing a base plate strip containing at least one base plate unit; then arranging at least one chip on the base plate unit, wherein the chip is electrically connected with the base plate unit; then arranging a template on the upper surface of the base plate strip, wherein an air gap is positioned between the template and the base plate strip, the template is provided with at least one opening and one air-suction slotted hole, the air gap is communicated with the opening and the air-suction slotted hole, and the chip is positioned in the opening; finally forming a colloid on the opening of the template to coat the chip, and evacuating through the air-suction slotted hole and the air gap to prevent air from forming bubbles by being enclosed in the colloid.
Description
[technical field]
The invention relates to a kind of method for packing, particularly avoid air to be coated and form the method for packing of bubble by colloid relevant for a kind of.
[background technology]
Include some glue encapsulation step in the existing method for packing with sealing and protection chip; as shown in Figure 1; after several chips 120 are arranged at a upper surface 111 of a substrate strip 110; utilize some glue instruments 10 to carry out a glue step again; so in a glue step; then easily air tank is overlayed in the packaging structure if the speed control of colloid 130 flow distribution is improper, and cause packaging structure in generation bubble V to make electrical insulating property or poor heat conduction, even influence the useful life of packaging structure.
So, be necessary to provide a kind of flip chip mounting method, to solve the existing in prior technology problem.
[summary of the invention]
Main purpose of the present invention is to provide a kind of flip chip mounting method, air tank is overlayed in the packaging structure avoiding, and then improves the production reliability of packaging structure.
For reaching above-mentioned purpose, the invention provides a kind of flip chip mounting method, it comprises the following step at least: at first, provide one to have the substrate strip an of upper surface and a lower surface, described substrate strip includes a base board unit; Then, a chip is set in described base board unit and electrically connect described base board unit; Afterwards, the described upper surface of one template in described substrate strip is set, has an air gap between described template and the described substrate strip, described template has the slotted eye of bleeding that an opening and that runs through a first surface and a second surface is formed at described second surface, wherein said air gap is communicated with described opening and the described slotted eye of bleeding, and described chip is positioned at described opening; At last, form colloid in the described opening of described template coating described chip, and vacuumize by described slotted eye and the described air gap of bleeding.The present invention vacuumizes in forming the step of colloid, and the feature of utilizing described air gap to be communicated with described opening and the described slotted eye of bleeding extracts the air in the described opening out, residues in the packaging structure to prevent air.
In one embodiment of this invention, described chip is being set in the step of described base board unit, described base board unit has several first connection gaskets, and described chip has an active surface, a back side and several projections, and described several projections connect described several first connection gaskets; And include in addition: form the described upper surface of a underfill (underfill) in described substrate strip, described underfill coats described several projections of described chip, and described underfill appears the described back side of described chip.
In one embodiment of this invention, in the step of described template was set, the described slotted eye of bleeding directly was communicated with described opening in addition.
In one embodiment of this invention, before the step that forms described colloid, other includes: the described first surface of a web plate in described template is set, and described web plate has at least one shade portion and several hollow-out parts, and described shade portion is covered in the described back side of described chip.
In one embodiment of this invention, described colloid appears the described back side of described chip.
In one embodiment of this invention, in the step that forms described colloid, described colloid utilization extruding (Squeeze) method is formed at the described opening of described template.
In one embodiment of this invention, after the step that forms described colloid, other includes: carry out a heating steps to solidify described colloid.
In one embodiment of this invention, before the step of described colloid that is heating and curing, other includes: the step that removes described template.
In one embodiment of this invention, after the step that forms described colloid, described base board unit has several second connection gaskets in addition, and described several second connection gaskets are formed at described lower surface; And include in addition: the described lower surface of several soldered balls in described substrate strip is set, and described several soldered balls connect described several second connection gaskets.
In one embodiment of this invention, after forming the step of described colloid, other includes: cut described substrate strip with form several single from flip chip package structure.
[description of drawings]
Fig. 1: the schematic cross-section that in the step of spot printing formation adhesive body, is full of bubble in the existing flip chip mounting method.
Fig. 2 A to 2I: according to one first specific embodiment of the present invention, a kind of schematic cross-section of flip chip mounting method.
Fig. 3: according to one second specific embodiment of the present invention, another kind of flip chip package structure covers the schematic cross-section of chip back with a web plate.
[embodiment]
See also Fig. 2 A to 2I, disclose a kind of flip chip mounting method according to a specific embodiment of the present invention, at first, see also Fig. 2 A, one substrate strip 210 is provided, described substrate strip 210 includes at least one base board unit 210 ', in the present embodiment, described substrate strip 210 comprises several base board units 210 ', described substrate strip 210 has a upper surface 211 and a lower surface 212, the described upper surface 211 of described substrate strip 210 and described lower surface 212 are the upper surface and the lower surface of described several base board units 210 ', described several base board units 210 ' have several first connection gaskets 213 and several second connection gaskets 214, described several first connection gaskets 213 are formed at described upper surface 211, and described several second connection gaskets 214 are formed at described lower surface 212; Then, see also Fig. 2 B, several chips 220 are set in described several base board units 210 ', each chip 220 has an active surface 221, a back side 222 and several projections 223, and described several projections 223 of described several chips 220 electrically connect described several first connection gaskets 213 of described several base board units 210 '; Afterwards, see also Fig. 2 C, form a underfill 230 (underfill) in the described upper surface 211 of described substrate strip 210, described underfill 230 coats described several projections 223 of described several chips 220, and described underfill 230 appears described several back sides 222 of described several chips 220.
Then, see also Fig. 2 D, the described upper surface 211 of one template 20 in described substrate strip 210 is set, described template 20 has a first surface 21, one second surface 22, at least one opening 23 and at least one slotted eye 24 of bleeding, in the present embodiment, described template 20 has several openings 23, described several opening 23 corresponding described several chips 220, and has an air gap I between the described second surface 22 of described template 20 and the described upper surface 211 of described substrate strip 210, described several openings 23 run through described first surface 21 and described second surface 22, the described slotted eye 24 of bleeding is formed at described second surface 22, described air gap I is communicated with described several openings 23 and the described slotted eye 24 of bleeding, and described several chips 220 are positioned at described several openings 23, perhaps, in another embodiment, the described slotted eye 24 of bleeding can directly be communicated with described several openings 23; Afterwards, see also Fig. 2 E, form colloid 240 (liquid compound) and vacuumize step to coat described chip 220 and to carry out one in described several openings 23 of described template 20, can utilize a scraper 30 that described colloid 240 is tamped in described template 20 in this step, described colloid 240 can utilize extruding (Squeeze) method to be formed at described several openings 23 of described template 20, described colloid 240 coats a madial wall 25 of described several chips 220 and the described template 20 of described colloid 240 contacts, in this step, be communicated with described several openings 23 and the described slotted eye 24 of bleeding by described air gap I, therefore can the extraction of the air described several openings 23 in when forming described colloid 240 in described several openings 23 of described template 20, to prevent that air is coated in the described colloid 240 and the formation bubble.
See also Fig. 3, before the step of the described upper surface 211 of described substrate strip 210, can include in addition the step of a web plate 40 in the described first surface 21 of described template 20 is set forming described colloid 240, described web plate 40 has several shade portions 41 and several hollow-out parts 42, described several shade portions 41 are covered in described several back sides 222 of described several chips 220, to avoid described colloid 240 to be covered in described several back sides 222 of described several chips 220, and after removing described web plate 40, can manifest described several back sides 222 of described several chips 220, have the effect that increases heat radiation.
Then, please continue to consult Fig. 2 F, carrying out a pre-bake step makes 240 one-tenth semi-solid preparation shapes of described colloid and removes described template 20, afterwards, see also Fig. 2 G, carry out a heating steps to solidify described colloid 240, then, see also Fig. 2 H, the described lower surface 212 of several soldered balls 250 in described substrate strip 210 is set, described several soldered balls 250 connect described several second connection gaskets 214.At last, see also Fig. 2 I, cut described substrate strip 210 with form several single from flip chip package structure.The invention reside in the step that forms described colloid 240 and vacuumize, and utilize described air gap I described several openings 23 of connection and the described slotted eye 24 of bleeding that the air in described several openings 23 are extracted out, form bubble to prevent air from being coated by described colloid 240.
The present invention is described by above-mentioned related embodiment, yet the foregoing description is only for implementing example of the present invention.Must be pointed out that disclosed embodiment does not limit the scope of the invention.On the contrary, being contained in the spirit of claims and the modification and impartial setting of scope is included in the scope of the present invention.
Claims (10)
1. flip chip mounting method, it is characterized in that: described flip chip mounting method comprises:
One substrate strip is provided, and described substrate strip includes at least one base board unit, and described substrate strip has a upper surface and a lower surface;
At least one chip is set in described base board unit, described chip electrically connects described base board unit;
The described upper surface of one template in described substrate strip is set, has an air gap between described template and the described substrate strip, described template has a first surface, a second surface, at least one opening and at least one slotted eye of bleeding, described opening runs through described first surface and described second surface, the described slotted eye of bleeding is formed at described second surface, wherein said air gap is communicated with described opening and the described slotted eye of bleeding, and described chip is positioned at described opening; And
Form colloid in the described opening of described template coating described chip, and vacuumize the air in the described opening is extracted out by described slotted eye and the described air gap of bleeding.
2. flip chip mounting method as claimed in claim 1, it is characterized in that: described chip is being set in the step of described base board unit, described base board unit has several first connection gaskets, described chip has an active surface, a back side and several projections, and described several projections connect described several first connection gaskets; And include in addition: form the described upper surface of a underfill in described substrate strip, described underfill coats described several projections of described chip, and described underfill appears the described back side of described chip.
3. flip chip mounting method as claimed in claim 1 is characterized in that: in the step of described template was set, the described slotted eye of bleeding directly was communicated with described opening in addition.
4. flip chip mounting method as claimed in claim 1, it is characterized in that: before the step that forms described colloid, other includes: the described first surface of a web plate in described template is set, described web plate has at least one shade portion and several hollow-out parts, and described shade portion is covered in the described back side of described chip.
5. flip chip mounting method as claimed in claim 4 is characterized in that: after the step that forms described colloid, described colloid appears the described back side of described chip.
6. flip chip mounting method as claimed in claim 1 is characterized in that: in the step that forms described colloid, described colloid utilizes extrusion to be formed at the described opening of described template.
7. flip chip mounting method as claimed in claim 1 is characterized in that: after the step that forms described colloid, other includes: carry out a heating steps to solidify described colloid.
8. flip chip mounting method as claimed in claim 7 is characterized in that: before the step of described colloid that is heating and curing, other includes: the step that removes described template.
9. flip chip mounting method as claimed in claim 1 is characterized in that: after the step that forms described colloid, described base board unit has several second connection gaskets in addition, and described several second connection gaskets are formed at described lower surface; And include in addition: the described lower surface of several soldered balls in described substrate strip is set, and described several soldered balls connect described several second connection gaskets.
10. flip chip mounting method as claimed in claim 1 is characterized in that: after forming the step of described colloid, other includes: cut described substrate strip with form several single from flip chip package structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910003642 CN101777502B (en) | 2009-01-13 | 2009-01-13 | Packaging method of inverted chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910003642 CN101777502B (en) | 2009-01-13 | 2009-01-13 | Packaging method of inverted chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101777502A true CN101777502A (en) | 2010-07-14 |
| CN101777502B CN101777502B (en) | 2011-12-07 |
Family
ID=42513904
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200910003642 Active CN101777502B (en) | 2009-01-13 | 2009-01-13 | Packaging method of inverted chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101777502B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102522343A (en) * | 2011-12-15 | 2012-06-27 | 烟台睿创微纳技术有限公司 | Microcomponent vacuum packaging exhaust device and method |
| CN103098190A (en) * | 2010-09-09 | 2013-05-08 | 超威半导体公司 | Semiconductor chip device with underfill |
| CN104795436A (en) * | 2015-04-28 | 2015-07-22 | 华天科技（昆山）电子有限公司 | Wafer packaging structure, chip packaging structure and packaging method thereof |
-
2009
- 2009-01-13 CN CN 200910003642 patent/CN101777502B/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103098190A (en) * | 2010-09-09 | 2013-05-08 | 超威半导体公司 | Semiconductor chip device with underfill |
| CN102522343A (en) * | 2011-12-15 | 2012-06-27 | 烟台睿创微纳技术有限公司 | Microcomponent vacuum packaging exhaust device and method |
| CN102522343B (en) * | 2011-12-15 | 2014-04-16 | 烟台睿创微纳技术有限公司 | Microcomponent vacuum packaging exhaust device and method |
| CN104795436A (en) * | 2015-04-28 | 2015-07-22 | 华天科技（昆山）电子有限公司 | Wafer packaging structure, chip packaging structure and packaging method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101777502B (en) | 2011-12-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN201226592Y (en) | Silicon microphone packaged by flexible circuit board | |
| CN101777502B (en) | Packaging method of inverted chip | |
| CN112447895A (en) | Full-color SMD LED of reinforcing waterproof performance | |
| CN101740528B (en) | Radiating-enhanced outer pin-free semiconductor packaging structure and combination thereof | |
| CN206312887U (en) | Chip embedded encapsulating structure with closed cavity | |
| CN107079583A (en) | For transmission control module, the method for the TCU components that are used in this transmission control module and for manufacturing this transmission control module used in the medium of pollution | |
| CN103762200B (en) | Chip package and method for packing thereof | |
| CN101026133A (en) | Semiconductor package structure with radiating fin and its manufacturing method | |
| CN104254190B (en) | The preparation method of circuit board | |
| CN100533721C (en) | Chip packaging structure and method of producing the same | |
| CN101826495B (en) | Window-shaped semiconductor encapsulation structure | |
| CN206505948U (en) | The sheet-shaped LED device and its display screen of a kind of high moisture | |
| CN212587519U (en) | LED wafer packaging structure | |
| CN101226888A (en) | Heat sinking type chip packaging technology and constitution | |
| CN102709199B (en) | Mold array process method for covering side edge of substrate | |
| CN2567768Y (en) | Encapsulation structure for chip on base plate | |
| CN105390477B (en) | A kind of multi-chip 3 D secondary encapsulation semiconductor devices and its packaging method | |
| CN210607238U (en) | Integrated chip packaging plastic lead support | |
| CN110493954B (en) | QFN device embedded PCB structure and manufacturing method thereof | |
| CN101556940B (en) | Semiconductor encapsulating structure with radiation fins | |
| CN207637845U (en) | A kind of simple semiconductor package, SAW filter and terminal device | |
| CN104220365A (en) | Cavity package design | |
| CN102299213A (en) | Light emitting diode (LED) polycrystalline packaging substrate and manufacturing method thereof | |
| CN208923105U (en) | Surface-adhered type semiconductor devices | |
| CN106952990A (en) | A kind of chip-scale LED package device and its manufacture craft |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |