CN101764115A - Conducting structure for semiconductor integrated circuit and forming method thereof - Google Patents
Conducting structure for semiconductor integrated circuit and forming method thereof Download PDFInfo
- Publication number
- CN101764115A CN101764115A CN200910266817A CN200910266817A CN101764115A CN 101764115 A CN101764115 A CN 101764115A CN 200910266817 A CN200910266817 A CN 200910266817A CN 200910266817 A CN200910266817 A CN 200910266817A CN 101764115 A CN101764115 A CN 101764115A
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- China
- Prior art keywords
- conductive layer
- liner
- projection
- integrated circuit
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 title abstract description 10
- 239000010410 layer Substances 0.000 claims description 67
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 claims description 22
- 239000011241 protective layer Substances 0.000 claims description 21
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 20
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 230000004308 accommodation Effects 0.000 claims 2
- 238000005516 engineering process Methods 0.000 description 12
- 238000009713 electroplating Methods 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000007747 plating Methods 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910001080 W alloy Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005246 galvanizing Methods 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
Images
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention relates to a conducting structure for a semiconductor integrated circuit and a forming method thereof. The semiconductor integrated circuit comprises a gasket and a protection layer, wherein the protection layer locally covers the gasket so as to define a first opening area with a first transverse size and ensure that the conducting structure is suitable for passing through the first opening area to be electrically connected with the gasket. The conducting structure covers the first opening area and a part of the protection layer so as to provide conducting property with lower impedance between the gasket and a bump, and meanwhile, the conducting structure on other positions of the protection layer has no break points and also has the characteristic for ensuring the conduction to be more stable.
Description
The application be the applicant on February 16th, 2007 submit to, application number be 200710084091.1, denomination of invention divides an application for the application for a patent for invention of " being used for conductive structure of semiconductor integrated circuit and forming method thereof ".
Technical field
The present invention is a kind of conductive structure; Particularly a kind of conductive structure that is used for the semiconductor integrated circuit and forming method thereof.
Background technology
Projection is plated on microelectronics (microelectronics) and micro-system fields such as (micro system) have been developed and many technology, such as flat-panel screens (flat panel displays, FPD) with being connected of chip for driving (driverICs), GaAs chip on call wire and gas bridge (air bridges) technology and LIGA technology in the making etc. of X-ray light shield, all use this projection electroplating technology in different phase.
With the example that is connected to of circuit board and IC chip, the IC chip can utilize variety of way to be connected with circuit board, and its packaged type mainly is to utilize projection (particularly golden projection) electroplating technology, and liner in the IC chip and circuit board are electrically connected.This technology not only can significantly be dwindled the volume of IC chip, and it can directly be embedded on the circuit board, has to save characteristics such as space, low induction and heat-sinking capability be good, adds the low-cost advantage of electroplating technology, and it is flourish to cause the projection electroplating technology to be able to.
Typical projection electroplating technology, for example golden projection electroplating technology, need on liner, form a underlying metal (under bump metal) in advance, underlying metal is except that the adhesion layer as engagement protrusion and liner, also usually with a conductive layer electrically connect, wherein this conductive layer can form respectively or simultaneously with underlying metal, also can utilize same process and material to form, with after electroplating the formation projection, jointly as the usefulness of conductive media, make projection can be formed at the underlying metal top smoothly, and by underlying metal and liner electrically connect.So before electroplating beginning, needing elder generation at chip surface, other places except liner form a plurality of conductive layers, after the projection plating is finished, utilize etching mode again, and those conductive layers are removed.
So in fact,, therefore when conductive layer is formed at rough surface, therefore produces breakpoint easily and can't conduct electricity, perhaps differ, and cause the resistance increase of conductive layer because of thickness everywhere because chip surface may have the part rough surface.For addressing the above problem, prior art forms thicker conductive layer and the underlying metal of average thickness, to improve the disappearance that may produce breakpoint when conductive layer forms.But its equivalent resistance of underlying metal that thickness increases can increase, and because the underlying metal major function is the adhesion layer as projection and liner, its impedance itself is promptly higher, therefore as the underlying metal of adhesion layer, if have thicker degree, with making the impedance between projection and the liner increase, be unfavorable for the electrically connect of chip and circuit board.Above-mentioned situation all can influence electroplating effect, and the yield that projection is electroplated reduces, and need carry out back processing reformation or discarded this chip.
Because form the conductive characteristic that conductive layer does not influence underlying metal again, still belong to unsolved technology, the invention provides following technological break-through, to address the above problem.
Summary of the invention
A purpose of the present invention is to provide a kind of conductive structure that is used for the semiconductor integrated circuit; this semiconductor integrated circuit comprises a liner and a protective layer; local this liner that covers; to define one first open area with one first lateral dimension; make this conductive structure fit and to pass through this first open area, be electric connection with this liner.This conductive structure covers this first open area and this protective layer of part, to provide liner more low-impedance conductive layer.
Another object of the present invention is to provide a kind of conductive structure that is used for the semiconductor integrated circuit, and this semiconductor integrated circuit comprises a liner and a protective layer, to form no breakpoint and the conductive layer with stable resistance conductive layer characteristic on protective layer.
For reaching above-mentioned purpose, the present invention discloses a kind of conductive structure, comprises one first conductive layer and one second conductive layer.This first conductive layer is formed on this protective layer, and corresponds to this first open area, and definition has one second open area of one second lateral dimension, and wherein this second lateral dimension is not less than this first lateral dimension.This second conductive layer mainly is formed in this first open area, and to be electric connection with this liner, wherein this second conductive layer covers the zone, an edge of this first conductive layer and the zone, an edge of this protective layer continuously.
The present invention also discloses a kind of method that forms above-mentioned conductive structure on the semiconductor integrated circuit, and this semiconductor integrated circuit comprises a liner, and a protective layer, and local this liner that covers is to define one first open area with one first lateral dimension.Said method comprises the following step: form one first conductive layer, with corresponding this first open area, definition one has second open area of one second lateral dimension; Form one second conductive layer in this first open area, can be electric connection by this first open area and this liner so that this second conductive layer is suitable; Wherein this second conductive layer is to be formed up to the zone, an edge of this first conductive layer of covering and the zone, an edge of this protective layer continuously.For above-mentioned purpose of the present invention, technical characterictic and advantage can be become apparent, will be elaborated with the preferred embodiment conjunction with figs. below.
Description of drawings
Fig. 1 (a) is the process schematic representation of preferred embodiment of the present invention to the 1st (h), and it also discloses the structural representation of preferred embodiment of the present invention.
Embodiment
Fig. 1 (a) shows a preferred embodiment of the present invention to Fig. 1 (h), and it is a kind of formation schematic flow sheet that is used for the conductive structure of semiconductor integrated circuit.
Fig. 1 (a) shows initial fabrication schedule, and it at first forms a liner 11 and a protective layer 12.Liner 11 is made of aluminum in the present embodiment; and these protective layer 12 local these liners 11 that cover; so that this liner 11 is exposed defining one first open area, with as after with projection electric connection window, wherein this first open area has one first lateral dimension W1.Because protective layer 12 covers the edge of liner 11, first open area is less than the lateral dimension of liner.
Then form one first conductive layer, for example a titanium-tungsten conductive layer 13 covers this first open area during its formation, and extends on the protective layer 12; Shown in Fig. 1 (b), this titanium-tungsten conductive layer 13 will form a recessed zone naturally by covering the part of this first open area.
Afterwards, near the titanium-tungsten conductive layer 13 that covers first open area is removed, for example utilized etching mode to carry out, make titanium-tungsten conductive layer 13 on first open area, form one second open area, appear this protective layer 12 with part optionally.At this moment, this second open area has one second lateral dimension W2, and shown in Fig. 1 (c), wherein W2 is more than or equal to W1, fully to expose this first open area.Under the situation of W2 greater than W1, suitable protective layer 12 and the titanium-tungsten conductive layer 13 of can making in second open area and first open area forms a stepped profile.
Then form one second conductive layer (i.e. a bottom metal layer) on titanium-tungsten conductive layer 13, it also can be a titanium-tungsten conductive layer 14, covers this second open area and this first open area, with liner 11 electrically connects.Shown in Fig. 1 (d), this titanium-tungsten conductive layer 14 will present a staged recessed area naturally by covering the part of this first and second open area; Because this titanium-tungsten conductive layer 14 forms continuously covering the edge of first open area and second open area, so needed good conductive path when following projection formation is provided.
Structure shown in Fig. 1 (d) is formed in first open area and electrically connects part with liner, only has the thin titanium layer tungsten alloy, and promptly the titanium-tungsten conductive layer 14, as underlying metal; Simultaneously, on protective layer, the conductive layer of conductive path is contained two layers of titanium-tungsten layer during as plating, and promptly the titanium-tungsten conductive layer 13,14; So when semiconductor chip surface was more coarse, this thicker conductive layer does not have breakpoint in the time of can guaranteeing to conduct electricity takes place, and on conductive layer, provides stable resistance, helps follow-up galvanizing process and carries out.
Then form a photoresist layer 15 and cover chip comprehensively, and will form the photoresistance removal at projection place, form a space, shown in Fig. 1 (e).
Then, be to utilize plating mode to form projection 16, the titanium-tungsten conductive layer 14 that projection 16 is covered on first open area and second open area is to electrically connect with titanium-tungsten conductive layer 14, shown in Fig. 1 (f).In the present embodiment, projection 16 is to be made of gold, and projection 16 has one the 3rd lateral dimension W3, and W3 is greater than W2, make projection 16 cover this second open area fully, at this moment, one deck titanium-tungsten conductive layer 14 is only arranged, can effectively lower the conduction impedance that underlying metal (being titanium-tungsten conductive layer 14) causes projection 16 with the liner contact portion.
Then remove photoresist layer 15, shown in Fig. 1 (g); Then remove unwanted titanium-tungsten conductive layer 13,14 at last, only stay the part titanium-tungsten conductive layer between projection 16 and the liner 11, shown in Fig. 1 (h).
In the present embodiment, second conductive layer is as underlying metal, and first conductive layer be as intermediate conductive layer with the conducting electric current, both are neither to be limited to by titanium-tungsten madely, for example can only utilize titanium to make.Simultaneously also can corresponding different chip situation, surface roughness difference for example, the zone beyond liner forms two-layer above conductive layer, but still only retains a single underlying metal, makes projection and liner carry out very perfect electrically connect.
By above-mentioned announcement, conductive structure of the present invention is suitable can be used on the protective layer, forms the design of two layers of titanium-tungsten conductive layer 13,14, the conductive layer of required adequate thickness in the time of can guaranteeing to electroplate, and unlikely generation breakpoint is to provide stable conduction impedance operator; With the liner contact portion, also only there is single titanium-tungsten conductive layer 14 simultaneously, can effectively lowers the conduction impedance between liner and the projection again, and then improve the reliability of conductive structure.
The above embodiments only are used for exemplifying enforcement aspect of the present invention, and explain technical characterictic of the present invention, open the non-protection category of the present invention that is used for limiting.Any be familiar with this operator can unlabored change or the arrangement of the isotropism scope that all belongs to the present invention and advocated, the scope of the present invention should be as the criterion with the application's claim scope.
Claims (4)
1. conductive structure that is used for the semiconductor integrated circuit, wherein this semiconductor integrated circuit comprises a liner and a protective layer, local this liner that covers, this protective layer has zone, an edge, and to define an exposed region of this liner, this conductive structure comprises:
At least one intermediate conductive layer has zone, an edge, is formed at the top of this protective layer, the fringe region of this protective layer and the fringe region of this at least one intermediate conductive layer, and order forms a stepped profile, and defines an accommodation space;
One underlying metal, this underlying metal contacts with this exposed region, and extends the fringe region of this protective layer of covering and the fringe region of this at least one intermediate conductive layer continuously; And
One projection corresponding to this exposed region, is formed on this underlying metal.
2. conductive structure as claimed in claim 1 is characterized in that this projection fully laterally is covered on this accommodation space.
3. conductive structure as claimed in claim 2 is characterized in that this projection is a gold medal projection.
4. conductive structure as claimed in claim 1, it is characterized in that this at least one intermediate conductive layer and this underlying metal at least one of them, be to make by titanium-tungsten.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009102668172A CN101764115B (en) | 2007-02-16 | 2007-02-16 | Conducting structure for semiconductor integrated circuit and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009102668172A CN101764115B (en) | 2007-02-16 | 2007-02-16 | Conducting structure for semiconductor integrated circuit and forming method thereof |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007100840911A Division CN101246863B (en) | 2007-02-16 | 2007-02-16 | Conductive structure for semiconductor integrated circuit and method for forming the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101764115A true CN101764115A (en) | 2010-06-30 |
| CN101764115B CN101764115B (en) | 2011-09-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009102668172A Expired - Fee Related CN101764115B (en) | 2007-02-16 | 2007-02-16 | Conducting structure for semiconductor integrated circuit and forming method thereof |
Country Status (1)
| Country | Link |
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| CN (1) | CN101764115B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102456647A (en) * | 2010-10-14 | 2012-05-16 | 台湾积体电路制造股份有限公司 | Conductive pillar structure |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6380084B1 (en) * | 2000-10-02 | 2002-04-30 | Chartered Semiconductor Manufacturing Inc. | Method to form high performance copper damascene interconnects by de-coupling via and metal line filling |
| KR100796795B1 (en) * | 2001-10-22 | 2008-01-22 | 삼성전자주식회사 | Contact portion of semiconductor device and method for manufacturing the same, and thin film transistor array panel for display device including the contact portion and method for manufacturing the same |
| CN100416875C (en) * | 2005-03-30 | 2008-09-03 | 南茂科技股份有限公司 | Structure of package using coupling and its forming method |
-
2007
- 2007-02-16 CN CN2009102668172A patent/CN101764115B/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102456647A (en) * | 2010-10-14 | 2012-05-16 | 台湾积体电路制造股份有限公司 | Conductive pillar structure |
| CN102456647B (en) * | 2010-10-14 | 2014-12-03 | 台湾积体电路制造股份有限公司 | Conductive pillar structure |
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| Publication number | Publication date |
|---|---|
| CN101764115B (en) | 2011-09-14 |
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Granted publication date: 20110914 |