CN101110366A

CN101110366A - Semiconductor substrate with bare conducting circuit and forming method thereof

Info

Publication number: CN101110366A
Application number: CN 200610099255
Authority: CN
Inventors: 陈家庆
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2006-07-21
Filing date: 2006-07-21
Publication date: 2008-01-23

Abstract

The invention discloses a semiconductor basal plate with naked lead circuit and the forming method. The semi-conductor basal plate comprises a main body of a basal plate, at least a conductance line, a metallic layer that is formed on the main body of the basal plate is covered on partial section of the conductance line and a welding prevention layer that is covered on another section not covered by the metallic layer. Wherein, the welding prevention layer does not cover the metallic layer, which resolves the problem of stripping between the existing welding prevention layer and he conductance line.

Description

Has semiconductor substrate of bare conducting circuit and forming method thereof

Technical field

The present invention relates to a kind of semiconductor substrate and forming method thereof, particularly a kind of semiconductor substrate and forming method thereof with bare conducting circuit.

Background technology

Please refer to Fig. 1, it is a view on existing ball lattice array (BGA) base plate for packaging 100.Base plate for packaging 100 has on the 101 surperficial 100a formed thereon of a plurality of conducting wires (conductive lines), and a welding resisting layer 102 is covered on the part section (not shown) of upper surface 100a and conducting wire 101.Each conducting wire 101 have another part section (also be called welding finger (finger)) 101a concurrently Arranged rings be around in around the chip setting area 104, and distinctly be exposed on four opening 102a of welding resisting layer 102.Chip setting area 104 is in order to be provided with semiconductor chip (not shown).

Generally speaking, be exposed to and be electroplate with a gold medal (Au) layer on the surface of each the part section 101a on the opening 102a, in case oxidation, and can the routing mode and be electrically connected to semiconductor chip (not shown) on the chip setting area 104.Fig. 2 a and Fig. 2 b are along the profile of A-A line, in order to two kinds of formed gold layers 106 of different manufacturing process to be described among Fig. 1.

Now please refer to Fig. 2 a, gold layer 106 is plated on the whole piece conducting wire 101, and the gold-plated technology of this kind is called golden pattern plating (gold pattern plating, GPP) manufacturing process usually.Yet GPP manufacturing process need be used more gold (Au), thereby can increase manufacturing cost.Moreover, because welding resisting layer 102 is not good with the adhesive force of 106 on gold layer, so welding resisting layer 102 is peeled off (delamination) by conducting wire 101 problem can take place usually.

Now please refer to Fig. 2 b, gold layer 106 is plated on the part section 101a of conducting wire 101, and the gold-plated technology of this kind is called selectivity gold-plated (selectivity gold) manufacturing process usually.Compared to above-mentioned GPP manufacturing process, the gold-plated manufacturing process of selectivity can reduce the use amount of gold (Au), to save manufacturing cost.Yet, since gold layer 106 some be covered in welding resisting layer 102 times, therefore still have the problem that above-mentioned welding resisting layer 102 is peeled off by conducting wire 101.

Summary of the invention

The technical problem that institute of the present invention desire solves is to provide a kind of semiconductor substrate with bare conducting circuit, in order to solve the problem that existing welding resisting layer is peeled off by the conducting wire.Another technical problem that institute of the present invention desire solves is to provide a kind of formation method of aforesaid semiconductor substrate.

In order to solve above-mentioned purpose, the invention provides a kind of semiconductor substrate with bare conducting circuit, it comprises a base main body, at least one conducting wire, be formed on the base main body, a metal level, be covered on a part of section of conducting wire and a welding resisting layer, be covered on another part section of conducting wire, but do not cover metal level, to strengthen the adhesive force between welding resisting layer and conducting wire.

For solving the problem of second half conductor substrate formation method, the invention provides a kind of formation method of above-mentioned semiconductor substrate, it comprises: a substrate is provided; Form metallic conduction on substrate, the conducting wire is divided into one first section, one second section and one the 3rd section, and wherein second section is between between first section and the 3rd section; Form a screen, cover first section and second section, and the 3rd section is exposed to outside the screen; Form a metal level, be covered on the 3rd section; Peel off screen; And form a welding resisting layer (solder mask), and be covered on first section of conducting wire, make second section be exposed to welding resisting layer and metal interlevel.

Semiconductor substrate according to the present invention and forming method thereof, metal level is preferably gold (Au) layer, and owing to welding resisting layer is not covered on the gold layer, so between welding resisting layer and conducting wire preferable adhesive force can be arranged, to solve the problem that existing welding resisting layer is peeled off by the conducting wire.

Description of drawings

Fig. 1 is the simple vertical view of existing ball lattice array (BGA) base plate for packaging;

Fig. 2 a to Fig. 2 b is along the profile of A-A line among Fig. 1;

Fig. 3 is the generalized section of first embodiment of the present invention's semiconductor substrate;

Fig. 4 to Fig. 7 is the formation method schematic diagram of the present invention's semiconductor substrate.

Wherein, description of reference numerals is as follows:

100 base plate for packaging

101 conducting wires

101a part section

The 100a upper surface

102 welding resisting layers

The 102a opening

104 chip setting areas

106 gold medal layers

200 semiconductor substrates

202 base main body

The 202a upper surface

The 202b lower surface

204 conducting wires

204a, 204b, 204c section

206 welding resisting layers

206a chip setting area

207 openings

208 metal levels

210 screens

The 210a opening

Embodiment

Fig. 3 is the generalized section according to the semiconductor substrate 200 of one embodiment of the invention.The semiconductor substrate 200 of this embodiment with ball lattice array (BGA) base plate for packaging as an illustration.In addition, semiconductor substrate 200 is a summary schematic diagram, and it is only in order to illustrating the last structure of surperficial 202a on the base main body 202, and structures such as relevant conducting wire that other is gone up as conduction plated-through-hole and lower surface 202b thereof and welding resisting layer are not given unnecessary details at this.

Semiconductor substrate 200 has comprised base main body 202, a plurality of (only representing two) conducting wires 204, is formed at that surperficial 202a on the base main body 202 goes up and a welding resisting layer (solder mask) 206 is covered on the part section of surperficial 202a and each conducting wire 204 on the base main body 202.The formation purpose of welding resisting layer 206 mainly is for the conducting wire on the protective substrate main body 202 204, avoids because of scratch causes short circuit or breaking phenomena, and therefore reaches the function of " anti-welding ".In addition, welding resisting layer 206 has plurality of openings 207, part section in order to exposed each conducting wire 204 defines the central portion that a chip setting area 206a is positioned at surperficial 202a on the base main body 202, simultaneously so that semiconductor chip (not shown) to be set thereon.

In this embodiment, each conducting wire 204 is formed by copper, and can be divided into three

section

204a, 204b and 204c does explanation.This section 204a is covered in welding resisting layer 206 times, and can be electrically connected under the base main body 202 on the surperficial 202b because of plural conductive plated-through-hole (not shown).Section 204b and section 204c are exposed on the opening 207 of welding resisting layer 206, make that being positioned at the last semiconductor chip (not shown) of chip setting area 206a can be electrically connected on one of the section 204c welding region by routing manufacturing process, electrically connect with conducting wire 204 by this.Welding region refers to the zone that metal wire in the routing manufacturing process and section 204c electrically connect in this embodiment, also can be described as welding finger (can with reference to shown in the label 101a of the 1st figure).In addition, be formed with a metal level 208 on the section 204c, be preferably a gold medal (Au) layer or be a nickel/gold layer, preventing the section 204c oxidation of conducting wire 204, and the electric connection characteristic of raising section 204c.Moreover section 204b is exposed to 208 of welding resisting layer 206 and metal levels.

In semiconductor substrate 200 of the present invention, welding resisting layer 206 only is covered on the section 204a of conducting wire 204, but does not cover metal level 208.Therefore, golden pattern for prior art is electroplated (goldpattern plating, GPP) the formed substrate of gold-plated (selectivity gold) manufacturing process of manufacturing process and selectivity, welding resisting layer 206 has preferable adhesive force with conducting wire 204, can't cause the phenomenon of peeling off (delamination).

Fig. 4 to Fig. 7 is in order to the formation method of the semiconductor substrate 200 of explanation according to the present invention.

At first, as shown in Figure 4, the upper surface 202a at a substrate 202 forms a metal conducting layer, again via manufacturing process such as existing little shadow, etchings and form a plurality of conducting wires 204.

Then, as shown in Figure 5, on the upper surface 202a of substrate 202, form on the part section that a screen 210 is covered in conducting wire 204.Screen 210 has plurality of openings 210a, and a section 204c of conducting wire 204 is exposed to outside the opening 210a.

Afterwards, as shown in Figure 6,, in opening 210a, form a metal level 208 and be covered on the section 204c of conducting wire 204 because of electroplating manufacturing process.

Then, as shown in Figure 7, peel off screen 210, make that the part section of conducting wire 204 is exposed to outside, wherein the part section is divided into two sections in addition,

i.e. section

204a and 204b.

At last, on the section 204a of conducting wire 204, cover a welding resisting layer 206, and exposed section 204b, make section 204b be exposed to 206 of metal level 208 and welding resisting layers, as shown in Figure 3.

Should be appreciated that, not exceed that the substrate that other is any to have welding resisting layer and a conducting wire all can be because of the present invention's method, and solves the problem that welding resisting layer is peeled off by the conducting wire with ball lattice array base plate for packaging according to the semiconductor substrate in the embodiment of the invention 200.

The above only is the present invention's preferred embodiment wherein, is not to be used for limiting practical range of the present invention; Be that all equalizations of doing according to claim of the present invention change and modification, be all claim of the present invention and contain.

Claims

1. the semiconductor substrate with bare conducting circuit is characterized in that, this semiconductor substrate with bare conducting circuit comprises:

One base main body has at least one surface;

One conducting wire is formed on this surface, and this conducting wire has one first section, one second section and one the 3rd section, and wherein this second section is between between this first section and the 3rd section;

One metal level is covered on the 3rd section of this conducting wire; And

One welding resisting layer (solder mask) is covered on first section of this conducting wire;

Wherein second section of this conducting wire is exposed at this welding resisting layer and this metal interlevel.

2. the semiconductor substrate with bare conducting circuit as claimed in claim 1 is characterized in that this metal level is exposed to outside this welding resisting layer fully.

3. the semiconductor substrate with bare conducting circuit as claimed in claim 1 is characterized in that this metal level is a gold medal (Au) layer or nickel and gold (Ni-Au) layer.

4. the semiconductor substrate with bare conducting circuit as claimed in claim 1 is characterized in that the 3rd section has a welding region, in order to be electrically connected to the semiconductor assembly.

5. the semiconductor substrate with bare conducting circuit as claimed in claim 4 is characterized in that, this welding region is a welding finger (finger).

6. the formation method of a semiconductor substrate is characterized in that, this method may further comprise the steps:

One substrate is provided;

Form at least one metallic conduction on this substrate, this conducting wire has one first section, one second section and one the 3rd section, and wherein this second section is between between this first section and the 3rd section;

Form a metal level, be covered on the 3rd section of this conducting wire; And

Form a welding resisting layer (solder mask), be covered on first section of this conducting wire, make this second section be exposed to this welding resisting layer and this metal interlevel.

7. the formation method of semiconductor substrate as claimed in claim 6, it is characterized in that, before the step that forms this metal level, more comprise: form a screen, cover first section and second section of this conducting wire, and the 3rd section is exposed to outside this screen.

8. the formation method of semiconductor substrate as claimed in claim 7 is characterized in that, after the step that forms this metal level, more comprises: peel off this screen.

9. the formation method of semiconductor substrate as claimed in claim 6 is characterized in that, this metal level is a gold medal (Au) layer or nickel and gold (Ni-Au) layer.

10. the formation method of semiconductor substrate as claimed in claim 6 is characterized in that this metal level forms because of plating mode, and is covered on the 3rd section of this conducting wire.