US20030164303A1 - Method of metal electro-plating for IC package substrate - Google Patents

Method of metal electro-plating for IC package substrate Download PDF

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Publication number
US20030164303A1
US20030164303A1 US10289312 US28931202A US2003164303A1 US 20030164303 A1 US20030164303 A1 US 20030164303A1 US 10289312 US10289312 US 10289312 US 28931202 A US28931202 A US 28931202A US 2003164303 A1 US2003164303 A1 US 2003164303A1
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US
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Application
Patent type
Prior art keywords
package substrate
plating
electro
circuit
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10289312
Inventor
Fu-Yu Huang
Yu-Chun Huang
Chin-Hui chuang
Ya-Shin Tseng
Chi-Ju Chiang
Pei-Fen Hung
Wei-Yin Lee
Shu-Hui Lo
Che-Chen Chen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Orient Semiconductor Electronics Ltd
Original Assignee
Orient Semiconductor Electronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/24Reinforcing the conductive pattern
    • H05K3/243Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0335Layered conductors or foils
    • H05K2201/0352Differences between the conductors of different layers of a multilayer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14Related to the order of processing steps
    • H05K2203/1476Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061Etching masks
    • H05K3/064Photoresists
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • H05K3/282Applying non-metallic protective coatings for inhibiting the corrosion of the circuit, e.g. for preserving the solderability
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/425Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/427Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates

Abstract

A method of metal-electro-plating for IC package substrate comprising the steps of: forming vias on the package substrate coated with copper film on both sides thereof; electro-plating the vias to form electrical conductive holes between the top layer and the bottom layer of the package substrate; coating a resisting agent where the patterns should be formed on the top layer and on the entire bottom layer of the package substrate; etching the pattern to form circuit without plating lines on the top layer of the substrate, and removing the resisting agent; coating with a resisting agent on the top side and the bottom side of the package substrate but the wiring position to be electro-plated as surface finish for wire-bonding electro-plating on the top side of the package substrate not being applied with the resisting agent; electro-plating the substrate with nickel and gold, and removing the resisting agent; fabricating the circuit on the bottom side of the package substrate and coating with a resisting agent to cover the entire top side and where the circuit is to be formed on the bottom side; etching the substrate to obtain the circuit on the bottom side of the package substrate; and coating solder resist on the region other than the circuit section and applying pre-flux onto the circuit section to form into a protective film.

Description

    BACKGROUND OF THE INVENTION
  • (a) Technical Field of the Invention [0001]
  • The present invention relates to a metal electro-plating for IC package substrate, and in particular, to a method of electro-plating metal to form a circuit. [0002]
  • (b) Description of the Prior Art [0003]
  • FIGS. 1A and 1B show a conventional dual surface package substrate where the circuits on each layer are connected with plated through holes. The electro-plating method of the substrate is normally the conventional type where at an appropriate position, an electro-plating lead is extended to the plating bar and is then cut off upon completion. At this instance plating tails remain on the substrate and such residues will generate heat while working. In addition, noise will be generated to affect the integrity of signal. [0004]
  • Accordingly, a main object of the present invention is to provide a method of metal electro-plating for IC package substrate, which overcomes the above-mentioned drawbacks. [0005]
  • SUMMARY OF THE INVENTION
  • The present invention relates to a metal electro-plating for IC package substrate, and in particular, to a method of electro-plated metal to form a circuit. [0006]
  • Accordingly, it is an object of the present invention to provide a method of metal electro-plating for IC package substrate, wherein the copper film layer of the bottom layer of the package substrate is used as plating bar such that the circuit on the top side of the substrate does not require electro-plating lead wires and no residual lead wires are left over the substrate which causes unnecessary heat and noise. [0007]
  • Yet a further object of the present invention is to provide a method of metal electro-plating IC package substrate, wherein the top side and the lateral sides of the electro-plated layer can be completely covered, and the quality of the circuit will not be damaged in the following processes of substrate manufacturing. [0008]
  • The foregoing object and summary provide only a brief introduction to the present invention. To fully appreciate these and other objects of the present invention as well as the invention itself, all of which will become apparent to those skilled in the art, the following detailed description of the invention and the claims should be read in conjunction with the accompanying drawings. Throughout the specification and drawings identical reference numerals refer to identical or similar parts. [0009]
  • Many other advantages and features of the present invention will become manifest to those versed in the art upon making reference to the detailed description and the accompanying sheets of drawings in which a preferred structural embodiment incorporating the principles of the present invention is shown by way of illustrative example. [0010]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1A is a schematic view showing the residual lead wire of a metal electro-plating in a conventional package substrate. [0011]
  • FIG. 1B is a sectional view of FIG. 1A. [0012]
  • FIGS. 2A to I are schematic views showing the metal electro-plating method in accordance with the present invention. [0013]
  • DETAILED DESCRIPTION OF THE PRESENT INVENTION
  • The following descriptions are of exemplary embodiments only, and are not intended to limit the scope, applicability or configuration of the invention in any way. Rather, the following description provides a convenient illustration for implementing exemplary embodiments of the invention. Various changes to the described embodiments may be made in the function and arrangement of the elements described without departing from the scope of the invention as set forth in the appended claims. [0014]
  • Referring to FIG. 2, the method of metal electro-plating for IC package substrate. In accordance with the present invention, the method of metal electro-plating for IC package substrate comprises the steps of: [0015]
  • (a) forming vias [0016] 4 on the package substrate 1 coated with copper film 11 on both sides thereof (shown as FIG. 2A);
  • (b) electro-plating the vias [0017] 4 to form electrical conductive holes between the top layer and the bottom layer of the package substrate 1 (referring to FIG. 2B);
  • (c) coating a resisting agent [0018] 2 where the patterns should be formed on the top layer and on the entire bottom layer of the package substrate 1 (referring to FIG. 2C);
  • (d) etching the pattern to form circuit [0019] 3 without plating lines on the top layer of the substrate 1, and removing the resisting agent 2 (referring to FIG. 2D);
  • (e) coating with a resisting agent [0020] 4 on the top side and the bottom side of the package substrate 1 but the wiring position to be electro-plated as surface finish for wire-bonding electro-plating on the top side of the package substrate not being applied with the resisting agent 4 (as shown in FIG. 2E);
  • (f) Electro-plating the substrate with nickel and gold (layer [0021] 31), and removing the resisting agent 4;
  • (g) fabricating the circuit [0022] 32 on the bottom side of the package substrate 1 and coating with a resisting agent 4 to cover the entire top side and where the circuit 32 is to be formed on the bottom side (referring to FIG. 2G);
  • (h) etching the substrate [0023] 1 to obtain the circuit 32 on the bottom side of the package substrate 1 (referring to FIG. 2H); and
  • (i) coating solder resist [0024] 2 on the region other than the circuit section 31 and 32 and applying pre-flux onto the circuit section 32 to form into a protective film 6 (referring to FIG. 2I).
  • In view of the present invention, an electro-plated metallic circuit without plating lines on the package substrate is obtained and the electro-plated metal perfectly covers the top face and lateral face of the copper wire. Thus short circuit due to lateral etching can be avoided. [0025]
  • It will be understood that each of the elements described above, or two or more together may also find a useful application in other types of methods differing from the type described above. [0026]
  • While certain novel features of this invention have been shown and described and are pointed out in the annexed claim, it is not intended to be limited to the details above, since it will be understood that various omissions, modifications, substitutions and changes in the forms and details of the device illustrated and in its operation can be made by those skilled in the art without departing in any way from the spirit of the present invention. [0027]

Claims (1)

    I claim:
  1. 1. A method of metal electro-plating for IC package substrate comprising the steps of:
    (a) forming vias on the package substrate coated with copper film on both sides thereof;
    (b) electro-plating the vias to form electrical conductive holes between the top layer and the bottom layer of the package substrate;
    (c) coating a resisting agent where the patterns should be formed on the top layer and on the entire bottom layer of the package substrate;
    (d) etching the pattern to form circuit without plating lines on the top layer of the substrate, and removing the resisting agent;
    (e) coating with a resisting agent on the top side and the bottom side of the package substrate but the wiring position to be electro-plated as surface finish for wire-bonding electro-plating on the top side of the package substrate not being applied with the resisting agent;
    (f) electro-plating the substrate with nickel and gold, and removing the resisting agent;
    (g) fabricating the circuit on the bottom side of the package substrate and coating with a resisting agent to cover the entire top side and where the circuit is to be formed on the bottom side;
    (h) etching the substrate to obtain the circuit on the bottom side of the package substrate; and
    (i) coating solder resist on the region other than the circuit section and applying pre-flux onto the circuit section to form into a protective film.
US10289312 2002-03-04 2002-11-07 Method of metal electro-plating for IC package substrate Abandoned US20030164303A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW091104213 2002-03-04
TW91104213A TW544877B (en) 2002-03-04 2002-03-04 Method for electroplating IC encapsulated substrate

Publications (1)

Publication Number Publication Date
US20030164303A1 true true US20030164303A1 (en) 2003-09-04

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Country Status (2)

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US (1) US20030164303A1 (en)
JP (1) JP2003253486A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060102384A1 (en) * 2004-10-27 2006-05-18 Ibiden Co., Ltd. Multilayer printed wiring board and manufacturing method of the multilayer printed wiring board
US20070045834A1 (en) * 2005-08-31 2007-03-01 Micron Technology, Inc. Interconnecting substrates for microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100660027B1 (en) 2006-01-25 2006-12-14 삼성전기주식회사 Manufacturing method of printed circuit board using electrolytic plating lead
CN101932206B (en) 2009-06-25 2012-06-13 富葵精密组件(深圳)有限公司 Fabrication method of multi-layer circuit board

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060102384A1 (en) * 2004-10-27 2006-05-18 Ibiden Co., Ltd. Multilayer printed wiring board and manufacturing method of the multilayer printed wiring board
US20100000087A1 (en) * 2004-10-27 2010-01-07 Ibiden Co., Ltd. Multilayer printed wiring board and manufacturing method of the multilayer printed wiring board
EP1806956A1 (en) * 2004-10-27 2007-07-11 Ibiden Co., Ltd. Multilayer printed wiring board and method for manufacturing multilayer printed wiring board
EP1806956A4 (en) * 2004-10-27 2007-11-21 Ibiden Co Ltd Multilayer printed wiring board and method for manufacturing multilayer printed wiring board
US8737087B2 (en) 2004-10-27 2014-05-27 Ibiden Co., Ltd. Multilayer printed wiring board and manufacturing method of multilayer printed wiring board
US7626829B2 (en) 2004-10-27 2009-12-01 Ibiden Co., Ltd. Multilayer printed wiring board and manufacturing method of the multilayer printed wiring board
US8353103B2 (en) 2004-10-27 2013-01-15 Ibiden Co., Ltd. Manufacturing method of multilayer printed wiring board
US20080099931A1 (en) * 2005-08-31 2008-05-01 Micron Technology, Inc. Interconnecting substrates for microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices
US20070045834A1 (en) * 2005-08-31 2007-03-01 Micron Technology, Inc. Interconnecting substrates for microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices
US7915726B2 (en) 2005-08-31 2011-03-29 Micron Technology, Inc. Interconnecting substrates for microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices
US7326591B2 (en) 2005-08-31 2008-02-05 Micron Technology, Inc. Interconnecting substrates for microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices

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Publication number Publication date Type
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AS Assignment

Owner name: ORIENT SEMICONDUCTOR ELECTRONICS LIMITED, TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HUANG, FU-YU;CHUANG, CHIN-HUI;TSENG, YA-SHIN;AND OTHERS;REEL/FRAME:013474/0730

Effective date: 20021017